commit 06b99d7e1812cf6aae832b9a11de9d31cef54b65 Author: Andrey Perminov Date: Thu Apr 16 15:40:31 2020 -0700 Initial commit Change-Id: I532af5014d3392fb525487a4894673405cf6fe42 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a6424b5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +out +.cproject +.project diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..bc10cf9 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,45 @@ +{ + "files.associations": { + }, + "C_Cpp.default.systemIncludePath": [ + "/usr/lib/gcc/arm-none-eabi/7.3.1/include", + "/usr/lib/gcc/arm-none-eabi/7.3.1/include-fixed", + "/usr/arm-none-eabi/include", + ], + + "C_Cpp.default.includePath": [ + "${workspaceFolder}/BMLite_example/inc", + "${workspaceFolder}/hcp/inc", + "${workspaceFolder}/HAL_Driver/inc", + "${workspaceFolder}/HAL_Driver/sdk", + "${workspaceFolder}/HAL_Driver/sdk/components", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/scheduler", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/timer", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/strerror", + "${workspaceFolder}/HAL_Driver/sdk/components/toolchain/cmsis/include", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/util", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/balloc", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/ringbuf", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/fifo", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/bsp", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/log", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/uart", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/button", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/experimental_section_vars", + "${workspaceFolder}/HAL_Driver/sdk/integration/nrfx/legacy", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/delay", + "${workspaceFolder}/HAL_Driver/sdk/integration/nrfx", + "${workspaceFolder}/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd", + "${workspaceFolder}/HAL_Driver/sdk/external/segger_rtt", + "${workspaceFolder}/HAL_Driver/sdk/components/boards", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/memobj", + "${workspaceFolder}/HAL_Driver/sdk/modules/nrfx/drivers/include", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/log/src", + "${workspaceFolder}/HAL_Driver/sdk/external/fprintf", + "${workspaceFolder}/HAL_Driver/sdk/components/libraries/atomic", + "${workspaceFolder}/HAL_Driver/sdk/modules/nrfx", + "${workspaceFolder}/HAL_Driver/sdk/modules/nrfx/hal", + "${workspaceFolder}/HAL_Driver/sdk/modules/nrfx/mdk", + + ] +} \ No newline at end of file diff --git a/BMLite_example/Makefile b/BMLite_example/Makefile new file mode 100644 index 0000000..687ad59 --- /dev/null +++ b/BMLite_example/Makefile @@ -0,0 +1,109 @@ +# Copyright (c) 2020 Fingerprint Cards AB +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + + +# Make sure that 'all' target become default target +.DEFAULT_GOAL := all + +PRODUCT := bmlite_demo + +#PATH := /work/devtools/gcc-arm-hf/bin:$(PATH) + +CC := arm-none-eabi-gcc + +# Setup paths +OUT := out +DEPTH := +HCP_PATH := ../hcp +MCUHAL_PATH := ../HAL_Driver + +# Main target +TARGET := $(OUT)/$(PRODUCT) + +# Common flags +CFLAGS +=\ + -std=c99 \ + -Wall \ + -fdata-sections \ + -ffunction-sections \ + -MMD \ + -MP \ + -Wextra \ + -Werror \ + -mcpu=cortex-m4 \ + -mthumb \ + -g \ + + #-Og\ + +# -g3\ + +# ifeq ($(FPU),soft) +# CFLAGS +=\ +# -mfloat-abi=soft +# else +CFLAGS +=\ + -mfloat-abi=hard \ + -mfpu=fpv4-sp-d16 +# endif + + + + +# C source files +C_SRCS = $(wildcard src/*.c) + +# Include directories +PATH_INC += inc + +C_INC = $(addprefix -I,$(PATH_INC)) + +# Include HCP +include $(HCP_PATH)/hcp.mk +include $(MCUHAL_PATH)/nordic.mk + +# Object files and search paths +VPATH += $(sort $(dir $(C_SRCS))) +OBJECTS = $(patsubst %.c,$(OUT)/obj/%.o,$(notdir $(C_SRCS))) + +# Dependency files +DEP := $(OBJECTS:.o=.d) +DEP_CFLAGS=$(OUT)/dep_cflags.txt + +all: $(TARGET) + +# Create binary from object files and external libraries +$(TARGET): $(OBJECTS) $(DEP_CFLAGS) $(S_SRCS) + @mkdir -p $(@D) + $(CC) $(CFLAGS) $(C_INC) $(S_SRCS) $(OBJECTS) $(LDFLAGS) -o $@ + +# Compile source files +$(OUT)/obj/%.o: %.c $(DEP_CFLAGS) + @mkdir -p $(dir $@) + $(CC) $(CFLAGS) $(C_INC) -o $@ -c $< + +# Detect changes in CFLAGS +$(DEP_CFLAGS): force + @mkdir -p $(dir $@) + @echo '$(CFLAGS)' | cmp -s - $@ || echo '$(CFLAGS)' > $@ + +-include $(DEP) + +# Empty rule for dep files, they will be created when compiling +%.d: ; + +clean: + rm -rf $(OUT) + +.PHONY: clean force diff --git a/BMLite_example/inc/bep_host_if.h b/BMLite_example/inc/bep_host_if.h new file mode 100644 index 0000000..b05033d --- /dev/null +++ b/BMLite_example/inc/bep_host_if.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BEP_HOST_IF_H +#define BEP_HOST_IF_H + +/** + * @file bep_host_if.h + * @brief BEP Host Interface API + */ + +#include +#include +#include "fpc_bep_types.h" +#include "fpc_com_chain.h" + +#define REMOVE_ID_ALL_TEMPLATES 0U + +/** + * @brief Sends HCP commands for capturing an image in Bio MCU + * + * @param[in] chain HCP com chain + * @param[in] timeout Timeout in ms + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_capture(fpc_com_chain_t *chain, uint16_t timeout); + +/** + * @brief Sends HCP commands for enrolling a finger in Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_enroll_finger(fpc_com_chain_t *chain); + +/** + * @brief Sends HCP commands for identifying a finger in Bio MCU + * + * @param[in] chain HCP com chain + * @param[out] template_id Template id that was identified (only valid if match is true) + * @param[out] match True if match + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_identify_finger(fpc_com_chain_t *chain, uint16_t *template_id, bool *match); + + +/** + * @brief Sends HCP commands for saving template of an enrolled finger in Bio MCU + * + * @param[in] chain HCP com chain + * @param[in] template_id Template id to save + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_save_template(fpc_com_chain_t *chain, uint16_t template_id); + +/** + * @brief Remove template(s) stored + * + * @param[in] chain HCP com chain + * @param[in] template_id template id to remove, if =REMOVE_ID_ALL_TEMPLATES removes all templates + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_delete_template(fpc_com_chain_t *chain, uint16_t template_id); + +/** + * @brief Gets all template ids from Bio MCU + * + * @param[in] chain HCP com chain + * @param[out] template_ids Should be allocated by the caller for storing template ids and should + * have capacity to hold bio_get_template_count + * @param[in] nof_templates This should be acquired using bio_get_template_count + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_get_template_ids(fpc_com_chain_t *chain, uint16_t *template_ids, + uint32_t nof_templates); + +/** + * @brief Get the number of templates in Bio MCU + * + * @param[in] chain HCP com chain + * @param[out] template_count + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_get_template_count(fpc_com_chain_t *chain, uint32_t *template_count); + + +/** + * @brief Sends HCP commands for extracting a template from a previously capture image in Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_image_extract(fpc_com_chain_t *chain); + +/** + * @brief Sends HCP commands for getting the image size of a previously capture image in Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_image_get_size(fpc_com_chain_t *chain, uint32_t *size); + +/** + * @brief Sends HCP commands for getting the image data of a previously capture image in Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_image_get(fpc_com_chain_t *chain, uint8_t *data, uint32_t size); + +/** + * @brief Sends HCP commands for fetching the version of the Bio MCU FW + * + * @param[in] chain HCP com chain + * @param[out] version Version string buffer + * @param[out] len Length of version string buffer + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_version(fpc_com_chain_t *chain, char *version, int len); + +/** + * @brief Sends HCP commands for resetting the Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_reset(fpc_com_chain_t *chain); + +/** + * @brief Sends HCP commands for calibrating the sensor in the Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_sensor_calibrate(fpc_com_chain_t *chain); + +/** + * @brief Sends HCP commands for removing the sensor calibration in the Bio MCU + * + * @param[in] chain HCP com chain + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_sensor_calibrate_remove(fpc_com_chain_t *chain); + +/** + * @brief Sends HCP commands for setting the sensor in sleep and waiting for finger in the Bio MCU + * + * @param[in] chain HCP com chain + * @param[in] timeout Timeout in ms + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_sensor_wait_for_finger(fpc_com_chain_t *chain, uint16_t timeout); + +/** + * @brief Sends HCP commands that returns when finger is not on the sensor in the Bio MCU + * + * @param[in] chain HCP com chain + * @param[in] timeout Timeout in ms + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t bep_sensor_wait_finger_not_present(fpc_com_chain_t *chain, uint16_t timeout); + +#endif /* BEP_HOST_IF_H */ diff --git a/BMLite_example/inc/com_app_cleartext.h b/BMLite_example/inc/com_app_cleartext.h new file mode 100644 index 0000000..0c9a972 --- /dev/null +++ b/BMLite_example/inc/com_app_cleartext.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file com_app_cleartext.h + * @brief TODO + */ + +#ifndef COM_APP_CLEARTEXT_H +#define COM_APP_CLEARTEXT_H + +#include "fpc_com_chain.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * Sends a packet over the physical link in blocking mode. + * + * @param packet Packet to transmit. + * @param chain The transmit chain to use. + * @return ::fpc_com_result_t + */ +fpc_com_result_t com_app_clr_transmit(fpc_com_chain_t *chain); + +/** + * Receives a packet from the physical link. + * + * @param packet Packet to populate. + * @param chain The transmit chain to use. + * @return ::fpc_com_result_t + */ +fpc_com_result_t com_app_clr_receive(fpc_com_chain_t *chain); + +/** + * @brief Returns the overhead of the layer. + * @return Overhead size in bytes. + */ +uint16_t com_app_clr_get_overhead(uint16_t *offset); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* COM_APP_CLEARTEXT_H */ diff --git a/BMLite_example/inc/com_common.h b/BMLite_example/inc/com_common.h new file mode 100644 index 0000000..83ef972 --- /dev/null +++ b/BMLite_example/inc/com_common.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * 04/14/2020: Added SPI interfcae support + */ + + +#ifndef COM_COMMON_H +#define COM_COMMON_H + +/** + * @file com_common.h + * @brief Communication common interface. + */ + +#include +#include + +#include "fpc_bep_types.h" +#include "fpc_hcp_common.h" +#include "fpc_com_chain.h" + +/** + * @brief Allocates or assigns memory for arguments during HCP packet reassembly. + + * @param[in] cmd HCP command. + * @param[in] arg HCP argument. + * @param[in] size size of allocation. + * @param[out] free_data Should data be freed by caller. + * @param[in] context User defined context pointer. + * + * @return Pointer to allocation or NULL if allocation failed. + */ +void *argument_allocator(fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size, bool *free_data, + void *context); + +/** + * @brief Frees memory for arguments during HCP packet destruction. + * + * @param[in] cmd HCP Command. + * @param[in] arg_data Argument data. + * @param[in] context User defined context pointer. + */ +void argument_free(fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, void *context); + +/** + * @brief Prints packet information to the log. + * + * @param[in] packet Packet to print. + * @param[in] msg Optional message to print. Set NULL if not needed. + */ +void print_packet(fpc_hcp_packet_t *packet, const char *msg); + +/** + * @brief Initialize the chain used during communication with the host. + * + * @param[in, out] chain The chain structure to populate. + * @param[in] buffer The buffer to use during communication. + * @param[in] size An array of two sizes, one for the TX buffer size and one for the RX. + * @param[in] context Application context. + * @param[in] spi_enabled Use SPI instead of COM. + */ +void init_com_chain(fpc_com_chain_t *chain, uint8_t *buffer, uint16_t size[2], void *context); + +/** + * @brief Convert a COM result from HCP to a BEP result. + * + * @param[in] result COM result to convert. + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t com_to_bep_result(fpc_com_result_t result); + +/** + * @brief Allocate and add data to an argument. + * + * @param[in, out] cmd Command to add argument to. + * @param[in] arg Argument to add. + * @param[in] data Data to copy to allocated memory. + * @param[in] size Size of data. + * @return ::fpc_bep_result_t + */ +fpc_bep_result_t arg_add(fpc_hcp_packet_t *cmd, fpc_hcp_arg_t arg, const void *data, uint16_t size); + +#endif /* COM_COMMON_H */ diff --git a/BMLite_example/inc/fpc_bep_types.h b/BMLite_example/inc/fpc_bep_types.h new file mode 100644 index 0000000..e9a187e --- /dev/null +++ b/BMLite_example/inc/fpc_bep_types.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FPC_BEP_TYPES_H +#define FPC_BEP_TYPES_H + +#include + +/** + * @file fpc_bep_types.h + * @brief Biometric Embedded Platform types. + * + * This is the common types used by Biometric Embedded Platform (BEP) library. + * + * @note This is a work-in-progress specification. Implementers are informed + * that this API may change without providing any backward compatibility. + * However it is FPC's ambition that the API shall remain compatible between + * releases. + */ + +/** @brief Common result returned by BEP functions. */ +typedef enum { + /** No errors occurred. */ + FPC_BEP_RESULT_OK = 0, + /** General error. */ + FPC_BEP_RESULT_GENERAL_ERROR = -1, + /** Internal error. */ + FPC_BEP_RESULT_INTERNAL_ERROR = -2, + /** Invalid argument. */ + FPC_BEP_RESULT_INVALID_ARGUMENT = -3, + /** The functionality is not implemented. */ + FPC_BEP_RESULT_NOT_IMPLEMENTED = -4, + /** The operation was cancelled. */ + FPC_BEP_RESULT_CANCELLED = -5, + /** Out of memory. */ + FPC_BEP_RESULT_NO_MEMORY = -6, + /** Resources are not available. */ + FPC_BEP_RESULT_NO_RESOURCE = -7, + /** An I/O error occurred. */ + FPC_BEP_RESULT_IO_ERROR = -8, + /** Sensor is broken. */ + FPC_BEP_RESULT_BROKEN_SENSOR = -9, + /** The operation cannot be performed in the current state. */ + FPC_BEP_RESULT_WRONG_STATE = -10, + /** The operation timed out. */ + FPC_BEP_RESULT_TIMEOUT = -11, + /** The ID is not unique. */ + FPC_BEP_RESULT_ID_NOT_UNIQUE = -12, + /** The ID is not found. */ + FPC_BEP_RESULT_ID_NOT_FOUND = -13, + /** The format is invalid. */ + FPC_BEP_RESULT_INVALID_FORMAT = -14, + /** An image capture error occurred. */ + FPC_BEP_RESULT_IMAGE_CAPTURE_ERROR = -15, + /** Sensor hardware id or sensor configuration mismatch. */ + FPC_BEP_RESULT_SENSOR_MISMATCH = -16, + /** Invalid parameter. */ + FPC_BEP_RESULT_INVALID_PARAMETER = -17, + /** Missing Template. */ + FPC_BEP_RESULT_MISSING_TEMPLATE = -18, + /** Invalid Calibration.*/ + FPC_BEP_RESULT_INVALID_CALIBRATION = -19, + /** Calibration/template storage not formatted.*/ + FPC_BEP_RESULT_STORAGE_NOT_FORMATTED = -20, + /** Sensor hasn't been initialized. */ + FPC_BEP_RESULT_SENSOR_NOT_INITIALIZED = -21, + /** Enroll fail after too many bad images. */ + FPC_BEP_RESULT_TOO_MANY_BAD_IMAGES = -22, + /** Cryptographic operation failed. */ + FPC_BEP_RESULT_CRYPTO_ERROR = -23, + /** The functionality is not supported. */ + FPC_BEP_RESULT_NOT_SUPPORTED = -24, + /** Finger not stable during image capture. */ + FPC_BEP_FINGER_NOT_STABLE = -25, + /** The functionality could not be used before it's initialized. */ + FPC_BEP_RESULT_NOT_INITIALIZED = -26, +} fpc_bep_result_t; + +#endif /* FPC_BEP_TYPES_H */ diff --git a/BMLite_example/inc/fpc_crc.h b/BMLite_example/inc/fpc_crc.h new file mode 100644 index 0000000..9c01afa --- /dev/null +++ b/BMLite_example/inc/fpc_crc.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FPC_CRC_H +#define FPC_CRC_H + +/** + * @file fpc_crc.h + * @brief Functionality for calculating CRC-32. + */ + +#include + +/** + * @brief Calculates CRC-32 value for the data in the buffer. + * + * @param crc Accumulated CRC-32 value, must be 0 on first call. + * @param buf Buffer with data to calculate CRC-32 for. + * @param size Size of buffer in number of bytes. + * @return CRC-32 value for the data in buffer. + */ +uint32_t fpc_crc(uint32_t crc, const void *buf, uint32_t size); + +#endif /* FPC_CRC_H */ diff --git a/BMLite_example/inc/platform.h b/BMLite_example/inc/platform.h new file mode 100644 index 0000000..1962de3 --- /dev/null +++ b/BMLite_example/inc/platform.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_H +#define PLATFORM_H + +/** + * @file platform.h + * @brief Platform specific function interface + */ + +#include +#include +#include + +#include "fpc_com_result.h" + +/** + * @brief LED colors. + * + * Different LED colors. + */ +typedef enum { + BMLITE_LED_STATUS_READY = 0, + BMLITE_LED_STATUS_MATCH, + BMLITE_LED_STATUS_NOMATCH, + BMLITE_LED_STATUS_WAITTOUCH, + BMLITE_LED_STATUS_STARTENROLL, + BMLITE_LED_STATUS_FINISHENROLL, + BMLITE_LED_STATUS_DELETE_TEMPLATES +} platform_led_status_t; + +/** + * @brief Initializes board functions + * + * @param[in] speed_hz Baudrate. + */ +bool platform_init(uint32_t speed_hz); + +/** + * @brief Does BM-Lite HW Reset + * + */ +void platform_bmlite_reset(void); + +/** + * @brief Sends data over communication port in blocking mode. + * + * @param[in] size Number of bytes to send. + * @param[in] data Data buffer to send. + * @param[in] timeout Timeout in ms. Use 0 for infinity. + * + * @return ::fpc_com_result_t + */ +fpc_com_result_t platform_bmlite_send(uint16_t size, const uint8_t *data, uint32_t timeout, + void *session); + +/** + * @brief Receives data from communication port in blocking mode. + * + * @param[in] size Number of bytes to receive. + * @param[in, out] data Data buffer to fill. + * @param[in] timeout Timeout in ms. Use 0 for infinity. + * + * @return ::fpc_com_result_t + */ +fpc_com_result_t platform_bmlite_receive(uint16_t size, uint8_t *data, uint32_t timeout, + void *session); + +/** + * @brief Initializes timebase. Starts system tick counter. + */ +void platform_timebase_init(void); + +/** + * @brief Reads the system tick counter. + * + * @return Tick count since platform_timebase_init() call. [ms] + */ +uint32_t platform_timebase_get_tick(void); + +/** + * @brief Busy wait. + * + * @param[in] ms Time to wait [ms]. + * 0 => return immediately + * 1 => wait at least 1ms etc. + */ +void platform_timebase_busy_wait(uint32_t ms); + +/** + * @brief Get time in micro seconds + * + * @return time in us. + */ +uint32_t platform_get_time(void); + +/** + * @brief Stops execution if a debug interface is attached. + */ +void platform_halt_if_debug(void); + +/** + * @brief Performs a software reset. + */ +void platform_sw_reset(void) __attribute__((__noreturn__)); + +/** + * @brief Set LED to a given color and display status. + * + * @param[in] color Color of RGB LED. + * @param[in] status Status of LED. + */ +void platform_set_led(platform_led_status_t color); + +/** + * @brief Get button press time. + * + * @return Button press time in milli seconds. + */ +uint32_t platform_get_button_press_time(void); + +#endif /* PLATFORM_H */ diff --git a/BMLite_example/src/bep_host_if.c b/BMLite_example/src/bep_host_if.c new file mode 100644 index 0000000..b3911be --- /dev/null +++ b/BMLite_example/src/bep_host_if.c @@ -0,0 +1,542 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file bep_host_if.c + * @brief BEP Host Interface implementation. + */ + +#include +#include +#include + +#include "fpc_bep_types.h" +#include "fpc_hcp_common.h" +#include "fpc_com_result.h" +#include "fpc_hcp.h" +#include "platform.h" +#include "com_common.h" + +#include "bep_host_if.h" + +/** Returns the number of elements in an array. */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#define RECEIVE_TIMEOUT 10 + +#ifdef DEBUG +#define log_debug(format, ...) printf(format, ##__VA_ARGS__) +#else +#define log_debug(format, ...) +#endif +// #define log_info(format, ...) printf(format, ##__VA_ARGS__) +// #define log_error(format, ...) printf(format, ##__VA_ARGS__) + +#define log_info(format, ...) +#define log_error(format, ...) + + + +/** Maximum attempts for capture image */ +static const uint8_t MAX_CAPTURE_ATTEMPTS = 15U; +static const uint16_t CAPTURE_TIMEOUT = 3000; + + +/** + * @brief Helper function for sending HCP commands + * + * @param chain HCP communication chain + * @param command_id command to send + * @param arg_key1 first key to add to the command + * @param arg_data1 first argument data to add + * @param arg_data1_length first data length of argument data + * @param arg_key2 second key to add to the command + * @param arg_data2 second argument data to add + * @param arg_data2_length second data length of argument data + * @return ::fpc_bep_result_t + */ +static fpc_bep_result_t send_command_args2(fpc_com_chain_t *chain, fpc_hcp_cmd_t command_id, + fpc_hcp_arg_t arg_key1, void *arg_data1, uint16_t arg_data1_length, + fpc_hcp_arg_t arg_key2, void *arg_data2, uint16_t arg_data2_length) +{ + fpc_hcp_packet_t command; + fpc_bep_result_t bep_result; + fpc_com_result_t com_result; + fpc_hcp_arg_data_t args_tx[10] = {{ 0 }}; + + memset(&command, 0x0, sizeof(command)); + command.arguments = args_tx; + command.num_args = ARRAY_SIZE(args_tx); + command.id = command_id; + + if (arg_key1 != ARG_NONE) { + if (!fpc_hcp_arg_add(&command, arg_key1, arg_data1_length, false, arg_data1)) { + log_error("%s:%u Could not add arg:%u\n", __func__, __LINE__, arg_key1); + bep_result = FPC_BEP_RESULT_NO_MEMORY; + goto exit; + } + } + + if (arg_key2 != ARG_NONE) { + if (!fpc_hcp_arg_add(&command, arg_key2, arg_data2_length, false, arg_data2)) { + log_error("%s:%u Could not add arg:%u\n", __func__, __LINE__, arg_key2); + bep_result = FPC_BEP_RESULT_NO_MEMORY; + goto exit; + } + } + + com_result = fpc_hcp_transmit(&command, chain); + bep_result = com_to_bep_result(com_result); + + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u ERROR %d\n", __func__, __LINE__, bep_result); + } + +exit: + fpc_hcp_free(chain, &command); + + return bep_result; +} + +static fpc_bep_result_t send_command_no_args(fpc_com_chain_t *chain, fpc_hcp_cmd_t command_id) +{ + return send_command_args2(chain, command_id, ARG_NONE, NULL, 0, ARG_NONE, NULL, 0); +} + +static fpc_bep_result_t send_command(fpc_com_chain_t *chain, fpc_hcp_cmd_t command_id, + fpc_hcp_arg_t arg_key, void *arg_data, uint16_t arg_data_length) +{ + return send_command_args2(chain, command_id, arg_key, arg_data, arg_data_length, + ARG_NONE, NULL, 0); +} + +/** + * @brief Helper function for receiving HCP commands + + * @param command_id command to send + * @param arg_key1 first key to receive + * @param arg_data1 first argument data + * @param arg_data1_length first argument data length + * @param arg_key2 second key to receive + * @param arg_data2 second argument data + * @param arg_data2_length second argument + * @return ::fpc_bep_result_t + */ +static fpc_bep_result_t receive_result_args2(fpc_com_chain_t *chain, + fpc_hcp_arg_t arg_key1, void *arg_data1, uint16_t arg_data1_length, + fpc_hcp_arg_t arg_key2, void *arg_data2, uint16_t arg_data2_length) +{ + fpc_hcp_packet_t response; + fpc_hcp_arg_data_t args_rx[10] = {{ 0 }}; + fpc_bep_result_t bep_result = FPC_BEP_RESULT_GENERAL_ERROR; + fpc_hcp_arg_data_t *arg_data; + + memset(&response, 0x0, sizeof(fpc_hcp_cmd_t)); + response.arguments = args_rx; + response.num_args = ARRAY_SIZE(args_rx); + + do { + fpc_com_result_t com_result = fpc_hcp_receive(&response, chain); + bep_result = com_to_bep_result(com_result); + } while (bep_result == FPC_BEP_RESULT_TIMEOUT); + + if (bep_result != FPC_BEP_RESULT_OK) { + goto exit; + } + + /* Check bep result first */ + arg_data = fpc_hcp_arg_get(&response, ARG_RESULT); + if (arg_data) { + bep_result = *(int8_t *)arg_data->data; + } else { + log_error("%s Result argument missing\n", __func__); + bep_result = FPC_BEP_RESULT_INVALID_ARGUMENT; + } + if (bep_result != FPC_BEP_RESULT_OK) { + goto exit; + } + + /* Get first argument */ + if (arg_key1 != ARG_NONE) { + arg_data = fpc_hcp_arg_get(&response, arg_key1); + if (arg_data && arg_data->size <= arg_data1_length) { + memcpy(arg_data1, arg_data->data, arg_data->size); + } else { + log_error("%s %d argument missing\n", __func__, arg_key1); + bep_result = FPC_BEP_RESULT_INVALID_ARGUMENT; + goto exit; + } + } + + /* Get second argument */ + if (arg_key2 != ARG_NONE) { + arg_data = fpc_hcp_arg_get(&response, arg_key2); + if (arg_data && arg_data->size <= arg_data2_length) { + memcpy(arg_data2, arg_data->data, arg_data->size); + } else { + /* Not an error since the second argument is optional */ + log_debug("%s %d argument missing\n", __func__, arg_key2); + } + } + +exit: + fpc_hcp_free(chain, &response); + + return bep_result; +} + +static fpc_bep_result_t receive_result_no_args(fpc_com_chain_t *chain) +{ + return receive_result_args2(chain, ARG_NONE, NULL, 0, ARG_NONE, NULL, 0); +} + +static fpc_bep_result_t receive_result_args1(fpc_com_chain_t *chain, + fpc_hcp_arg_t arg_key, void *arg_data, uint16_t arg_data_length) +{ + return receive_result_args2(chain, arg_key, arg_data, arg_data_length, ARG_NONE, NULL, 0); +} + + +fpc_bep_result_t bep_capture(fpc_com_chain_t *chain, uint16_t timeout) +{ + fpc_bep_result_t bep_result; + + log_info("Put finger on sensor\n"); + + /* Capture finger down */ + bep_result = send_command(chain, CMD_CAPTURE, ARG_TIMEOUT, &timeout, sizeof(timeout)); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u Error transmitting CMD_CAPTURE\n", __func__, __LINE__); + return bep_result; + } + + platform_set_led(BMLITE_LED_STATUS_WAITTOUCH); + bep_result = receive_result_no_args(chain); + platform_set_led(BMLITE_LED_STATUS_READY); + + return bep_result; +} + +fpc_bep_result_t bep_enroll_finger(fpc_com_chain_t *chain) +{ + uint32_t samples_remaining = 0; + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + bool enroll_done = false; + + /* Enroll start */ + bep_result = send_command(chain, CMD_ENROLL, ARG_START, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s, ERROR line:%u\n", __func__, __LINE__); + goto exit; + } + + bep_result = receive_result_no_args(chain); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + goto exit; + } + + for (uint8_t i = 0; i < MAX_CAPTURE_ATTEMPTS; ++i) { + + bep_result = bep_capture(chain, CAPTURE_TIMEOUT); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Capture failed\n"); + break; + } + + log_info("Capture done. Remove finger from sensor\n"); + + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving, result=%d\n", __func__, __LINE__, bep_result); + continue; + } + + /* Enroll add */ + bep_result = send_command(chain, CMD_ENROLL, ARG_ADD, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + continue; + } + + bep_result = receive_result_args1(chain, ARG_COUNT, &samples_remaining, + sizeof(samples_remaining)); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + continue; + } + + log_info("Enroll samples remaining: %d\n", samples_remaining); + + if (samples_remaining == 0U) { + enroll_done = true; + break; + } + + bep_result = send_command(chain, CMD_WAIT, ARG_FINGER_UP, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + continue; + } + + /* Wait for finger to be lifted from sensor */ + bep_result = receive_result_no_args(chain); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + continue; + } + } + + bep_result = send_command(chain, CMD_ENROLL, ARG_FINISH, NULL, 0); + if (bep_result == FPC_BEP_RESULT_OK) { + bep_result = receive_result_no_args(chain); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + } + } + +exit: + return (!enroll_done) ? FPC_BEP_RESULT_GENERAL_ERROR : bep_result; +} + +fpc_bep_result_t bep_identify_finger(fpc_com_chain_t *chain, uint16_t *template_id, bool *match) +{ + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + + *match = false; + + bep_result = bep_capture(chain, CAPTURE_TIMEOUT); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Capture failed result=%d\n", bep_result); + return bep_result; + } + + log_info("Capture done. Remove finger from sensor\n"); + + bep_result = bep_image_extract(chain); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Extract failed\n"); + return bep_result; + } + + bep_result = send_command(chain, CMD_IDENTIFY, ARG_NONE, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Identify failed\n"); + return bep_result; + } + + bep_result = receive_result_args2(chain, ARG_MATCH, match, sizeof(bool), + ARG_ID, template_id, sizeof(uint16_t)); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Identify failed\n"); + return bep_result; + } + + return bep_result; +} + +fpc_bep_result_t bep_save_template(fpc_com_chain_t *chain, uint16_t template_id) +{ + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + + bep_result = send_command_args2(chain, CMD_TEMPLATE, ARG_SAVE, NULL, 0, ARG_ID, &template_id, + sizeof(template_id)); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_delete_template(fpc_com_chain_t *chain, uint16_t template_id) +{ + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + + if (template_id == REMOVE_ID_ALL_TEMPLATES) { + bep_result = send_command_args2(chain, CMD_STORAGE_TEMPLATE, ARG_DELETE, NULL, 0, + ARG_ALL, NULL, 0); + } else { + bep_result = send_command_args2(chain, CMD_STORAGE_TEMPLATE, ARG_DELETE, NULL, 0, + ARG_ID, &template_id, sizeof(template_id)); + } + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_get_template_count(fpc_com_chain_t *chain, uint32_t *template_count) +{ + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + + bep_result = send_command(chain, CMD_STORAGE_TEMPLATE, ARG_COUNT, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u ERROR sending CMD_STORAGE_TEMPLATE\n", __func__, __LINE__); + return bep_result; + } + + bep_result = receive_result_args1(chain, ARG_COUNT, template_count, sizeof(template_count[0])); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + return bep_result; + } + + return bep_result; +} + +fpc_bep_result_t bep_get_template_ids(fpc_com_chain_t *chain, uint16_t *template_ids, + uint32_t nof_templates) +{ + fpc_bep_result_t bep_result = FPC_BEP_RESULT_OK; + + bep_result = send_command(chain, CMD_STORAGE_TEMPLATE, ARG_ID, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u ERROR sending CMD_STORAGE_TEMPLATE\n", __func__, __LINE__); + return bep_result; + } + + bep_result = receive_result_args1(chain, ARG_DATA, template_ids, nof_templates * + sizeof(template_ids[0])); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR receiving status=%d\n", __func__, __LINE__, bep_result); + return bep_result; + } + + return bep_result; +} + +fpc_bep_result_t bep_image_extract(fpc_com_chain_t *chain) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_IMAGE, ARG_EXTRACT, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Extract failed\n"); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_image_get_size(fpc_com_chain_t *chain, uint32_t *size) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_IMAGE, ARG_SIZE, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Extract failed\n"); + return bep_result; + } + + log_info("Downloading image data...\n"); + + return receive_result_args1(chain, ARG_SIZE, size, sizeof(size)); +} + +fpc_bep_result_t bep_image_get(fpc_com_chain_t *chain, uint8_t *data, uint32_t size) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_IMAGE, ARG_UPLOAD, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("Extract failed\n"); + return bep_result; + } + + return receive_result_args1(chain, ARG_DATA, data, size); +} + +fpc_bep_result_t bep_version(fpc_com_chain_t *chain, char *version, int len) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command_args2(chain, CMD_INFO, ARG_GET, NULL, 0, ARG_VERSION, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s, ERROR line:%u\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_args1(chain, ARG_VERSION, version, len); +} + +fpc_bep_result_t bep_reset(fpc_com_chain_t *chain) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command_no_args(chain, CMD_RESET); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_sensor_calibrate(fpc_com_chain_t *chain) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command_no_args(chain, CMD_STORAGE_CALIBRATION); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_sensor_calibrate_remove(fpc_com_chain_t *chain) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_STORAGE_CALIBRATION, ARG_DELETE, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_sensor_wait_for_finger(fpc_com_chain_t *chain, uint16_t timeout) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_WAIT, ARG_FINGER_DOWN, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + /* Wait for finger on sensor */ + return receive_result_no_args(chain); +} + +fpc_bep_result_t bep_sensor_wait_finger_not_present(fpc_com_chain_t *chain, uint16_t timeout) +{ + fpc_bep_result_t bep_result; + + bep_result = send_command(chain, CMD_WAIT, ARG_FINGER_UP, NULL, 0); + if (bep_result != FPC_BEP_RESULT_OK) { + log_error("%s:%u, ERROR\n", __func__, __LINE__); + return bep_result; + } + + /* Wait for finger to be lifted from sensor */ + return receive_result_no_args(chain); +} diff --git a/BMLite_example/src/com_app_cleartext.c b/BMLite_example/src/com_app_cleartext.c new file mode 100644 index 0000000..41a5d6d --- /dev/null +++ b/BMLite_example/src/com_app_cleartext.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file com_app_cleartext.c + * @brief TODO + */ + +#include +#include + +#include "com_app_cleartext.h" +#include "fpc_hcp.h" + +fpc_com_result_t com_app_clr_transmit(fpc_com_chain_t *chain) +{ + fpc_com_packet_tsp_t tsp_packet = { 0 }; + uint16_t tsp_offset; + uint16_t link_offset; + + /* Get offsets */ + chain->link_overhead_get(&link_offset); + chain->tsp_overhead_get(&tsp_offset); + + /* Create header */ + tsp_packet.data = chain->phy_mtu_buffer[FPC_COM_CHAIN_TX] + link_offset + tsp_offset; + tsp_packet.size = chain->app_packet_size[FPC_COM_CHAIN_TX]; + tsp_packet.seq_len = chain->private_vars.hcp_seq_len; + tsp_packet.seq_nr = chain->private_vars.hcp_seq_nr; + + return chain->tsp_tx(&tsp_packet, chain); +} + +fpc_com_result_t com_app_clr_receive(fpc_com_chain_t *chain) +{ + fpc_com_result_t result; + fpc_com_packet_tsp_t tsp_packet = { 0 }; + + result = chain->tsp_rx(&tsp_packet, chain); + + chain->app_packet_size[FPC_COM_CHAIN_RX] = tsp_packet.size; + + return result; +} + +uint16_t com_app_clr_get_overhead(uint16_t *offset) +{ + if (offset) { + *offset = 0; + } + + return 0; +} diff --git a/BMLite_example/src/com_common.c b/BMLite_example/src/com_common.c new file mode 100644 index 0000000..7444525 --- /dev/null +++ b/BMLite_example/src/com_common.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * 04/14/2020: Added SPI interfcae support + */ + +/** + * @file com_common.c + * @brief TODO + */ + +#include +#include +#include + +#include "fpc_com_transport.h" +#include "fpc_com_link.h" +#include "fpc_hcp.h" +#include "fpc_crc.h" + +#include "platform.h" +#include "com_app_cleartext.h" +#include "com_common.h" + +#define UNUSED(x) (void)(x) + +__attribute__((weak)) void *argument_allocator(fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size, + bool *free_data, void *context) +{ + void *pointer = NULL; + + UNUSED(cmd); + UNUSED(arg); + UNUSED(context); + + /* Default behavior */ + pointer = malloc(size); + + if (free_data != NULL) { + *free_data = true; + } + + return pointer; +} + +__attribute__((weak)) void argument_free(fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, + void *context) +{ + UNUSED(cmd); + UNUSED(context); + + if (arg_data->free_data) { + free(arg_data->data); + arg_data->data = NULL; + } +} + +__attribute__((weak)) void print_packet(fpc_hcp_packet_t *packet, const char* msg) +{ +#if (FPC_LOG_INCLUDE == 1) + if (!packet) { + fpc_log_app_var(FPC_LOG_LEVEL_INFO, "Invalid argument"); + return; + } + + fpc_log_app_var(FPC_LOG_LEVEL_DEBUG, "%sPacket cmd id=0x%04X", msg != NULL ? msg : "", + packet->id); + + for (int i = 0; i < packet->num_args; ++i) { + if (packet->arguments[i].arg != ARG_NONE) { + fpc_log_app_var(FPC_LOG_LEVEL_DEBUG, "\tArg[%02d]: key=0x%04X, size=%d free=%d", i, + packet->arguments[i].arg, packet->arguments[i].size, + packet->arguments[i].free_data); + } + } +#else + UNUSED(packet); + UNUSED(msg); +#endif +} + +__attribute__((weak)) void init_com_chain(fpc_com_chain_t *chain, uint8_t *buffer, uint16_t size[2], + void *context) +{ + chain->initialized = true; + + /* CRC */ + chain->crc_calc = fpc_crc; + + /* HCP */ + chain->app_tx = com_app_clr_transmit; + chain->app_rx = com_app_clr_receive; + chain->app_overhead_get = com_app_clr_get_overhead; + chain->argument_allocator = argument_allocator; + chain->argument_free = argument_free; + chain->app_packet_size[FPC_COM_CHAIN_TX] = 0; + chain->app_packet_size[FPC_COM_CHAIN_RX] = 0; + chain->app_mtu_buffer[FPC_COM_CHAIN_TX] = NULL; + chain->app_mtu_buffer[FPC_COM_CHAIN_RX] = NULL; + chain->app_mtu_size[FPC_COM_CHAIN_TX] = 0; + chain->app_mtu_size[FPC_COM_CHAIN_RX] = 0; + + /* Transport */ + chain->tsp_tx = fpc_com_transport_transmit; + chain->tsp_rx = fpc_com_transport_receive; + chain->tsp_overhead_get = fpc_com_transport_get_overhead; + + /* Link */ + chain->link_overhead_get = fpc_com_link_get_overhead; + + /* Phy */ + chain->phy_tx = platform_bmlite_send; + chain->phy_rx = platform_bmlite_receive; + + chain->phy_mtu_size[FPC_COM_CHAIN_TX] = size[FPC_COM_CHAIN_TX]; + chain->phy_mtu_size[FPC_COM_CHAIN_RX] = size[FPC_COM_CHAIN_RX]; + chain->phy_mtu_buffer[FPC_COM_CHAIN_TX] = buffer; + chain->phy_mtu_buffer[FPC_COM_CHAIN_RX] = buffer + size[FPC_COM_CHAIN_TX]; + chain->phy_timeout_tx = 2000; + chain->phy_timeout_rx = 2000; + + chain->session = NULL; + chain->context = context; +} + +fpc_bep_result_t com_to_bep_result(fpc_com_result_t result) +{ + fpc_bep_result_t bep_result; + switch (result) { + case FPC_COM_RESULT_OK : + bep_result = FPC_BEP_RESULT_OK; + break; + case FPC_COM_RESULT_NO_MEMORY: + bep_result = FPC_BEP_RESULT_NO_MEMORY; + break; + case FPC_COM_RESULT_INVALID_ARGUMENT: + bep_result = FPC_BEP_RESULT_INVALID_ARGUMENT; + break; + case FPC_COM_RESULT_NOT_IMPLEMENTED: + bep_result = FPC_BEP_RESULT_NOT_IMPLEMENTED; + break; + case FPC_COM_RESULT_IO_ERROR: + bep_result = FPC_BEP_RESULT_IO_ERROR; + break; + case FPC_COM_RESULT_TIMEOUT: + bep_result = FPC_BEP_RESULT_TIMEOUT; + break; + default: + bep_result = FPC_BEP_RESULT_GENERAL_ERROR; + break; + } + return bep_result; +} + +fpc_bep_result_t arg_add(fpc_hcp_packet_t *cmd, fpc_hcp_arg_t arg, const void *data, uint16_t size) +{ + fpc_bep_result_t result = FPC_BEP_RESULT_OK; + uint32_t *pointer; + + if (cmd == NULL || data == NULL || size == 0) { + result = FPC_BEP_RESULT_INVALID_ARGUMENT; + goto exit; + } + + pointer = malloc(size); + if (pointer == NULL) { + result = FPC_BEP_RESULT_NO_MEMORY; + goto exit; + } + + memcpy(pointer, data, size); + if (fpc_hcp_arg_add(cmd, arg, size, true, pointer) == false) { + free(pointer); + result = FPC_BEP_RESULT_NO_RESOURCE; + } + +exit: + return result; +} diff --git a/BMLite_example/src/fpc_crc.c b/BMLite_example/src/fpc_crc.c new file mode 100644 index 0000000..c16ed1d --- /dev/null +++ b/BMLite_example/src/fpc_crc.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file fpc_crc.c + * @brief CRC32 calculation. + */ + +#include + +#include "fpc_crc.h" + +/** + * The constants here are for the CRC-32 generator polynomial, as defined in + * the Microsoft Systems Journal, March 1995, pp. 107-108. + */ +static const uint32_t crc32_table[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t fpc_crc(uint32_t crc, const void *buf, uint32_t size) +{ + const uint8_t *p; + + p = buf; + crc = crc ^ ~0U; + + while (size--) { + crc = crc32_table[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + } + return crc ^ ~0U; +} + diff --git a/BMLite_example/src/main.c b/BMLite_example/src/main.c new file mode 100644 index 0000000..df47b84 --- /dev/null +++ b/BMLite_example/src/main.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Modified by Andrey Perminov for running on microcontrollers + */ + + +/** + * @file main.c + * @brief Main file for FPC BM-Lite Communication example. + */ + +#include +#include +#include +#include +#include + +#include "bep_host_if.h" +#include "com_common.h" +#include "platform.h" +// #include "fpc_hal_interfaces.h" + +int main (int argc, char **argv) +{ + int baudrate = 4000000; + uint8_t buffer[512]; + uint16_t size[2] = { 256, 256 }; + fpc_com_chain_t hcp_chain; + + if(!platform_init(baudrate)) { + platform_halt_if_debug(); + } + + init_com_chain(&hcp_chain, buffer, size, NULL); + hcp_chain.channel = 1; + + { + char version[100]; + uint16_t template_id; + uint32_t current_id = 0; + bool match; + + memset(version, 0, 100); + fpc_bep_result_t res = bep_version(&hcp_chain, version, 99); + if (res == FPC_BEP_RESULT_OK) + { + printf("%s\n", version); + } + + platform_set_led(BMLITE_LED_STATUS_READY); + + while (1) + { + uint32_t btn_time = platform_get_button_press_time(); + if (btn_time < 200) { + // nothing hapened + } else if (btn_time < 5000) { + // Enroll + platform_set_led(BMLITE_LED_STATUS_STARTENROLL); + platform_timebase_busy_wait(500); + res = bep_enroll_finger(&hcp_chain); + res = bep_save_template(&hcp_chain, current_id++); + platform_set_led(BMLITE_LED_STATUS_STARTENROLL); + platform_timebase_busy_wait(500); + } else { + // Erase All templates + platform_set_led(BMLITE_LED_STATUS_DELETE_TEMPLATES); + platform_timebase_busy_wait(500); + res = bep_delete_template(&hcp_chain, REMOVE_ID_ALL_TEMPLATES); + } + res = bep_identify_finger(&hcp_chain, &template_id, &match); + if (res != FPC_BEP_RESULT_OK) + continue; + if (match) { + platform_set_led(BMLITE_LED_STATUS_MATCH); + } else { + platform_set_led(BMLITE_LED_STATUS_NOMATCH); + } + platform_timebase_busy_wait(500); + } + } +} diff --git a/HAL_Driver/CMSIS/Include/arm_common_tables.h b/HAL_Driver/CMSIS/Include/arm_common_tables.h new file mode 100755 index 0000000..d5d7241 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/HAL_Driver/CMSIS/Include/arm_const_structs.h b/HAL_Driver/CMSIS/Include/arm_const_structs.h new file mode 100755 index 0000000..54595f5 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/HAL_Driver/CMSIS/Include/arm_math.h b/HAL_Driver/CMSIS/Include/arm_math.h new file mode 100755 index 0000000..580cbbd --- /dev/null +++ b/HAL_Driver/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + +#elif defined __CSMC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + static __INLINE uint32_t __CLZ( + q31_t data); + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + } +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + } +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/HAL_Driver/CMSIS/Include/cmsis_armcc.h b/HAL_Driver/CMSIS/Include/cmsis_armcc.h new file mode 100755 index 0000000..f2bb66a --- /dev/null +++ b/HAL_Driver/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/HAL_Driver/CMSIS/Include/cmsis_armcc_V6.h b/HAL_Driver/CMSIS/Include/cmsis_armcc_V6.h new file mode 100755 index 0000000..d714e9b --- /dev/null +++ b/HAL_Driver/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/HAL_Driver/CMSIS/Include/cmsis_gcc.h b/HAL_Driver/CMSIS/Include/cmsis_gcc.h new file mode 100755 index 0000000..d868f2e --- /dev/null +++ b/HAL_Driver/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/HAL_Driver/CMSIS/Include/core_cm0.h b/HAL_Driver/CMSIS/Include/core_cm0.h new file mode 100755 index 0000000..fdee521 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_cm0plus.h b/HAL_Driver/CMSIS/Include/core_cm0plus.h new file mode 100755 index 0000000..7614450 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_cm3.h b/HAL_Driver/CMSIS/Include/core_cm3.h new file mode 100755 index 0000000..34ed84c --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_cm4.h b/HAL_Driver/CMSIS/Include/core_cm4.h new file mode 100755 index 0000000..01cb73b --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_cm7.h b/HAL_Driver/CMSIS/Include/core_cm7.h new file mode 100755 index 0000000..20963c1 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cm7.h @@ -0,0 +1,2512 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_cmFunc.h b/HAL_Driver/CMSIS/Include/core_cmFunc.h new file mode 100755 index 0000000..ca319a5 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/HAL_Driver/CMSIS/Include/core_cmInstr.h b/HAL_Driver/CMSIS/Include/core_cmInstr.h new file mode 100755 index 0000000..a0a5064 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/HAL_Driver/CMSIS/Include/core_cmSimd.h b/HAL_Driver/CMSIS/Include/core_cmSimd.h new file mode 100755 index 0000000..4d76bf9 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/HAL_Driver/CMSIS/Include/core_sc000.h b/HAL_Driver/CMSIS/Include/core_sc000.h new file mode 100755 index 0000000..ea16bf3 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/Include/core_sc300.h b/HAL_Driver/CMSIS/Include/core_sc300.h new file mode 100755 index 0000000..820cef4 --- /dev/null +++ b/HAL_Driver/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/HAL_Driver/CMSIS/dsp/GCC/libarm_cortexM4lf_math.a b/HAL_Driver/CMSIS/dsp/GCC/libarm_cortexM4lf_math.a new file mode 100755 index 0000000..1ad5280 Binary files /dev/null and b/HAL_Driver/CMSIS/dsp/GCC/libarm_cortexM4lf_math.a differ diff --git a/HAL_Driver/config/sdk_config.h b/HAL_Driver/config/sdk_config.h new file mode 100644 index 0000000..250240e --- /dev/null +++ b/HAL_Driver/config/sdk_config.h @@ -0,0 +1,11816 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif +// Application + +//========================================================== +// APP_SHUTDOWN_HANDLER_PRIORITY - Application shutdown observer priority. +#ifndef APP_SHUTDOWN_HANDLER_PRIORITY +#define APP_SHUTDOWN_HANDLER_PRIORITY 1 +#endif + +// +//========================================================== + +// Board Support + +//========================================================== +// BSP_BTN_BLE_ENABLED - bsp_btn_ble - Button Control for BLE + + +#ifndef BSP_BTN_BLE_ENABLED +#define BSP_BTN_BLE_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_BLE + +//========================================================== +// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module + + +#ifndef BLE_ADVERTISING_ENABLED +#define BLE_ADVERTISING_ENABLED 0 +#endif + +// BLE_DB_DISCOVERY_ENABLED - ble_db_discovery - Database discovery module + + +#ifndef BLE_DB_DISCOVERY_ENABLED +#define BLE_DB_DISCOVERY_ENABLED 1 +#endif + +// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands + + +#ifndef BLE_DTM_ENABLED +#define BLE_DTM_ENABLED 0 +#endif + +// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library + + +#ifndef BLE_RACP_ENABLED +#define BLE_RACP_ENABLED 0 +#endif + +// NRF_BLE_GATT_ENABLED - nrf_ble_gatt - GATT module + + +#ifndef NRF_BLE_GATT_ENABLED +#define NRF_BLE_GATT_ENABLED 1 +#endif + +// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) +//========================================================== +#ifndef NRF_BLE_QWR_ENABLED +#define NRF_BLE_QWR_ENABLED 0 +#endif +// NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. +#ifndef NRF_BLE_QWR_MAX_ATTR +#define NRF_BLE_QWR_MAX_ATTR 0 +#endif + +// + +// NRF_BLE_SCAN_ENABLED - nrf_ble_scan - Scanning Module +//========================================================== +#ifndef NRF_BLE_SCAN_ENABLED +#define NRF_BLE_SCAN_ENABLED 1 +#endif +// NRF_BLE_SCAN_BUFFER - Data length for an advertising set. +#ifndef NRF_BLE_SCAN_BUFFER +#define NRF_BLE_SCAN_BUFFER 31 +#endif + +// NRF_BLE_SCAN_NAME_MAX_LEN - Maximum size for the name to search in the advertisement report. +#ifndef NRF_BLE_SCAN_NAME_MAX_LEN +#define NRF_BLE_SCAN_NAME_MAX_LEN 32 +#endif + +// NRF_BLE_SCAN_SHORT_NAME_MAX_LEN - Maximum size of the short name to search for in the advertisement report. +#ifndef NRF_BLE_SCAN_SHORT_NAME_MAX_LEN +#define NRF_BLE_SCAN_SHORT_NAME_MAX_LEN 32 +#endif + +// NRF_BLE_SCAN_SCAN_INTERVAL - Scanning interval. Determines the scan interval in units of 0.625 millisecond. +#ifndef NRF_BLE_SCAN_SCAN_INTERVAL +#define NRF_BLE_SCAN_SCAN_INTERVAL 160 +#endif + +// NRF_BLE_SCAN_SCAN_DURATION - Duration of a scanning session in units of 10 ms. Range: 0x0001 - 0xFFFF (10 ms to 10.9225 ms). If set to 0x0000, the scanning continues until it is explicitly disabled. +#ifndef NRF_BLE_SCAN_SCAN_DURATION +#define NRF_BLE_SCAN_SCAN_DURATION 0 +#endif + +// NRF_BLE_SCAN_SCAN_WINDOW - Scanning window. Determines the scanning window in units of 0.625 millisecond. +#ifndef NRF_BLE_SCAN_SCAN_WINDOW +#define NRF_BLE_SCAN_SCAN_WINDOW 80 +#endif + +// NRF_BLE_SCAN_MIN_CONNECTION_INTERVAL - Determines minimum connection interval in milliseconds. +#ifndef NRF_BLE_SCAN_MIN_CONNECTION_INTERVAL +#define NRF_BLE_SCAN_MIN_CONNECTION_INTERVAL 7.5 +#endif + +// NRF_BLE_SCAN_MAX_CONNECTION_INTERVAL - Determines maximum connection interval in milliseconds. +#ifndef NRF_BLE_SCAN_MAX_CONNECTION_INTERVAL +#define NRF_BLE_SCAN_MAX_CONNECTION_INTERVAL 30 +#endif + +// NRF_BLE_SCAN_SLAVE_LATENCY - Determines the slave latency in counts of connection events. +#ifndef NRF_BLE_SCAN_SLAVE_LATENCY +#define NRF_BLE_SCAN_SLAVE_LATENCY 0 +#endif + +// NRF_BLE_SCAN_SUPERVISION_TIMEOUT - Determines the supervision time-out in units of 10 millisecond. +#ifndef NRF_BLE_SCAN_SUPERVISION_TIMEOUT +#define NRF_BLE_SCAN_SUPERVISION_TIMEOUT 4000 +#endif + +// NRF_BLE_SCAN_SCAN_PHY - PHY to scan on. + +// <0=> BLE_GAP_PHY_AUTO +// <1=> BLE_GAP_PHY_1MBPS +// <2=> BLE_GAP_PHY_2MBPS +// <4=> BLE_GAP_PHY_CODED +// <255=> BLE_GAP_PHY_NOT_SET + +#ifndef NRF_BLE_SCAN_SCAN_PHY +#define NRF_BLE_SCAN_SCAN_PHY 1 +#endif + +// NRF_BLE_SCAN_FILTER_ENABLE - Enabling filters for the Scanning Module. +//========================================================== +#ifndef NRF_BLE_SCAN_FILTER_ENABLE +#define NRF_BLE_SCAN_FILTER_ENABLE 1 +#endif +// NRF_BLE_SCAN_UUID_CNT - Number of filters for UUIDs. +#ifndef NRF_BLE_SCAN_UUID_CNT +#define NRF_BLE_SCAN_UUID_CNT 1 +#endif + +// NRF_BLE_SCAN_NAME_CNT - Number of name filters. +#ifndef NRF_BLE_SCAN_NAME_CNT +#define NRF_BLE_SCAN_NAME_CNT 0 +#endif + +// NRF_BLE_SCAN_SHORT_NAME_CNT - Number of short name filters. +#ifndef NRF_BLE_SCAN_SHORT_NAME_CNT +#define NRF_BLE_SCAN_SHORT_NAME_CNT 0 +#endif + +// NRF_BLE_SCAN_ADDRESS_CNT - Number of address filters. +#ifndef NRF_BLE_SCAN_ADDRESS_CNT +#define NRF_BLE_SCAN_ADDRESS_CNT 0 +#endif + +// NRF_BLE_SCAN_APPEARANCE_CNT - Number of appearance filters. +#ifndef NRF_BLE_SCAN_APPEARANCE_CNT +#define NRF_BLE_SCAN_APPEARANCE_CNT 0 +#endif + +// + +// + +// PEER_MANAGER_ENABLED - peer_manager - Peer Manager +//========================================================== +#ifndef PEER_MANAGER_ENABLED +#define PEER_MANAGER_ENABLED 0 +#endif +// PM_MAX_REGISTRANTS - Number of event handlers that can be registered. +#ifndef PM_MAX_REGISTRANTS +#define PM_MAX_REGISTRANTS 3 +#endif + +// PM_FLASH_BUFFERS - Number of internal buffers for flash operations. +// Decrease this value to lower RAM usage. + +#ifndef PM_FLASH_BUFFERS +#define PM_FLASH_BUFFERS 4 +#endif + +// PM_CENTRAL_ENABLED - Enable/disable central-specific Peer Manager functionality. + + +// Enable/disable central-specific Peer Manager functionality. + +#ifndef PM_CENTRAL_ENABLED +#define PM_CENTRAL_ENABLED 1 +#endif + +// PM_SERVICE_CHANGED_ENABLED - Enable/disable the service changed management for GATT server in Peer Manager. + + +// If not using a GATT server, or using a server wihout a service changed characteristic, +// disable this to save code space. + +#ifndef PM_SERVICE_CHANGED_ENABLED +#define PM_SERVICE_CHANGED_ENABLED 1 +#endif + +// PM_PEER_RANKS_ENABLED - Enable/disable the peer rank management in Peer Manager. + + +// Set this to false to save code space if not using the peer rank API. + +#ifndef PM_PEER_RANKS_ENABLED +#define PM_PEER_RANKS_ENABLED 1 +#endif + +// PM_LESC_ENABLED - Enable/disable LESC support in Peer Manager. + + +// If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space. + +#ifndef PM_LESC_ENABLED +#define PM_LESC_ENABLED 0 +#endif + +// PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager. +//========================================================== +#ifndef PM_RA_PROTECTION_ENABLED +#define PM_RA_PROTECTION_ENABLED 0 +#endif +// PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. +#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM +#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8 +#endif + +// PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL +#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000 +#endif + +// PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. +#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL +#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000 +#endif + +// PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). +// The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period. + +#ifndef PM_RA_PROTECTION_REWARD_PERIOD +#define PM_RA_PROTECTION_REWARD_PERIOD 10000 +#endif + +// + +// PM_HANDLER_SEC_DELAY_MS - Delay before starting security. +// This might be necessary for interoperability reasons, especially as peripheral. + +#ifndef PM_HANDLER_SEC_DELAY_MS +#define PM_HANDLER_SEC_DELAY_MS 0 +#endif + +// + +// +//========================================================== + +// nRF_BLE_Services + +//========================================================== +// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client + + +#ifndef BLE_ANCS_C_ENABLED +#define BLE_ANCS_C_ENABLED 0 +#endif + +// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client + + +#ifndef BLE_ANS_C_ENABLED +#define BLE_ANS_C_ENABLED 0 +#endif + +// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client + + +#ifndef BLE_BAS_C_ENABLED +#define BLE_BAS_C_ENABLED 0 +#endif + +// BLE_BAS_ENABLED - ble_bas - Battery Service +//========================================================== +#ifndef BLE_BAS_ENABLED +#define BLE_BAS_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_BAS_CONFIG_LOG_ENABLED +#define BLE_BAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_BAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_BAS_CONFIG_LOG_LEVEL +#define BLE_BAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_BAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_INFO_COLOR +#define BLE_BAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_BAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_BAS_CONFIG_DEBUG_COLOR +#define BLE_BAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service + + +#ifndef BLE_CSCS_ENABLED +#define BLE_CSCS_ENABLED 0 +#endif + +// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client + + +#ifndef BLE_CTS_C_ENABLED +#define BLE_CTS_C_ENABLED 0 +#endif + +// BLE_DIS_ENABLED - ble_dis - Device Information Service + + +#ifndef BLE_DIS_ENABLED +#define BLE_DIS_ENABLED 0 +#endif + +// BLE_GLS_ENABLED - ble_gls - Glucose Service + + +#ifndef BLE_GLS_ENABLED +#define BLE_GLS_ENABLED 0 +#endif + +// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service + + +#ifndef BLE_HIDS_ENABLED +#define BLE_HIDS_ENABLED 0 +#endif + +// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client + + +#ifndef BLE_HRS_C_ENABLED +#define BLE_HRS_C_ENABLED 0 +#endif + +// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service + + +#ifndef BLE_HRS_ENABLED +#define BLE_HRS_ENABLED 0 +#endif + +// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service + + +#ifndef BLE_HTS_ENABLED +#define BLE_HTS_ENABLED 0 +#endif + +// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client + + +#ifndef BLE_IAS_C_ENABLED +#define BLE_IAS_C_ENABLED 0 +#endif + +// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service +//========================================================== +#ifndef BLE_IAS_ENABLED +#define BLE_IAS_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_IAS_CONFIG_LOG_ENABLED +#define BLE_IAS_CONFIG_LOG_ENABLED 0 +#endif +// BLE_IAS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_IAS_CONFIG_LOG_LEVEL +#define BLE_IAS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_IAS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_INFO_COLOR +#define BLE_IAS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_IAS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_IAS_CONFIG_DEBUG_COLOR +#define BLE_IAS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client + + +#ifndef BLE_LBS_C_ENABLED +#define BLE_LBS_C_ENABLED 0 +#endif + +// BLE_LBS_ENABLED - ble_lbs - LED Button Service + + +#ifndef BLE_LBS_ENABLED +#define BLE_LBS_ENABLED 0 +#endif + +// BLE_LLS_ENABLED - ble_lls - Link Loss Service + + +#ifndef BLE_LLS_ENABLED +#define BLE_LLS_ENABLED 0 +#endif + +// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service + + +#ifndef BLE_NUS_C_ENABLED +#define BLE_NUS_C_ENABLED 1 +#endif + +// BLE_NUS_ENABLED - ble_nus - Nordic UART Service +//========================================================== +#ifndef BLE_NUS_ENABLED +#define BLE_NUS_ENABLED 1 +#endif +// BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef BLE_NUS_CONFIG_LOG_ENABLED +#define BLE_NUS_CONFIG_LOG_ENABLED 1 +#endif +// BLE_NUS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef BLE_NUS_CONFIG_LOG_LEVEL +#define BLE_NUS_CONFIG_LOG_LEVEL 3 +#endif + +// BLE_NUS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_INFO_COLOR +#define BLE_NUS_CONFIG_INFO_COLOR 0 +#endif + +// BLE_NUS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef BLE_NUS_CONFIG_DEBUG_COLOR +#define BLE_NUS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client + + +#ifndef BLE_RSCS_C_ENABLED +#define BLE_RSCS_C_ENABLED 0 +#endif + +// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service + + +#ifndef BLE_RSCS_ENABLED +#define BLE_RSCS_ENABLED 0 +#endif + +// BLE_TPS_ENABLED - ble_tps - TX Power Service + + +#ifndef BLE_TPS_ENABLED +#define BLE_TPS_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Core + +//========================================================== +// NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU +//========================================================== +#ifndef NRF_MPU_LIB_ENABLED +#define NRF_MPU_LIB_ENABLED 0 +#endif +// NRF_MPU_LIB_CLI_CMDS - Enable CLI commands specific to the module. + + +#ifndef NRF_MPU_LIB_CLI_CMDS +#define NRF_MPU_LIB_CLI_CMDS 0 +#endif + +// + +// NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard +//========================================================== +#ifndef NRF_STACK_GUARD_ENABLED +#define NRF_STACK_GUARD_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_SIZE - Size of the stack guard. + +// <5=> 32 bytes +// <6=> 64 bytes +// <7=> 128 bytes +// <8=> 256 bytes +// <9=> 512 bytes +// <10=> 1024 bytes +// <11=> 2048 bytes +// <12=> 4096 bytes + +#ifndef NRF_STACK_GUARD_CONFIG_SIZE +#define NRF_STACK_GUARD_CONFIG_SIZE 7 +#endif + +// + +// +//========================================================== + +// nRF_Crypto + +//========================================================== +// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library. +//========================================================== +#ifndef NRF_CRYPTO_ENABLED +#define NRF_CRYPTO_ENABLED 1 +#endif +// NRF_CRYPTO_ALLOCATOR - Memory allocator + + +// Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK. +// <0=> Default +// <1=> User macros +// <2=> On stack (alloca) +// <3=> C dynamic memory (malloc) +// <4=> SDK Memory Manager (nrf_malloc) + +#ifndef NRF_CRYPTO_ALLOCATOR +#define NRF_CRYPTO_ALLOCATOR 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend. + +// The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED - CC310_BL SHA-256 hash functionality. + + +// CC310_BL backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED - nrf_cc310_bl buffers to RAM before running hash operation + + +// Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian +// Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU! + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310 bl. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend. + +// The CC310 hardware-accelerated cryptography backend (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED - Enable the AES CBC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED - Enable the AES CTR mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED - Enable the AES ECB mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED - Enable the AES CBC_MAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED - Enable the AES CMAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED - Enable the AES CCM mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED - Enable the AES CCM* mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED - Enable the secp160r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED - Enable the secp160r2 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED - Enable the secp192r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED - Enable the secp384r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED - Enable the secp521r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED - Enable the secp160k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED - Enable the secp192k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED - Enable the secp224k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED - Enable the secp256k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED - Enable the Curve25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED - Enable the Ed25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED - CC310 SHA-256 hash functionality. + + +// CC310 backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED - CC310 SHA-512 hash functionality + + +// CC310 backend implementation for SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED - CC310 HMAC using SHA-256 + + +// CC310 backend implementation for HMAC using hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED - CC310 HMAC using SHA-512 + + +// CC310 backend implementation for HMAC using SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED - Enable RNG support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED - Enable the AES EAX mode using Cifra. + + +#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED - Enable the AES CBC mode mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED - Enable the AES CTR mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED - Enable the AES CFB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED - Enable the AES ECB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED - Enable the AES CBC MAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED - Enable the AES CMAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED - Enable the AES CCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED - Enable the AES GCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED - Enable secp384r1 (NIST 384-bit) curve + + +// Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED - Enable secp521r1 (NIST 521-bit) curve + + +// Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED - Enable secp192k1 (Koblitz 192-bit) curve + + +// Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED - Enable secp224k1 (Koblitz 224-bit) curve + + +// Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED - Enable bp256r1 (Brainpool 256-bit) curve + + +// Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED - Enable bp384r1 (Brainpool 384-bit) curve + + +// Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED - Enable bp512r1 (Brainpool 512-bit) curve + + +// Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED - Enable Curve25519 curve + + +// Enable this setting if you need Curve25519 support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED - Enable mbed TLS SHA-256 hash functionality. + + +// mbed TLS backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED - Enable mbed TLS SHA-512 hash functionality. + + +// mbed TLS backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED - Enable mbed TLS HMAC using SHA-256. + + +// mbed TLS backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED - Enable mbed TLS HMAC using SHA-512. + + +// mbed TLS backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend. + +// The nRF HW backend provide access to RNG peripheral in nRF5x devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. + + +// Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding. + +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto. + +// The nRF SW cryptography backend (only used in bootloader context). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED - nRF SW hash backend support for SHA-256 + + +// The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend + +// The Oberon backend +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using Oberon. + + +#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED - Enable secp256r1 curve + + +// Enable this setting if you need secp256r1 curve support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED - Enable Curve25519 ECDH + + +// Enable this setting if you need Curve25519 ECDH support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED - Enable Ed25519 signature scheme + + +// Enable this setting if you need Ed25519 support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED - Oberon SHA-256 hash functionality + + +// Oberon backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED - Oberon SHA-512 hash functionality + + +// Oberon backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED - Oberon HMAC using SHA-256 + + +// Oberon backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED - Oberon HMAC using SHA-512 + + +// Oberon backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend. + +// Enables the nrf_crypto backend for Optiga Trust X devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED - Optiga backend support for RNG + + +// The Optiga backend provide external chip RNG. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED - Optiga backend support for ECC secp256r1 + + +// The Optiga backend provide external chip ECC using secp256r1. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED - Big-endian byte order in raw Curve25519 data + + +// Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0. + +#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED +#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0 +#endif + +// + +// +//========================================================== + +// nRF_DFU + +//========================================================== +// ble_dfu - Device Firmware Update + +//========================================================== +// BLE_DFU_ENABLED - Enable DFU Service. + + +#ifndef BLE_DFU_ENABLED +#define BLE_DFU_ENABLED 0 +#endif + +// NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS - Buttonless DFU supports bonds. + + +#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS +#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer +//========================================================== +#ifndef COMP_ENABLED +#define COMP_ENABLED 0 +#endif +// COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef COMP_CONFIG_REF +#define COMP_CONFIG_REF 1 +#endif + +// COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef COMP_CONFIG_MAIN_MODE +#define COMP_CONFIG_MAIN_MODE 0 +#endif + +// COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef COMP_CONFIG_SPEED_MODE +#define COMP_CONFIG_SPEED_MODE 2 +#endif + +// COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef COMP_CONFIG_HYST +#define COMP_CONFIG_HYST 0 +#endif + +// COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef COMP_CONFIG_ISOURCE +#define COMP_CONFIG_ISOURCE 0 +#endif + +// COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_INPUT +#define COMP_CONFIG_INPUT 0 +#endif + +// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_IRQ_PRIORITY +#define COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer + + +#ifndef EGU_ENABLED +#define EGU_ENABLED 0 +#endif + +// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer +//========================================================== +#ifndef GPIOTE_ENABLED +#define GPIOTE_ENABLED 1 +#endif +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 +#endif + +// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef GPIOTE_CONFIG_IRQ_PRIORITY +#define GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer +//========================================================== +#ifndef I2S_ENABLED +#define I2S_ENABLED 0 +#endif +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef I2S_CONFIG_SCK_PIN +#define I2S_CONFIG_SCK_PIN 31 +#endif + +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef I2S_CONFIG_LRCK_PIN +#define I2S_CONFIG_LRCK_PIN 30 +#endif + +// I2S_CONFIG_MCK_PIN - MCK pin +#ifndef I2S_CONFIG_MCK_PIN +#define I2S_CONFIG_MCK_PIN 255 +#endif + +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef I2S_CONFIG_SDOUT_PIN +#define I2S_CONFIG_SDOUT_PIN 29 +#endif + +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef I2S_CONFIG_SDIN_PIN +#define I2S_CONFIG_SDIN_PIN 28 +#endif + +// I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef I2S_CONFIG_MASTER +#define I2S_CONFIG_MASTER 0 +#endif + +// I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef I2S_CONFIG_FORMAT +#define I2S_CONFIG_FORMAT 0 +#endif + +// I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef I2S_CONFIG_ALIGN +#define I2S_CONFIG_ALIGN 0 +#endif + +// I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef I2S_CONFIG_SWIDTH +#define I2S_CONFIG_SWIDTH 1 +#endif + +// I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef I2S_CONFIG_CHANNELS +#define I2S_CONFIG_CHANNELS 1 +#endif + +// I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef I2S_CONFIG_MCK_SETUP +#define I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef I2S_CONFIG_RATIO +#define I2S_CONFIG_RATIO 2000 +#endif + +// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef I2S_CONFIG_IRQ_PRIORITY +#define I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef I2S_CONFIG_LOG_ENABLED +#define I2S_CONFIG_LOG_ENABLED 0 +#endif +// I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef I2S_CONFIG_LOG_LEVEL +#define I2S_CONFIG_LOG_LEVEL 3 +#endif + +// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_INFO_COLOR +#define I2S_CONFIG_INFO_COLOR 0 +#endif + +// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_DEBUG_COLOR +#define I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer +//========================================================== +#ifndef LPCOMP_ENABLED +#define LPCOMP_ENABLED 0 +#endif +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef LPCOMP_CONFIG_REFERENCE +#define LPCOMP_CONFIG_REFERENCE 3 +#endif + +// LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef LPCOMP_CONFIG_DETECTION +#define LPCOMP_CONFIG_DETECTION 2 +#endif + +// LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_INPUT +#define LPCOMP_CONFIG_INPUT 0 +#endif + +// LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef LPCOMP_CONFIG_HYST +#define LPCOMP_CONFIG_HYST 0 +#endif + +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_IRQ_PRIORITY +#define LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 1 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 1 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 5 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver +//========================================================== +#ifndef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SCK_PIN +#define NRFX_I2S_CONFIG_SCK_PIN 31 +#endif + +// NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef NRFX_I2S_CONFIG_LRCK_PIN +#define NRFX_I2S_CONFIG_LRCK_PIN 30 +#endif + +// NRFX_I2S_CONFIG_MCK_PIN - MCK pin +#ifndef NRFX_I2S_CONFIG_MCK_PIN +#define NRFX_I2S_CONFIG_MCK_PIN 255 +#endif + +// NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDOUT_PIN +#define NRFX_I2S_CONFIG_SDOUT_PIN 29 +#endif + +// NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef NRFX_I2S_CONFIG_SDIN_PIN +#define NRFX_I2S_CONFIG_SDIN_PIN 28 +#endif + +// NRFX_I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef NRFX_I2S_CONFIG_MASTER +#define NRFX_I2S_CONFIG_MASTER 0 +#endif + +// NRFX_I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef NRFX_I2S_CONFIG_FORMAT +#define NRFX_I2S_CONFIG_FORMAT 0 +#endif + +// NRFX_I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef NRFX_I2S_CONFIG_ALIGN +#define NRFX_I2S_CONFIG_ALIGN 0 +#endif + +// NRFX_I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef NRFX_I2S_CONFIG_SWIDTH +#define NRFX_I2S_CONFIG_SWIDTH 1 +#endif + +// NRFX_I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef NRFX_I2S_CONFIG_CHANNELS +#define NRFX_I2S_CONFIG_CHANNELS 1 +#endif + +// NRFX_I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef NRFX_I2S_CONFIG_MCK_SETUP +#define NRFX_I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// NRFX_I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef NRFX_I2S_CONFIG_RATIO +#define NRFX_I2S_CONFIG_RATIO 2000 +#endif + +// NRFX_I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver +//========================================================== +#ifndef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef NRFX_LPCOMP_CONFIG_REFERENCE +#define NRFX_LPCOMP_CONFIG_REFERENCE 3 +#endif + +// NRFX_LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef NRFX_LPCOMP_CONFIG_DETECTION +#define NRFX_LPCOMP_CONFIG_DETECTION 2 +#endif + +// NRFX_LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_INPUT +#define NRFX_LPCOMP_CONFIG_INPUT 0 +#endif + +// NRFX_LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef NRFX_LPCOMP_CONFIG_HYST +#define NRFX_LPCOMP_CONFIG_HYST 0 +#endif + +// NRFX_LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR +#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR +#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE 1 +#endif + +// NRFX_PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE 0 +#endif + +// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module +//========================================================== +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 1 +#endif +// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. + + +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 1 +#endif + +// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. + + +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 1 +#endif + +// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. + + +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 1 +#endif + +// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. + + +#ifndef NRFX_PRS_BOX_3_ENABLED +#define NRFX_PRS_BOX_3_ENABLED 1 +#endif + +// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module. + + +#ifndef NRFX_PRS_BOX_4_ENABLED +#define NRFX_PRS_BOX_4_ENABLED 1 +#endif + +// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif +// NRFX_PWM0_ENABLED - Enable PWM0 instance + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 0 +#endif + +// NRFX_PWM1_ENABLED - Enable PWM1 instance + + +#ifndef NRFX_PWM1_ENABLED +#define NRFX_PWM1_ENABLED 0 +#endif + +// NRFX_PWM2_ENABLED - Enable PWM2 instance + + +#ifndef NRFX_PWM2_ENABLED +#define NRFX_PWM2_ENABLED 0 +#endif + +// NRFX_PWM3_ENABLED - Enable PWM3 instance + + +#ifndef NRFX_PWM3_ENABLED +#define NRFX_PWM3_ENABLED 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver +//========================================================== +#ifndef NRFX_QSPI_ENABLED +#define NRFX_QSPI_ENABLED 0 +#endif +// NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef NRFX_QSPI_CONFIG_SCK_DELAY +#define NRFX_QSPI_CONFIG_SCK_DELAY 1 +#endif + +// NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET +#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef NRFX_QSPI_CONFIG_READOC +#define NRFX_QSPI_CONFIG_READOC 0 +#endif + +// NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef NRFX_QSPI_CONFIG_WRITEOC +#define NRFX_QSPI_CONFIG_WRITEOC 0 +#endif + +// NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef NRFX_QSPI_CONFIG_ADDRMODE +#define NRFX_QSPI_CONFIG_ADDRMODE 0 +#endif + +// NRFX_QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef NRFX_QSPI_CONFIG_MODE +#define NRFX_QSPI_CONFIG_MODE 0 +#endif + +// NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef NRFX_QSPI_CONFIG_FREQUENCY +#define NRFX_QSPI_CONFIG_FREQUENCY 15 +#endif + +// NRFX_QSPI_PIN_SCK - SCK pin value. +#ifndef NRFX_QSPI_PIN_SCK +#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_CSN - CSN pin value. +#ifndef NRFX_QSPI_PIN_CSN +#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO0 - IO0 pin value. +#ifndef NRFX_QSPI_PIN_IO0 +#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO1 - IO1 pin value. +#ifndef NRFX_QSPI_PIN_IO1 +#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO2 - IO2 pin value. +#ifndef NRFX_QSPI_PIN_IO2 +#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_PIN_IO3 - IO3 pin value. +#ifndef NRFX_QSPI_PIN_IO3 +#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY +#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// NRFX_RTC2_ENABLED - Enable RTC2 instance + + +#ifndef NRFX_RTC2_ENABLED +#define NRFX_RTC2_ENABLED 0 +#endif + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION 1 +#endif + +// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE 0 +#endif + +// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 +#endif + +// NRFX_SPIM1_ENABLED - Enable SPIM1 instance + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 +#endif + +// NRFX_SPIM2_ENABLED - Enable SPIM2 instance + + +#ifndef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED 0 +#endif + +// NRFX_SPIM3_ENABLED - Enable SPIM3 instance + + +#ifndef NRFX_SPIM3_ENABLED +#define NRFX_SPIM3_ENABLED 0 +#endif + +// NRFX_SPIM_EXTENDED_ENABLED - Enable extended SPIM features + + +#ifndef NRFX_SPIM_EXTENDED_ENABLED +#define NRFX_SPIM_EXTENDED_ENABLED 0 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// NRFX_SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 0 +#endif + +// NRFX_SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef NRFX_SPIS2_ENABLED +#define NRFX_SPIS2_ENABLED 0 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 1 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 1 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 1 +#endif + +// NRFX_SPI2_ENABLED - Enable SPI2 instance + + +#ifndef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED 0 +#endif + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 0 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 1 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 1 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 1 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// NRFX_TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef NRFX_TIMER3_ENABLED +#define NRFX_TIMER3_ENABLED 0 +#endif + +// NRFX_TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef NRFX_TIMER4_ENABLED +#define NRFX_TIMER4_ENABLED 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 +#endif + +// NRFX_TWIM1_ENABLED - Enable TWIM1 instance + + +#ifndef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// NRFX_TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED 0 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 0 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#endif + +// NRFX_TWI1_ENABLED - Enable TWI1 instance + + +#ifndef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 1 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 1 +#endif + +// NRFX_UARTE1_ENABLED - Enable UARTE1 instance +#ifndef NRFX_UARTE1_ENABLED +#define NRFX_UARTE1_ENABLED 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 1 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver +//========================================================== +#ifndef NRFX_USBD_ENABLED +#define NRFX_USBD_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY +#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_MODE - USBD DMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE +#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// NRFX_USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. + +#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP +#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer +//========================================================== +#ifndef NRF_CLOCK_ENABLED +#define NRF_CLOCK_ENABLED 1 +#endif +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_LF_CAL_ENABLED - Calibration enable for LF Clock Source + + +#ifndef CLOCK_CONFIG_LF_CAL_ENABLED +#define CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer +//========================================================== +#ifndef PDM_ENABLED +#define PDM_ENABLED 0 +#endif +// PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef PDM_CONFIG_MODE +#define PDM_CONFIG_MODE 1 +#endif + +// PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef PDM_CONFIG_EDGE +#define PDM_CONFIG_EDGE 0 +#endif + +// PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef PDM_CONFIG_CLOCK_FREQ +#define PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PDM_CONFIG_IRQ_PRIORITY +#define PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer +//========================================================== +#ifndef POWER_ENABLED +#define POWER_ENABLED 0 +#endif +// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef POWER_CONFIG_IRQ_PRIORITY +#define POWER_CONFIG_IRQ_PRIORITY 6 +#endif + +// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCEN +#define POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCENHV +#define POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver - legacy layer + + +#ifndef PPI_ENABLED +#define PPI_ENABLED 0 +#endif + +// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer +//========================================================== +#ifndef PWM_ENABLED +#define PWM_ENABLED 0 +#endif +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN +#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN +#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN +#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN +#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK +#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE +#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE +#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE +#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef PWM_DEFAULT_CONFIG_STEP_MODE +#define PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// PWM0_ENABLED - Enable PWM0 instance + + +#ifndef PWM0_ENABLED +#define PWM0_ENABLED 0 +#endif + +// PWM1_ENABLED - Enable PWM1 instance + + +#ifndef PWM1_ENABLED +#define PWM1_ENABLED 0 +#endif + +// PWM2_ENABLED - Enable PWM2 instance + + +#ifndef PWM2_ENABLED +#define PWM2_ENABLED 0 +#endif + +// PWM3_ENABLED - Enable PWM3 instance + + +#ifndef PWM3_ENABLED +#define PWM3_ENABLED 0 +#endif + +// + +// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer +//========================================================== +#ifndef QDEC_ENABLED +#define QDEC_ENABLED 0 +#endif +// QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef QDEC_CONFIG_REPORTPER +#define QDEC_CONFIG_REPORTPER 0 +#endif + +// QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef QDEC_CONFIG_SAMPLEPER +#define QDEC_CONFIG_SAMPLEPER 7 +#endif + +// QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_A +#define QDEC_CONFIG_PIO_A 31 +#endif + +// QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_B +#define QDEC_CONFIG_PIO_B 31 +#endif + +// QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_LED +#define QDEC_CONFIG_PIO_LED 31 +#endif + +// QDEC_CONFIG_LEDPRE - LED pre +#ifndef QDEC_CONFIG_LEDPRE +#define QDEC_CONFIG_LEDPRE 511 +#endif + +// QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef QDEC_CONFIG_LEDPOL +#define QDEC_CONFIG_LEDPOL 1 +#endif + +// QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef QDEC_CONFIG_DBFEN +#define QDEC_CONFIG_DBFEN 0 +#endif + +// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef QDEC_CONFIG_SAMPLE_INTEN +#define QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QDEC_CONFIG_IRQ_PRIORITY +#define QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer +//========================================================== +#ifndef QSPI_ENABLED +#define QSPI_ENABLED 0 +#endif +// QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> + + +#ifndef QSPI_CONFIG_SCK_DELAY +#define QSPI_CONFIG_SCK_DELAY 1 +#endif + +// QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. +#ifndef QSPI_CONFIG_XIP_OFFSET +#define QSPI_CONFIG_XIP_OFFSET 0 +#endif + +// QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. + +// <0=> FastRead +// <1=> Read2O +// <2=> Read2IO +// <3=> Read4O +// <4=> Read4IO + +#ifndef QSPI_CONFIG_READOC +#define QSPI_CONFIG_READOC 0 +#endif + +// QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. + +// <0=> PP +// <1=> PP2O +// <2=> PP4O +// <3=> PP4IO + +#ifndef QSPI_CONFIG_WRITEOC +#define QSPI_CONFIG_WRITEOC 0 +#endif + +// QSPI_CONFIG_ADDRMODE - Addressing mode. + +// <0=> 24bit +// <1=> 32bit + +#ifndef QSPI_CONFIG_ADDRMODE +#define QSPI_CONFIG_ADDRMODE 0 +#endif + +// QSPI_CONFIG_MODE - SPI mode. + +// <0=> Mode 0 +// <1=> Mode 1 + +#ifndef QSPI_CONFIG_MODE +#define QSPI_CONFIG_MODE 0 +#endif + +// QSPI_CONFIG_FREQUENCY - Frequency divider. + +// <0=> 32MHz/1 +// <1=> 32MHz/2 +// <2=> 32MHz/3 +// <3=> 32MHz/4 +// <4=> 32MHz/5 +// <5=> 32MHz/6 +// <6=> 32MHz/7 +// <7=> 32MHz/8 +// <8=> 32MHz/9 +// <9=> 32MHz/10 +// <10=> 32MHz/11 +// <11=> 32MHz/12 +// <12=> 32MHz/13 +// <13=> 32MHz/14 +// <14=> 32MHz/15 +// <15=> 32MHz/16 + +#ifndef QSPI_CONFIG_FREQUENCY +#define QSPI_CONFIG_FREQUENCY 15 +#endif + +// QSPI_PIN_SCK - SCK pin value. +#ifndef QSPI_PIN_SCK +#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_CSN - CSN pin value. +#ifndef QSPI_PIN_CSN +#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO0 - IO0 pin value. +#ifndef QSPI_PIN_IO0 +#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO1 - IO1 pin value. +#ifndef QSPI_PIN_IO1 +#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO2 - IO2 pin value. +#ifndef QSPI_PIN_IO2 +#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_PIN_IO3 - IO3 pin value. +#ifndef QSPI_PIN_IO3 +#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED +#endif + +// QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef QSPI_CONFIG_IRQ_PRIORITY +#define QSPI_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 64 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer +//========================================================== +#ifndef RTC_ENABLED +#define RTC_ENABLED 0 +#endif +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef RTC_DEFAULT_CONFIG_FREQUENCY +#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef RTC_DEFAULT_CONFIG_RELIABLE +#define RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// RTC0_ENABLED - Enable RTC0 instance + + +#ifndef RTC0_ENABLED +#define RTC0_ENABLED 0 +#endif + +// RTC1_ENABLED - Enable RTC1 instance + + +#ifndef RTC1_ENABLED +#define RTC1_ENABLED 0 +#endif + +// RTC2_ENABLED - Enable RTC2 instance + + +#ifndef RTC2_ENABLED +#define RTC2_ENABLED 0 +#endif + +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRF_MAXIMUM_LATENCY_US +#define NRF_MAXIMUM_LATENCY_US 2000 +#endif + +// + +// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer +//========================================================== +#ifndef SAADC_ENABLED +#define SAADC_ENABLED 0 +#endif +// SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef SAADC_CONFIG_RESOLUTION +#define SAADC_CONFIG_RESOLUTION 1 +#endif + +// SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef SAADC_CONFIG_OVERSAMPLE +#define SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef SAADC_CONFIG_LP_MODE +#define SAADC_CONFIG_LP_MODE 0 +#endif + +// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SAADC_CONFIG_IRQ_PRIORITY +#define SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer +//========================================================== +#ifndef SPIS_ENABLED +#define SPIS_ENABLED 0 +#endif +// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// SPIS_DEFAULT_MODE - Mode + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 + +#ifndef SPIS_DEFAULT_MODE +#define SPIS_DEFAULT_MODE 0 +#endif + +// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order + +// <0=> MSB first +// <1=> LSB first + +#ifndef SPIS_DEFAULT_BIT_ORDER +#define SPIS_DEFAULT_BIT_ORDER 0 +#endif + +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef SPIS_DEFAULT_DEF +#define SPIS_DEFAULT_DEF 255 +#endif + +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_ORC 255 +#endif + +// SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef SPIS0_ENABLED +#define SPIS0_ENABLED 0 +#endif + +// SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef SPIS1_ENABLED +#define SPIS1_ENABLED 0 +#endif + +// SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef SPIS2_ENABLED +#define SPIS2_ENABLED 0 +#endif + +// + +// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer +//========================================================== +#ifndef SPI_ENABLED +#define SPI_ENABLED 1 +#endif +// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRF_SPI_DRV_MISO_PULLUP_CFG - MISO PIN pull-up configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG +#define NRF_SPI_DRV_MISO_PULLUP_CFG 1 +#endif + +// SPI0_ENABLED - Enable SPI0 instance +//========================================================== +#ifndef SPI0_ENABLED +#define SPI0_ENABLED 1 +#endif +// SPI0_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI0_USE_EASY_DMA +#define SPI0_USE_EASY_DMA 0 +#endif + +// + +// SPI1_ENABLED - Enable SPI1 instance +//========================================================== +#ifndef SPI1_ENABLED +#define SPI1_ENABLED 0 +#endif +// SPI1_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI1_USE_EASY_DMA +#define SPI1_USE_EASY_DMA 1 +#endif + +// + +// SPI2_ENABLED - Enable SPI2 instance +//========================================================== +#ifndef SPI2_ENABLED +#define SPI2_ENABLED 0 +#endif +// SPI2_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI2_USE_EASY_DMA +#define SPI2_USE_EASY_DMA 1 +#endif + +// + +// + +// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer +//========================================================== +#ifndef TIMER_ENABLED +#define TIMER_ENABLED 1 +#endif +// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY +#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef TIMER_DEFAULT_CONFIG_MODE +#define TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 3 +#endif + +// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef TIMER0_ENABLED +#define TIMER0_ENABLED 1 +#endif + +// TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef TIMER1_ENABLED +#define TIMER1_ENABLED 0 +#endif + +// TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef TIMER2_ENABLED +#define TIMER2_ENABLED 0 +#endif + +// TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef TIMER3_ENABLED +#define TIMER3_ENABLED 0 +#endif + +// TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef TIMER4_ENABLED +#define TIMER4_ENABLED 0 +#endif + +// + +// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer +//========================================================== +#ifndef TWIS_ENABLED +#define TWIS_ENABLED 0 +#endif +// TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef TWIS0_ENABLED +#define TWIS0_ENABLED 0 +#endif + +// TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef TWIS1_ENABLED +#define TWIS1_ENABLED 0 +#endif + +// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef TWIS_NO_SYNC_MODE +#define TWIS_NO_SYNC_MODE 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef TWIS_DEFAULT_CONFIG_ADDR0 +#define TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef TWIS_DEFAULT_CONFIG_ADDR1 +#define TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL +#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL +#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer +//========================================================== +#ifndef TWI_ENABLED +#define TWI_ENABLED 0 +#endif +// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef TWI_DEFAULT_CONFIG_FREQUENCY +#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init + + +#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT +#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 +#endif + +// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// TWI0_ENABLED - Enable TWI0 instance +//========================================================== +#ifndef TWI0_ENABLED +#define TWI0_ENABLED 0 +#endif +// TWI0_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI0_USE_EASY_DMA +#define TWI0_USE_EASY_DMA 0 +#endif + +// + +// TWI1_ENABLED - Enable TWI1 instance +//========================================================== +#ifndef TWI1_ENABLED +#define TWI1_ENABLED 0 +#endif +// TWI1_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI1_USE_EASY_DMA +#define TWI1_USE_EASY_DMA 0 +#endif + +// + +// + +// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer +//========================================================== +#ifndef UART_ENABLED +#define UART_ENABLED 1 +#endif +// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef UART_DEFAULT_CONFIG_HWFC +#define UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef UART_DEFAULT_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA + + +#ifndef UART_EASY_DMA_SUPPORT +#define UART_EASY_DMA_SUPPORT 1 +#endif + +// UART_LEGACY_SUPPORT - Driver supporting Legacy mode + + +#ifndef UART_LEGACY_SUPPORT +#define UART_LEGACY_SUPPORT 1 +#endif + +// UART0_ENABLED - Enable UART0 instance +//========================================================== +#ifndef UART0_ENABLED +#define UART0_ENABLED 1 +#endif +// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA + + +#ifndef UART0_CONFIG_USE_EASY_DMA +#define UART0_CONFIG_USE_EASY_DMA 1 +#endif + +// + +// UART1_ENABLED - Enable UART1 instance +//========================================================== +#ifndef UART1_ENABLED +#define UART1_ENABLED 0 +#endif +// + +// + +// USBD_ENABLED - nrf_drv_usbd - Software Component +//========================================================== +#ifndef USBD_ENABLED +#define USBD_ENABLED 0 +#endif +// USBD_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef USBD_CONFIG_IRQ_PRIORITY +#define USBD_CONFIG_IRQ_PRIORITY 6 +#endif + +// USBD_CONFIG_DMASCHEDULER_MODE - USBD SMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef USBD_CONFIG_DMASCHEDULER_MODE +#define USBD_CONFIG_DMASCHEDULER_MODE 0 +#endif + +// USBD_CONFIG_DMASCHEDULER_ISO_BOOST - Give priority to isochronous transfers + + +// This option gives priority to isochronous transfers. +// Enabling it assures that isochronous transfers are always processed, +// even if multiple other transfers are pending. +// Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm +// function is called, so the option is independent of the algorithm chosen. + +#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST +#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1 +#endif + +// USBD_CONFIG_ISO_IN_ZLP - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready + + +// If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent. +// Else, there will be no response. + +#ifndef USBD_CONFIG_ISO_IN_ZLP +#define USBD_CONFIG_ISO_IN_ZLP 0 +#endif + +// + +// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer +//========================================================== +#ifndef WDT_ENABLED +#define WDT_ENABLED 0 +#endif +// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef WDT_CONFIG_BEHAVIOUR +#define WDT_CONFIG_BEHAVIOUR 1 +#endif + +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef WDT_CONFIG_RELOAD_VALUE +#define WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef WDT_CONFIG_IRQ_PRIORITY +#define WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// + +// +//========================================================== + +// nRF_Drivers_External + +//========================================================== +// NRF_TWI_SENSOR_ENABLED - nrf_twi_sensor - nRF TWI Sensor module + + +#ifndef NRF_TWI_SENSOR_ENABLED +#define NRF_TWI_SENSOR_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_FIFO_ENABLED - app_fifo - Software FIFO implementation + + +#ifndef APP_FIFO_ENABLED +#define APP_FIFO_ENABLED 1 +#endif + +// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher + + +#ifndef APP_GPIOTE_ENABLED +#define APP_GPIOTE_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 1 +#endif +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +// + +// APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI +//========================================================== +#ifndef APP_SDCARD_ENABLED +#define APP_SDCARD_ENABLED 0 +#endif +// APP_SDCARD_SPI_INSTANCE - SPI instance used + +// <0=> 0 +// <1=> 1 +// <2=> 2 + +#ifndef APP_SDCARD_SPI_INSTANCE +#define APP_SDCARD_SPI_INSTANCE 0 +#endif + +// APP_SDCARD_FREQ_INIT - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_INIT +#define APP_SDCARD_FREQ_INIT 67108864 +#endif + +// APP_SDCARD_FREQ_DATA - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_DATA +#define APP_SDCARD_FREQ_DATA 1073741824 +#endif + +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 1 +#endif +// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. + +// <0=> 32768 Hz +// <1=> 16384 Hz +// <3=> 8192 Hz +// <7=> 4096 Hz +// <15=> 2048 Hz +// <31=> 1024 Hz + +#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY +#define APP_TIMER_CONFIG_RTC_FREQUENCY 0 +#endif + +// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY +#define APP_TIMER_CONFIG_IRQ_PRIORITY 6 +#endif + +// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. +// Size of the queue depends on how many timers are used +// in the system, how often timers are started and overall +// system latency. If queue size is too small app_timer calls +// will fail. + +#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE +#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 +#endif + +// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler + + +#ifndef APP_TIMER_CONFIG_USE_SCHEDULER +#define APP_TIMER_CONFIG_USE_SCHEDULER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +// APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. +// Maximum possible timeout that can be set is reduced by safe window. +// Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS. +// Since RTC is not stopped when processor is halted in debugging session, this value +// must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS +// without corrupting app_timer behavior. + +#ifndef APP_TIMER_SAFE_WINDOW_MS +#define APP_TIMER_SAFE_WINDOW_MS 300000 +#endif + +// App Timer Legacy configuration - Legacy configuration. + +//========================================================== +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_CONFIG_SWI_NUMBER - Configure SWI instance used. + + +#ifndef APP_TIMER_CONFIG_SWI_NUMBER +#define APP_TIMER_CONFIG_SWI_NUMBER 0 +#endif + +// +//========================================================== + +// + +// APP_UART_ENABLED - app_uart - UART driver +//========================================================== +#ifndef APP_UART_ENABLED +#define APP_UART_ENABLED 1 +#endif +// APP_UART_DRIVER_INSTANCE - UART instance used + +// <0=> 0 + +#ifndef APP_UART_DRIVER_INSTANCE +#define APP_UART_DRIVER_INSTANCE 0 +#endif + +// + +// APP_USBD_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class + + +#ifndef APP_USBD_AUDIO_ENABLED +#define APP_USBD_AUDIO_ENABLED 0 +#endif + +// APP_USBD_ENABLED - app_usbd - USB Device library +//========================================================== +#ifndef APP_USBD_ENABLED +#define APP_USBD_ENABLED 0 +#endif +// APP_USBD_VID - Vendor ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ + +#ifndef APP_USBD_VID +#define APP_USBD_VID 0 +#endif + +// APP_USBD_PID - Product ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Selected Product ID + +#ifndef APP_USBD_PID +#define APP_USBD_PID 0 +#endif + +// APP_USBD_DEVICE_VER_MAJOR - Device version, major part. <0-99> + + +// Device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MAJOR +#define APP_USBD_DEVICE_VER_MAJOR 1 +#endif + +// APP_USBD_DEVICE_VER_MINOR - Device version, minor part. <0-99> + + +// Device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MINOR +#define APP_USBD_DEVICE_VER_MINOR 0 +#endif + +// APP_USBD_CONFIG_SELF_POWERED - Self-powered device, as opposed to bus-powered. + + +#ifndef APP_USBD_CONFIG_SELF_POWERED +#define APP_USBD_CONFIG_SELF_POWERED 1 +#endif + +// APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps. <0-500> + + +#ifndef APP_USBD_CONFIG_MAX_POWER +#define APP_USBD_CONFIG_MAX_POWER 100 +#endif + +// APP_USBD_CONFIG_POWER_EVENTS_PROCESS - Process power events. + + +// Enable processing power events in USB event handler. + +#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS +#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 +#endif + +// APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue. + +// This is the default configuration when all the events are placed into internal queue. +// Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts. +// Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context. +// Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable. +//========================================================== +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE +#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 +#endif +// APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue. <16-64> + + +// The size of the queue for the events that would be processed in the main loop. + +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE +#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 +#endif + +// APP_USBD_CONFIG_SOF_HANDLING_MODE - Change SOF events handling mode. + + +// Normal queue - SOF events are pushed normally into the event queue. +// Compress queue - SOF events are counted and binded with other events or executed when the queue is empty. +// This prevents the queue from filling up with SOF events. +// Interrupt - SOF events are processed in interrupt. +// <0=> Normal queue +// <1=> Compress queue +// <2=> Interrupt + +#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE +#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1 +#endif + +// + +// APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE - Provide a function that generates timestamps for logs based on the current SOF. + + +// The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. +// Use it when initializing the logger. +// SOF processing is always enabled when this configuration parameter is active. +// Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. +// This means that it works even if the logging in this very module is disabled. + +#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE +#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 +#endif + +// APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor. <31-254> + + +// 31 characters can be stored in the internal USB buffer used for transfers. +// Any value higher than 31 creates an additional buffer just for descriptor strings. + +#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE +#define APP_USBD_CONFIG_DESC_STRING_SIZE 31 +#endif + +// APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED - Enable UTF8 conversion. + + +// Enable UTF8-encoded characters. In normal processing, only ASCII characters are available. + +#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED +#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0 +#endif + +// APP_USBD_STRINGS_LANGIDS - Supported languages identifiers. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of supported languages. +#ifndef APP_USBD_STRINGS_LANGIDS +#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US) +#endif + +// APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_MANUFACTURER +#define APP_USBD_STRING_ID_MANUFACTURER 1 +#endif +// APP_USBD_STRINGS_MANUFACTURER_EXTERN - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN +#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0 +#endif + +// APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of manufacturer names for each defined language. +// Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string. +// Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values. +// Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values. +// Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor. +// Setting string to NULL disables that string. +// The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS. +#ifndef APP_USBD_STRINGS_MANUFACTURER +#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor") +#endif + +// + +// APP_USBD_STRING_ID_PRODUCT - Define product string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_PRODUCT +#define APP_USBD_STRING_ID_PRODUCT 2 +#endif +// APP_USBD_STRINGS_PRODUCT_EXTERN - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN +#define APP_USBD_STRINGS_PRODUCT_EXTERN 0 +#endif + +// APP_USBD_STRINGS_PRODUCT - String descriptor for the product name. + +// Note: This value is not editable in Configuration Wizard. +// List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_PRODUCT +#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product") +#endif + +// + +// APP_USBD_STRING_ID_SERIAL - Define serial number string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_SERIAL +#define APP_USBD_STRING_ID_SERIAL 3 +#endif +// APP_USBD_STRING_SERIAL_EXTERN - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRING_SERIAL_EXTERN +#define APP_USBD_STRING_SERIAL_EXTERN 0 +#endif + +// APP_USBD_STRING_SERIAL - String descriptor for the serial number. + +// Note: This value is not editable in Configuration Wizard. +// Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRING_SERIAL +#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000") +#endif + +// + +// APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_CONFIGURATION +#define APP_USBD_STRING_ID_CONFIGURATION 4 +#endif +// APP_USBD_STRING_CONFIGURATION_EXTERN - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable. + + +#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN +#define APP_USBD_STRING_CONFIGURATION_EXTERN 0 +#endif + +// APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration. + +// Note: This value is not editable in Configuration Wizard. +// Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_CONFIGURATION +#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration") +#endif + +// + +// APP_USBD_STRINGS_USER - Default values for user strings. + +// Note: This value is not editable in Configuration Wizard. +// This value stores all application specific user strings with the default initialization. +// The setup is done by X-macros. +// Expected macro parameters: +// @code +// X(mnemonic, [=str_idx], ...) +// @endcode +// - @c mnemonic: Mnemonic of the string descriptor that would be added to +// @ref app_usbd_string_desc_idx_t enumerator. +// - @c str_idx : String index value, can be set or left empty. +// For example, WinUSB driver requires descriptor to be present on 0xEE index. +// Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...))) +// - @c ... : List of string descriptors for each defined language. +#ifndef APP_USBD_STRINGS_USER +#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1")) +#endif + +// + +// APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class +//========================================================== +#ifndef APP_USBD_HID_ENABLED +#define APP_USBD_HID_ENABLED 0 +#endif +// APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class. <0-255> + + +// 0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification. + +#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE +#define APP_USBD_HID_DEFAULT_IDLE_RATE 0 +#endif + +// APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table. <1-255> + + +// Must be higher than the highest report ID used. + +#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE +#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4 +#endif + +// + +// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic + + +#ifndef APP_USBD_HID_GENERIC_ENABLED +#define APP_USBD_HID_GENERIC_ENABLED 0 +#endif + +// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard + + +#ifndef APP_USBD_HID_KBD_ENABLED +#define APP_USBD_HID_KBD_ENABLED 0 +#endif + +// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse + + +#ifndef APP_USBD_HID_MOUSE_ENABLED +#define APP_USBD_HID_MOUSE_ENABLED 0 +#endif + +// APP_USBD_MSC_ENABLED - app_usbd_msc - USB MSC class + + +#ifndef APP_USBD_MSC_ENABLED +#define APP_USBD_MSC_ENABLED 0 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 0 +#endif +// Pages - Virtual page settings + +// Configure the number of virtual pages to use and their size. +//========================================================== +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection. +// The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual flash page. + + +// Expressed in number of 4-byte words. +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <1024=> 1024 +// <2048=> 2048 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 1024 +#endif + +// FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. +// FDS module stores its data in the last pages of the flash memory. +// By setting this value, you can move flash end address used by the FDS. +// As a result the reserved space can be used by other modules. + +#ifndef FDS_VIRTUAL_PAGES_RESERVED +#define FDS_VIRTUAL_PAGES_RESERVED 0 +#endif + +// +//========================================================== + +// Backend - Backend configuration + +// Configure which nrf_fstorage backend is used by FDS to write to flash. +//========================================================== +// FDS_BACKEND - FDS flash backend. + + +// NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present. +// NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice. +// <1=> NRF_FSTORAGE_NVMC +// <2=> NRF_FSTORAGE_SD + +#ifndef FDS_BACKEND +#define FDS_BACKEND 2 +#endif + +// +//========================================================== + +// Queue - Queue settings + +//========================================================== +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +// Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors. + +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// +//========================================================== + +// CRC - CRC functionality + +//========================================================== +// FDS_CRC_CHECK_ON_READ - Enable CRC checks. + +// Save a record's CRC when it is written to flash and check it when the record is opened. +// Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened. +// Additionally, they will not be garbage collected until they are deleted. +//========================================================== +#ifndef FDS_CRC_CHECK_ON_READ +#define FDS_CRC_CHECK_ON_READ 0 +#endif +// FDS_CRC_CHECK_ON_WRITE - Perform a CRC check on newly written records. + + +// Perform a CRC check on newly written records. +// This setting can be used to make sure that the record data was not altered while being written to flash. +// <1=> Enabled +// <0=> Disabled + +#ifndef FDS_CRC_CHECK_ON_WRITE +#define FDS_CRC_CHECK_ON_WRITE 0 +#endif + +// + +// +//========================================================== + +// Users - Number of users + +//========================================================== +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 4 +#endif + +// +//========================================================== + +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30801920 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 8 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 6 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 5 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 7 +#endif + +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. +// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. +// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 +#endif + +// MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED +#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// MEM_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL +#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// MEM_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_INFO_COLOR +#define MEM_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// MEM_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR +#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +// + +// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module +//========================================================== +#ifndef NRF_BALLOC_ENABLED +#define NRF_BALLOC_ENABLED 1 +#endif +// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS +#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS +#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. + + +#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED +#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_BALLOC_CLI_CMDS +#define NRF_BALLOC_CLI_CMDS 0 +#endif + +// + +// + +// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. +// This is used when capacitive sensor does not use COMP. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 26 +#endif + +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +// USE_COMP - Use the comparator to implement the capacitive sensor driver. + +// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. +//========================================================== +#ifndef USE_COMP +#define USE_COMP 0 +#endif +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of a single measurement can be calculated as +// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). +// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +// + +// + +// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library +//========================================================== +#ifndef NRF_FSTORAGE_ENABLED +#define NRF_FSTORAGE_ENABLED 0 +#endif +// nrf_fstorage - Common settings + +// Common settings to all fstorage implementations +//========================================================== +// NRF_FSTORAGE_PARAM_CHECK_DISABLED - Disable user input validation + + +// If selected, use ASSERT to validate user input. +// This effectively removes user input validation in production code. +// Recommended setting: OFF, only enable this setting if size is a major concern. + +#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED +#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 +#endif + +// +//========================================================== + +// nrf_fstorage_sd - Implementation using the SoftDevice + +// Configuration options for the fstorage implementation using the SoftDevice +//========================================================== +// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations +// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. + +#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE +#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 +#endif + +// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy +// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. +// The SoftDevice might fail to schedule flash access due to high BLE activity. + +#ifndef NRF_FSTORAGE_SD_MAX_RETRIES +#define NRF_FSTORAGE_SD_MAX_RETRIES 8 +#endif + +// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation +// This value must be a multiple of four. +// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. +// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. +// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. + +#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE +#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 +#endif + +// +//========================================================== + +// + +// NRF_GFX_ENABLED - nrf_gfx - GFX module + + +#ifndef NRF_GFX_ENABLED +#define NRF_GFX_ENABLED 0 +#endif + +// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module + + +#ifndef NRF_MEMOBJ_ENABLED +#define NRF_MEMOBJ_ENABLED 1 +#endif + +// NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module +//========================================================== +#ifndef NRF_PWR_MGMT_ENABLED +#define NRF_PWR_MGMT_ENABLED 1 +#endif +// NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. + +// Selected pin will be set when CPU is in sleep mode. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED +#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 +#endif +// NRF_PWR_MGMT_SLEEP_DEBUG_PIN - Pin number + +// <0=> 0 (P0.0) +// <1=> 1 (P0.1) +// <2=> 2 (P0.2) +// <3=> 3 (P0.3) +// <4=> 4 (P0.4) +// <5=> 5 (P0.5) +// <6=> 6 (P0.6) +// <7=> 7 (P0.7) +// <8=> 8 (P0.8) +// <9=> 9 (P0.9) +// <10=> 10 (P0.10) +// <11=> 11 (P0.11) +// <12=> 12 (P0.12) +// <13=> 13 (P0.13) +// <14=> 14 (P0.14) +// <15=> 15 (P0.15) +// <16=> 16 (P0.16) +// <17=> 17 (P0.17) +// <18=> 18 (P0.18) +// <19=> 19 (P0.19) +// <20=> 20 (P0.20) +// <21=> 21 (P0.21) +// <22=> 22 (P0.22) +// <23=> 23 (P0.23) +// <24=> 24 (P0.24) +// <25=> 25 (P0.25) +// <26=> 26 (P0.26) +// <27=> 27 (P0.27) +// <28=> 28 (P0.28) +// <29=> 29 (P0.29) +// <30=> 30 (P0.30) +// <31=> 31 (P0.31) +// <32=> 32 (P1.0) +// <33=> 33 (P1.1) +// <34=> 34 (P1.2) +// <35=> 35 (P1.3) +// <36=> 36 (P1.4) +// <37=> 37 (P1.5) +// <38=> 38 (P1.6) +// <39=> 39 (P1.7) +// <40=> 40 (P1.8) +// <41=> 41 (P1.9) +// <42=> 42 (P1.10) +// <43=> 43 (P1.11) +// <44=> 44 (P1.12) +// <45=> 45 (P1.13) +// <46=> 46 (P1.14) +// <47=> 47 (P1.15) +// <4294967295=> Not connected + +#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN +#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - Enables CPU usage monitor. + + +// Module will trace percentage of CPU usage in one second intervals. + +#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED +#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). +// Shutdown procedure will begin no earlier than after this number of seconds. + +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - Enables FPU event cleaning. + + +#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED +#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 1 +#endif + +// NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - Blocked shutdown procedure will be retried every second. + + +#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY +#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0 +#endif + +// NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - Module will use @ref app_scheduler. + + +#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER +#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 +#endif + +// NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. +// The number of stages of the shutdown process. + +#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT +#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 +#endif + +// + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module +//========================================================== +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif +// NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_QUEUE_CLI_CMDS +#define NRF_QUEUE_CLI_CMDS 0 +#endif + +// + +// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator + + +#ifndef NRF_SECTION_ITER_ENABLED +#define NRF_SECTION_ITER_ENABLED 1 +#endif + +// NRF_SORTLIST_ENABLED - nrf_sortlist - Sorted list + + +#ifndef NRF_SORTLIST_ENABLED +#define NRF_SORTLIST_ENABLED 0 +#endif + +// NRF_SPI_MNGR_ENABLED - nrf_spi_mngr - SPI transaction manager + + +#ifndef NRF_SPI_MNGR_ENABLED +#define NRF_SPI_MNGR_ENABLED 0 +#endif + +// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. + + +#ifndef NRF_STRERROR_ENABLED +#define NRF_STRERROR_ENABLED 1 +#endif + +// NRF_TWI_MNGR_ENABLED - nrf_twi_mngr - TWI transaction manager + + +#ifndef NRF_TWI_MNGR_ENABLED +#define NRF_TWI_MNGR_ENABLED 0 +#endif + +// RETARGET_ENABLED - retarget - Retargeting stdio functions + + +#ifndef RETARGET_ENABLED +#define RETARGET_ENABLED 1 +#endif + +// SLIP_ENABLED - slip - SLIP encoding and decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// TASK_MANAGER_ENABLED - task_manager - Task manager. +//========================================================== +#ifndef TASK_MANAGER_ENABLED +#define TASK_MANAGER_ENABLED 0 +#endif +// TASK_MANAGER_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef TASK_MANAGER_CLI_CMDS +#define TASK_MANAGER_CLI_CMDS 0 +#endif + +// TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created +#ifndef TASK_MANAGER_CONFIG_MAX_TASKS +#define TASK_MANAGER_CONFIG_MAX_TASKS 2 +#endif + +// TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) +#ifndef TASK_MANAGER_CONFIG_STACK_SIZE +#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 +#endif + +// TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED - Enable stack profiling. + + +#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED +#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 +#endif + +// TASK_MANAGER_CONFIG_STACK_GUARD - Configures stack guard. + +// <0=> Disabled +// <4=> 32 bytes +// <5=> 64 bytes +// <6=> 128 bytes +// <7=> 256 bytes +// <8=> 512 bytes + +#ifndef TASK_MANAGER_CONFIG_STACK_GUARD +#define TASK_MANAGER_CONFIG_STACK_GUARD 7 +#endif + +// + +// app_button - buttons handling module + +//========================================================== +// BUTTON_ENABLED - Enables Button module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 1 +#endif + +// BUTTON_HIGH_ACCURACY_ENABLED - Enables GPIOTE high accuracy for buttons + + +#ifndef BUTTON_HIGH_ACCURACY_ENABLED +#define BUTTON_HIGH_ACCURACY_ENABLED 0 +#endif + +// +//========================================================== + +// app_usbd_cdc_acm - USB CDC ACM class + +//========================================================== +// APP_USBD_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library + + +#ifndef APP_USBD_CDC_ACM_ENABLED +#define APP_USBD_CDC_ACM_ENABLED 0 +#endif + +// APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE - Send ZLP on write with same size as endpoint + + +// If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint. +// This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent. + +#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE +#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1 +#endif + +// +//========================================================== + +// nrf_cli - Command line interface + +//========================================================== +// NRF_CLI_ENABLED - Enable/disable the CLI module. + + +#ifndef NRF_CLI_ENABLED +#define NRF_CLI_ENABLED 0 +#endif + +// NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. +#ifndef NRF_CLI_ARGC_MAX +#define NRF_CLI_ARGC_MAX 12 +#endif + +// NRF_CLI_BUILD_IN_CMDS_ENABLED - CLI built-in commands. + + +#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED +#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 +#endif + +// NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. +#ifndef NRF_CLI_CMD_BUFF_SIZE +#define NRF_CLI_CMD_BUFF_SIZE 128 +#endif + +// NRF_CLI_ECHO_STATUS - CLI echo status. If set, echo is ON. + + +#ifndef NRF_CLI_ECHO_STATUS +#define NRF_CLI_ECHO_STATUS 1 +#endif + +// NRF_CLI_WILDCARD_ENABLED - Enable wildcard functionality for CLI commands. + + +#ifndef NRF_CLI_WILDCARD_ENABLED +#define NRF_CLI_WILDCARD_ENABLED 0 +#endif + +// NRF_CLI_METAKEYS_ENABLED - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u + + +#ifndef NRF_CLI_METAKEYS_ENABLED +#define NRF_CLI_METAKEYS_ENABLED 0 +#endif + +// NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. +#ifndef NRF_CLI_PRINTF_BUFF_SIZE +#define NRF_CLI_PRINTF_BUFF_SIZE 23 +#endif + +// NRF_CLI_HISTORY_ENABLED - Enable CLI history mode. +//========================================================== +#ifndef NRF_CLI_HISTORY_ENABLED +#define NRF_CLI_HISTORY_ENABLED 1 +#endif +// NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. +#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE +#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 +#endif + +// NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. +#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT +#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 +#endif + +// + +// NRF_CLI_VT100_COLORS_ENABLED - CLI VT100 colors. + + +#ifndef NRF_CLI_VT100_COLORS_ENABLED +#define NRF_CLI_VT100_COLORS_ENABLED 1 +#endif + +// NRF_CLI_STATISTICS_ENABLED - Enable CLI statistics. + + +#ifndef NRF_CLI_STATISTICS_ENABLED +#define NRF_CLI_STATISTICS_ENABLED 1 +#endif + +// NRF_CLI_LOG_BACKEND - Enable logger backend interface. + + +#ifndef NRF_CLI_LOG_BACKEND +#define NRF_CLI_LOG_BACKEND 1 +#endif + +// NRF_CLI_USES_TASK_MANAGER_ENABLED - Enable CLI to use task_manager + + +#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED +#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 +#endif + +// +//========================================================== + +// nrf_fprintf - fprintf function. + +//========================================================== +// NRF_FPRINTF_ENABLED - Enable/disable fprintf module. + + +#ifndef NRF_FPRINTF_ENABLED +#define NRF_FPRINTF_ENABLED 1 +#endif + +// NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED - For each printed LF, function will add CR. + + +#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED +#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Log + +//========================================================== +// NRF_LOG_BACKEND_RTT_ENABLED - nrf_log_backend_rtt - Log RTT backend +//========================================================== +#ifndef NRF_LOG_BACKEND_RTT_ENABLED +#define NRF_LOG_BACKEND_RTT_ENABLED 1 +#endif +// NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE - Size of buffer for partially processed strings. +// Size of the buffer is a trade-off between RAM usage and processing. +// if buffer is smaller then strings will often be fragmented. +// It is recommended to use size which will fit typical log and only the +// longer one will be fragmented. + +#ifndef NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE +#define NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE 64 +#endif + +// NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS - Period before retrying writing to RTT +#ifndef NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS +#define NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS 1 +#endif + +// NRF_LOG_BACKEND_RTT_TX_RETRY_CNT - Writing to RTT retries. +// If RTT fails to accept any new data after retries +// module assumes that host is not active and on next +// request it will perform only one write attempt. +// On successful writing, module assumes that host is active +// and scheme with retry is applied again. + +#ifndef NRF_LOG_BACKEND_RTT_TX_RETRY_CNT +#define NRF_LOG_BACKEND_RTT_TX_RETRY_CNT 3 +#endif + +// + +// NRF_LOG_ENABLED - nrf_log - Logger +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 1 +#endif +// Log message pool - Configuration of log message pool + +//========================================================== +// NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. +// If a small value is set, then performance of logs processing +// is degraded because data is fragmented. Bigger value impacts +// RAM memory utilization. The size is set to fit a message with +// a timestamp and up to 2 arguments in a single memory object. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE +#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20 +#endif + +// NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects +// If a small value is set, then it may lead to a deadlock +// in certain cases if backend has high latency and holds +// multiple messages for long time. Bigger value impacts +// RAM memory usage. + +#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT +#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8 +#endif + +// +//========================================================== + +// NRF_LOG_ALLOW_OVERFLOW - Configures behavior when circular buffer is full. + + +// If set then oldest logs are overwritten. Otherwise a +// marker is injected informing about overflow. + +#ifndef NRF_LOG_ALLOW_OVERFLOW +#define NRF_LOG_ALLOW_OVERFLOW 1 +#endif + +// NRF_LOG_BUFSIZE - Size of the buffer for storing logs (in bytes). + + +// Must be power of 2 and multiple of 4. +// If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum. +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 +// <2048=> 2048 +// <4096=> 4096 +// <8192=> 8192 +// <16384=> 16384 + +#ifndef NRF_LOG_BUFSIZE +#define NRF_LOG_BUFSIZE 1024 +#endif + +// NRF_LOG_CLI_CMDS - Enable CLI commands for the module. + + +#ifndef NRF_LOG_CLI_CMDS +#define NRF_LOG_CLI_CMDS 0 +#endif + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + + +// Log data is buffered and can be processed in idle. + +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif + +// NRF_LOG_FILTERS_ENABLED - Enable dynamic filtering of logs. + + +#ifndef NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_FILTERS_ENABLED 0 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_STR_PUSH_BUFFER_SIZE - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH. + +// <16=> 16 +// <32=> 32 +// <64=> 64 +// <128=> 128 +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE +#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128 +#endif + +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 2 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 4 +#endif + +// + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + +// Function for getting the timestamp is provided by the user +//========================================================== +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif +// NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. +#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY +#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0 +#endif + +// + +// nrf_log module configuration + +//========================================================== +// nrf_log in nRF_Core + +//========================================================== +// NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED +#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MPU_LIB_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL +#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MPU_LIB_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR +#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MPU_LIB_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR +#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED +#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL +#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_STACK_GUARD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR +#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0 +#endif + +// NRF_STACK_GUARD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR +#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED +#define TASK_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// TASK_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL +#define TASK_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// TASK_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_INFO_COLOR +#define TASK_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// TASK_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR +#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Drivers + +//========================================================== +// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef CLOCK_CONFIG_LOG_ENABLED +#define CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef CLOCK_CONFIG_LOG_LEVEL +#define CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_INFO_COLOR +#define CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_DEBUG_COLOR +#define CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMP_CONFIG_LOG_ENABLED +#define COMP_CONFIG_LOG_ENABLED 0 +#endif +// COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMP_CONFIG_LOG_LEVEL +#define COMP_CONFIG_LOG_LEVEL 3 +#endif + +// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_INFO_COLOR +#define COMP_CONFIG_INFO_COLOR 0 +#endif + +// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_DEBUG_COLOR +#define COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef GPIOTE_CONFIG_LOG_ENABLED +#define GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef GPIOTE_CONFIG_LOG_LEVEL +#define GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_INFO_COLOR +#define GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_DEBUG_COLOR +#define GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef LPCOMP_CONFIG_LOG_ENABLED +#define LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef LPCOMP_CONFIG_LOG_LEVEL +#define LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_INFO_COLOR +#define LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_DEBUG_COLOR +#define LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED +#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0 +#endif +// MAX3421E_HOST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL +#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3 +#endif + +// MAX3421E_HOST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR +#define MAX3421E_HOST_CONFIG_INFO_COLOR 0 +#endif + +// MAX3421E_HOST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR +#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef NRFX_USBD_CONFIG_LOG_ENABLED +#define NRFX_USBD_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_USBD_CONFIG_LOG_LEVEL +#define NRFX_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_INFO_COLOR +#define NRFX_USBD_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR +#define NRFX_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PDM_CONFIG_LOG_ENABLED +#define PDM_CONFIG_LOG_ENABLED 0 +#endif +// PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PDM_CONFIG_LOG_LEVEL +#define PDM_CONFIG_LOG_LEVEL 3 +#endif + +// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_INFO_COLOR +#define PDM_CONFIG_INFO_COLOR 0 +#endif + +// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_DEBUG_COLOR +#define PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PPI_CONFIG_LOG_ENABLED +#define PPI_CONFIG_LOG_ENABLED 0 +#endif +// PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PPI_CONFIG_LOG_LEVEL +#define PPI_CONFIG_LOG_LEVEL 3 +#endif + +// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_INFO_COLOR +#define PPI_CONFIG_INFO_COLOR 0 +#endif + +// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_DEBUG_COLOR +#define PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PWM_CONFIG_LOG_ENABLED +#define PWM_CONFIG_LOG_ENABLED 0 +#endif +// PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PWM_CONFIG_LOG_LEVEL +#define PWM_CONFIG_LOG_LEVEL 3 +#endif + +// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_INFO_COLOR +#define PWM_CONFIG_INFO_COLOR 0 +#endif + +// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_DEBUG_COLOR +#define PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef QDEC_CONFIG_LOG_ENABLED +#define QDEC_CONFIG_LOG_ENABLED 0 +#endif +// QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef QDEC_CONFIG_LOG_LEVEL +#define QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_INFO_COLOR +#define QDEC_CONFIG_INFO_COLOR 0 +#endif + +// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_DEBUG_COLOR +#define QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RNG_CONFIG_LOG_ENABLED +#define RNG_CONFIG_LOG_ENABLED 0 +#endif +// RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RNG_CONFIG_LOG_LEVEL +#define RNG_CONFIG_LOG_LEVEL 3 +#endif + +// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_INFO_COLOR +#define RNG_CONFIG_INFO_COLOR 0 +#endif + +// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_DEBUG_COLOR +#define RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED - Enables logging of random numbers. + + +#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED +#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0 +#endif + +// + +// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RTC_CONFIG_LOG_ENABLED +#define RTC_CONFIG_LOG_ENABLED 0 +#endif +// RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RTC_CONFIG_LOG_LEVEL +#define RTC_CONFIG_LOG_LEVEL 3 +#endif + +// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_INFO_COLOR +#define RTC_CONFIG_INFO_COLOR 0 +#endif + +// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_DEBUG_COLOR +#define RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SAADC_CONFIG_LOG_ENABLED +#define SAADC_CONFIG_LOG_ENABLED 0 +#endif +// SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SAADC_CONFIG_LOG_LEVEL +#define SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_INFO_COLOR +#define SAADC_CONFIG_INFO_COLOR 0 +#endif + +// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_DEBUG_COLOR +#define SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPIS_CONFIG_LOG_ENABLED +#define SPIS_CONFIG_LOG_ENABLED 0 +#endif +// SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPIS_CONFIG_LOG_LEVEL +#define SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_INFO_COLOR +#define SPIS_CONFIG_INFO_COLOR 0 +#endif + +// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_DEBUG_COLOR +#define SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TIMER_CONFIG_LOG_ENABLED +#define TIMER_CONFIG_LOG_ENABLED 0 +#endif +// TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TIMER_CONFIG_LOG_LEVEL +#define TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_INFO_COLOR +#define TIMER_CONFIG_INFO_COLOR 0 +#endif + +// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_DEBUG_COLOR +#define TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWIS_CONFIG_LOG_ENABLED +#define TWIS_CONFIG_LOG_ENABLED 0 +#endif +// TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWIS_CONFIG_LOG_LEVEL +#define TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_INFO_COLOR +#define TWIS_CONFIG_INFO_COLOR 0 +#endif + +// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_DEBUG_COLOR +#define TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWI_CONFIG_LOG_ENABLED +#define TWI_CONFIG_LOG_ENABLED 0 +#endif +// TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWI_CONFIG_LOG_LEVEL +#define TWI_CONFIG_LOG_LEVEL 3 +#endif + +// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_INFO_COLOR +#define TWI_CONFIG_INFO_COLOR 0 +#endif + +// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_DEBUG_COLOR +#define TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef UART_CONFIG_LOG_ENABLED +#define UART_CONFIG_LOG_ENABLED 0 +#endif +// UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef UART_CONFIG_LOG_LEVEL +#define UART_CONFIG_LOG_LEVEL 3 +#endif + +// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_INFO_COLOR +#define UART_CONFIG_INFO_COLOR 0 +#endif + +// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_DEBUG_COLOR +#define UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// USBD_CONFIG_LOG_ENABLED - Enable logging in the module +//========================================================== +#ifndef USBD_CONFIG_LOG_ENABLED +#define USBD_CONFIG_LOG_ENABLED 0 +#endif +// USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef USBD_CONFIG_LOG_LEVEL +#define USBD_CONFIG_LOG_LEVEL 3 +#endif + +// USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_INFO_COLOR +#define USBD_CONFIG_INFO_COLOR 0 +#endif + +// USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef USBD_CONFIG_DEBUG_COLOR +#define USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef WDT_CONFIG_LOG_ENABLED +#define WDT_CONFIG_LOG_ENABLED 0 +#endif +// WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef WDT_CONFIG_LOG_LEVEL +#define WDT_CONFIG_LOG_LEVEL 3 +#endif + +// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_INFO_COLOR +#define WDT_CONFIG_INFO_COLOR 0 +#endif + +// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_DEBUG_COLOR +#define WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Libraries + +//========================================================== +// APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_TIMER_CONFIG_LOG_ENABLED +#define APP_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// APP_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_LOG_LEVEL +#define APP_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL +#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// APP_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_INFO_COLOR +#define APP_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// APP_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_TIMER_CONFIG_DEBUG_COLOR +#define APP_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED +#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL +#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CDC_ACM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR +#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR +#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module. +//========================================================== +#ifndef APP_USBD_CONFIG_LOG_ENABLED +#define APP_USBD_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_CONFIG_LOG_LEVEL +#define APP_USBD_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_INFO_COLOR +#define APP_USBD_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_CONFIG_DEBUG_COLOR +#define APP_USBD_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED +#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_DUMMY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL +#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_DUMMY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR +#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_DUMMY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR +#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED +#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_MSC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL +#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_MSC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR +#define APP_USBD_MSC_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_MSC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR +#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0 +#endif +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0 +#endif + +// APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR +#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED +#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0 +#endif +// NRF_ATFIFO_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_ATFIFO_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR +#define NRF_ATFIFO_CONFIG_INFO_COLOR 0 +#endif + +// NRF_ATFIFO_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR +#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED +#define NRF_BALLOC_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL +#define NRF_BALLOC_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL - Initial severity level if dynamic filtering is enabled. + + +// If module generates a lot of logs, initial log level can +// be decreased to prevent flooding. Severity level can be +// increased on instance basis. +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL +#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3 +#endif + +// NRF_BALLOC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_INFO_COLOR +#define NRF_BALLOC_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BALLOC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR +#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0 +#endif +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0 +#endif + +// NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR +#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_BLE_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR +#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED +#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRF_CLI_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL +#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_CLI_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR +#define NRF_CLI_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRF_CLI_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR +#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED +#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_LIBUARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL +#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_LIBUARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR +#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_LIBUARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR +#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED +#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0 +#endif +// NRF_MEMOBJ_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL +#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_MEMOBJ_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR +#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0 +#endif + +// NRF_MEMOBJ_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR +#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED +#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL +#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_PWR_MGMT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR +#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0 +#endif + +// NRF_PWR_MGMT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR +#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED +#define NRF_QUEUE_CONFIG_LOG_ENABLED 0 +#endif +// NRF_QUEUE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL +#define NRF_QUEUE_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL - Initial severity level if dynamic filtering is enabled + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL +#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3 +#endif + +// NRF_QUEUE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_INFO_COLOR +#define NRF_QUEUE_CONFIG_INFO_COLOR 0 +#endif + +// NRF_QUEUE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR +#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module. +//========================================================== +#ifndef NRF_SDH_ANT_LOG_ENABLED +#define NRF_SDH_ANT_LOG_ENABLED 0 +#endif +// NRF_SDH_ANT_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_ANT_LOG_LEVEL +#define NRF_SDH_ANT_LOG_LEVEL 3 +#endif + +// NRF_SDH_ANT_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_INFO_COLOR +#define NRF_SDH_ANT_INFO_COLOR 0 +#endif + +// NRF_SDH_ANT_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_ANT_DEBUG_COLOR +#define NRF_SDH_ANT_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module. +//========================================================== +#ifndef NRF_SDH_BLE_LOG_ENABLED +#define NRF_SDH_BLE_LOG_ENABLED 1 +#endif +// NRF_SDH_BLE_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_BLE_LOG_LEVEL +#define NRF_SDH_BLE_LOG_LEVEL 3 +#endif + +// NRF_SDH_BLE_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_INFO_COLOR +#define NRF_SDH_BLE_INFO_COLOR 0 +#endif + +// NRF_SDH_BLE_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_BLE_DEBUG_COLOR +#define NRF_SDH_BLE_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module. +//========================================================== +#ifndef NRF_SDH_LOG_ENABLED +#define NRF_SDH_LOG_ENABLED 1 +#endif +// NRF_SDH_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_LOG_LEVEL +#define NRF_SDH_LOG_LEVEL 3 +#endif + +// NRF_SDH_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_INFO_COLOR +#define NRF_SDH_INFO_COLOR 0 +#endif + +// NRF_SDH_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_DEBUG_COLOR +#define NRF_SDH_DEBUG_COLOR 0 +#endif + +// + +// NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module. +//========================================================== +#ifndef NRF_SDH_SOC_LOG_ENABLED +#define NRF_SDH_SOC_LOG_ENABLED 1 +#endif +// NRF_SDH_SOC_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SDH_SOC_LOG_LEVEL +#define NRF_SDH_SOC_LOG_LEVEL 3 +#endif + +// NRF_SDH_SOC_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_INFO_COLOR +#define NRF_SDH_SOC_INFO_COLOR 0 +#endif + +// NRF_SDH_SOC_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SDH_SOC_DEBUG_COLOR +#define NRF_SDH_SOC_DEBUG_COLOR 0 +#endif + +// + +// NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED +#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 +#endif +// NRF_SORTLIST_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL +#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_SORTLIST_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR +#define NRF_SORTLIST_CONFIG_INFO_COLOR 0 +#endif + +// NRF_SORTLIST_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR +#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED +#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0 +#endif +// NRF_TWI_SENSOR_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL +#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3 +#endif + +// NRF_TWI_SENSOR_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR +#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0 +#endif + +// NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR +#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules. +//========================================================== +#ifndef PM_LOG_ENABLED +#define PM_LOG_ENABLED 1 +#endif +// PM_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PM_LOG_LEVEL +#define PM_LOG_LEVEL 3 +#endif + +// PM_LOG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_INFO_COLOR +#define PM_LOG_INFO_COLOR 0 +#endif + +// PM_LOG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PM_LOG_DEBUG_COLOR +#define PM_LOG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// nrf_log in nRF_Serialization + +//========================================================== +// SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED +#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0 +#endif +// SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL +#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3 +#endif + +// SER_HAL_TRANSPORT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR +#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0 +#endif + +// SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR +#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// +//========================================================== + +// +//========================================================== + +// + +// NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED - nrf_log_str_formatter - Log string formatter + + +#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED +#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 +#endif + +// +//========================================================== + +// nRF_NFC + +//========================================================== +// NFC_AC_REC_ENABLED - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder + + +#ifndef NFC_AC_REC_ENABLED +#define NFC_AC_REC_ENABLED 0 +#endif + +// NFC_AC_REC_PARSER_ENABLED - nfc_ac_rec_parser - Alternative Carrier record parser + + +#ifndef NFC_AC_REC_PARSER_ENABLED +#define NFC_AC_REC_PARSER_ENABLED 0 +#endif + +// NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder +//========================================================== +#ifndef NFC_BLE_OOB_ADVDATA_ENABLED +#define NFC_BLE_OOB_ADVDATA_ENABLED 0 +#endif +// ADVANCED_ADVDATA_SUPPORT - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs) + +// <1=> Enabled +// <0=> Disabled + +#ifndef ADVANCED_ADVDATA_SUPPORT +#define ADVANCED_ADVDATA_SUPPORT 0 +#endif + +// + +// NFC_BLE_OOB_ADVDATA_PARSER_ENABLED - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser + + +#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED +#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0 +#endif + +// NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_ENABLED +#define NFC_BLE_PAIR_LIB_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED +#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0 +#endif +// NFC_BLE_PAIR_LIB_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL +#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3 +#endif + +// NFC_BLE_PAIR_LIB_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR +#define NFC_BLE_PAIR_LIB_INFO_COLOR 0 +#endif + +// NFC_BLE_PAIR_LIB_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR +#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0 +#endif + +// + +// NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters. + +//========================================================== +// BLE_NFC_SEC_PARAM_BOND - Enables device bonding. + +// If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled. +//========================================================== +#ifndef BLE_NFC_SEC_PARAM_BOND +#define BLE_NFC_SEC_PARAM_BOND 1 +#endif +// BLE_NFC_SEC_PARAM_KDIST_OWN_ENC - Enables Long Term Key and Master Identification distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_OWN_ID - Enables Identity Resolving Key and Identity Address Information distribution by device. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID +#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ENC - Enables Long Term Key and Master Identification distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1 +#endif + +// BLE_NFC_SEC_PARAM_KDIST_PEER_ID - Enables Identity Resolving Key and Identity Address Information distribution by peer. + + +#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID +#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1 +#endif + +// + +// BLE_NFC_SEC_PARAM_MIN_KEY_SIZE - Minimal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7 +#endif + +// BLE_NFC_SEC_PARAM_MAX_KEY_SIZE - Maximal size of a security key. + +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// <16=> 16 + +#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE +#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16 +#endif + +// +//========================================================== + +// + +// NFC_BLE_PAIR_MSG_ENABLED - nfc_ble_pair_msg - NDEF message for OOB pairing encoder + + +#ifndef NFC_BLE_PAIR_MSG_ENABLED +#define NFC_BLE_PAIR_MSG_ENABLED 0 +#endif + +// NFC_CH_COMMON_ENABLED - nfc_ble_pair_common - OOB pairing common data + + +#ifndef NFC_CH_COMMON_ENABLED +#define NFC_CH_COMMON_ENABLED 0 +#endif + +// NFC_EP_OOB_REC_ENABLED - nfc_ep_oob_rec - EP record for BLE pairing encoder + + +#ifndef NFC_EP_OOB_REC_ENABLED +#define NFC_EP_OOB_REC_ENABLED 0 +#endif + +// NFC_HS_REC_ENABLED - nfc_hs_rec - Handover Select NDEF record encoder + + +#ifndef NFC_HS_REC_ENABLED +#define NFC_HS_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_ENABLED - nfc_le_oob_rec - LE record for BLE pairing encoder + + +#ifndef NFC_LE_OOB_REC_ENABLED +#define NFC_LE_OOB_REC_ENABLED 0 +#endif + +// NFC_LE_OOB_REC_PARSER_ENABLED - nfc_le_oob_rec_parser - LE record parser + + +#ifndef NFC_LE_OOB_REC_PARSER_ENABLED +#define NFC_LE_OOB_REC_PARSER_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_MSG_ENABLED - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED +#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0 +#endif + +// NFC_NDEF_LAUNCHAPP_REC_ENABLED - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag + + +#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED +#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0 +#endif + +// NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module +//========================================================== +#ifndef NFC_NDEF_MSG_ENABLED +#define NFC_NDEF_MSG_ENABLED 0 +#endif +// NFC_NDEF_MSG_TAG_TYPE - NFC Tag Type + +// <2=> Type 2 Tag +// <4=> Type 4 Tag + +#ifndef NFC_NDEF_MSG_TAG_TYPE +#define NFC_NDEF_MSG_TAG_TYPE 2 +#endif + +// + +// NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_ENABLED +#define NFC_NDEF_MSG_PARSER_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED +#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_MSG_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL +#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_MSG_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR +#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_RECORD_ENABLED - nfc_ndef_record - NFC NDEF Record generator module + + +#ifndef NFC_NDEF_RECORD_ENABLED +#define NFC_NDEF_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_ENABLED +#define NFC_NDEF_RECORD_PARSER_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED +#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0 +#endif +// NFC_NDEF_RECORD_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL +#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3 +#endif + +// NFC_NDEF_RECORD_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR +#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_NDEF_TEXT_RECORD_ENABLED - nfc_text_rec - Encoding data for a text record for NFC Tag + + +#ifndef NFC_NDEF_TEXT_RECORD_ENABLED +#define NFC_NDEF_TEXT_RECORD_ENABLED 0 +#endif + +// NFC_NDEF_URI_MSG_ENABLED - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_MSG_ENABLED +#define NFC_NDEF_URI_MSG_ENABLED 0 +#endif + +// NFC_NDEF_URI_REC_ENABLED - nfc_uri_rec - Encoding data for a URI record for NFC Tag + + +#ifndef NFC_NDEF_URI_REC_ENABLED +#define NFC_NDEF_URI_REC_ENABLED 0 +#endif + +// NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data +//========================================================== +#ifndef NFC_T2T_PARSER_ENABLED +#define NFC_T2T_PARSER_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T2T_PARSER_LOG_ENABLED +#define NFC_T2T_PARSER_LOG_ENABLED 0 +#endif +// NFC_T2T_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T2T_PARSER_LOG_LEVEL +#define NFC_T2T_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T2T_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T2T_PARSER_INFO_COLOR +#define NFC_T2T_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_APDU_ENABLED +#define NFC_T4T_APDU_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_APDU_LOG_ENABLED +#define NFC_T4T_APDU_LOG_ENABLED 0 +#endif +// NFC_T4T_APDU_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_APDU_LOG_LEVEL +#define NFC_T4T_APDU_LOG_LEVEL 3 +#endif + +// NFC_T4T_APDU_LOG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_APDU_LOG_COLOR +#define NFC_T4T_APDU_LOG_COLOR 0 +#endif + +// + +// + +// NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED +#define NFC_T4T_CC_FILE_PARSER_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED +#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_CC_FILE_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL +#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_CC_FILE_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR +#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0 +#endif +// NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL +#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3 +#endif + +// NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR +#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0 +#endif + +// + +// APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage +#ifndef APDU_BUFF_SIZE +#define APDU_BUFF_SIZE 250 +#endif + +// CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage +#ifndef CC_STORAGE_BUFF_SIZE +#define CC_STORAGE_BUFF_SIZE 64 +#endif + +// + +// NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0 +#endif +// NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL +#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3 +#endif + +// NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR +#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0 +#endif + +// + +// + +// +//========================================================== + +// nRF_Segger_RTT + +//========================================================== +// segger_rtt - SEGGER RTT + +//========================================================== +// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. +// Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE +// or this value is actually used. It depends on which one is bigger. + +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 512 +#endif + +// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Maximum number of upstream buffers. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 +#endif + +// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of downstream buffer. +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 +#endif + +// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Maximum number of downstream buffers. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 +#endif + +// SEGGER_RTT_CONFIG_DEFAULT_MODE - RTT behavior if the buffer is full. + + +// The following modes are supported: +// - SKIP - Do not block, output nothing. +// - TRIM - Do not block, output as much as fits. +// - BLOCK - Wait until there is space in the buffer. +// <0=> SKIP +// <1=> TRIM +// <2=> BLOCK_IF_FIFO_FULL + +#ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE +#define SEGGER_RTT_CONFIG_DEFAULT_MODE 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_SoftDevice + +//========================================================== +// NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler +//========================================================== +#ifndef NRF_SDH_BLE_ENABLED +#define NRF_SDH_BLE_ENABLED 1 +#endif +// BLE Stack configuration - Stack configuration parameters + +// The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set. +// Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set. +//========================================================== +// NRF_SDH_BLE_GAP_DATA_LENGTH <27-251> + + +// Requested BLE GAP data length to be negotiated. + +#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH +#define NRF_SDH_BLE_GAP_DATA_LENGTH 251 +#endif + +// NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. +#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT +#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0 +#endif + +// NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. +#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT +#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. +// Maximum number of total concurrent connections using the default configuration. + +#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT +#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1 +#endif + +// NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. +// The time set aside for this connection on every connection interval in 1.25 ms units. + +#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH +#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6 +#endif + +// NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. +#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE +#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 247 +#endif + +// NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. +#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE +#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408 +#endif + +// NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. +#ifndef NRF_SDH_BLE_VS_UUID_COUNT +#define NRF_SDH_BLE_VS_UUID_COUNT 1 +#endif + +// NRF_SDH_BLE_SERVICE_CHANGED - Include the Service Changed characteristic in the Attribute Table. + + +#ifndef NRF_SDH_BLE_SERVICE_CHANGED +#define NRF_SDH_BLE_SERVICE_CHANGED 0 +#endif + +// +//========================================================== + +// BLE Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. +// This setting configures the number of priority levels available for BLE event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4 +#endif + +// BLE Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Advertising module. + +#ifndef BLE_ADV_BLE_OBSERVER_PRIO +#define BLE_ADV_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_ANCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Apple Notification Service Client. + +#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO +#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_ANS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Alert Notification Service Client. + +#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO +#define BLE_ANS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service. + +#ifndef BLE_BAS_BLE_OBSERVER_PRIO +#define BLE_BAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Battery Service Client. + +#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO +#define BLE_BAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_BPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Blood Pressure Service. + +#ifndef BLE_BPS_BLE_OBSERVER_PRIO +#define BLE_BPS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection parameters module. + +#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO +#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_CONN_STATE_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Connection State module. + +#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO +#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0 +#endif + +// BLE_CSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service. + +#ifndef BLE_CSCS_BLE_OBSERVER_PRIO +#define BLE_CSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_CTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Current Time Service Client. + +#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO +#define BLE_CTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DB_DISC_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Database Discovery module. + +#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO +#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_BLE_OBSERVER_PRIO +#define BLE_DFU_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_DIS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Device Information Client. + +#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO +#define BLE_DIS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_GLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Glucose Service. + +#ifndef BLE_GLS_BLE_OBSERVER_PRIO +#define BLE_GLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HIDS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Human Interface Device Service. + +#ifndef BLE_HIDS_BLE_OBSERVER_PRIO +#define BLE_HIDS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service. + +#ifndef BLE_HRS_BLE_OBSERVER_PRIO +#define BLE_HRS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HRS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Heart Rate Service Client. + +#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO +#define BLE_HRS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_HTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Health Thermometer Service. + +#ifndef BLE_HTS_BLE_OBSERVER_PRIO +#define BLE_HTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service. + +#ifndef BLE_IAS_BLE_OBSERVER_PRIO +#define BLE_IAS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_IAS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Immediate Alert Service Client. + +#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO +#define BLE_IAS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service. + +#ifndef BLE_LBS_BLE_OBSERVER_PRIO +#define BLE_LBS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LBS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the LED Button Service Client. + +#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO +#define BLE_LBS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LLS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Link Loss Service. + +#ifndef BLE_LLS_BLE_OBSERVER_PRIO +#define BLE_LLS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_LNS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Location Navigation Service. + +#ifndef BLE_LNS_BLE_OBSERVER_PRIO +#define BLE_LNS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Service. + +#ifndef BLE_NUS_BLE_OBSERVER_PRIO +#define BLE_NUS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_NUS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the UART Central Service. + +#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO +#define BLE_NUS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service. + +#ifndef BLE_OTS_BLE_OBSERVER_PRIO +#define BLE_OTS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_OTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Object transfer service client. + +#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO +#define BLE_OTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Service. + +#ifndef BLE_RSCS_BLE_OBSERVER_PRIO +#define BLE_RSCS_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_RSCS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Running Speed and Cadence Client. + +#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO +#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2 +#endif + +// BLE_TPS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the TX Power Service. + +#ifndef BLE_TPS_BLE_OBSERVER_PRIO +#define BLE_TPS_BLE_OBSERVER_PRIO 2 +#endif + +// BSP_BTN_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Button Control module. + +#ifndef BSP_BTN_BLE_OBSERVER_PRIO +#define BSP_BTN_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the NFC pairing library. + +#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO +#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_BMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Bond Management Service. + +#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO +#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_CGMS_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service. + +#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO +#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_ES_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Eddystone module. + +#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO +#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT Service Client. + +#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO +#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_GATT_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the GATT module. + +#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO +#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1 +#endif + +// NRF_BLE_QWR_BLE_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the Queued writes module. + +#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO +#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2 +#endif + +// NRF_BLE_SCAN_OBSERVER_PRIO +// Priority for dispatching the BLE events to the Scanning Module. + +#ifndef NRF_BLE_SCAN_OBSERVER_PRIO +#define NRF_BLE_SCAN_OBSERVER_PRIO 1 +#endif + +// PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. +#ifndef PM_BLE_OBSERVER_PRIO +#define PM_BLE_OBSERVER_PRIO 1 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler +//========================================================== +#ifndef NRF_SDH_ENABLED +#define NRF_SDH_ENABLED 1 +#endif +// Dispatch model + +// This setting configures how Stack events are dispatched to the application. +//========================================================== +// NRF_SDH_DISPATCH_MODEL + + +// NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context. +// NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler. +// NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually. +// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT +// <1=> NRF_SDH_DISPATCH_MODEL_APPSH +// <2=> NRF_SDH_DISPATCH_MODEL_POLLING + +#ifndef NRF_SDH_DISPATCH_MODEL +#define NRF_SDH_DISPATCH_MODEL 0 +#endif + +// +//========================================================== + +// Clock - SoftDevice clock configuration + +//========================================================== +// NRF_SDH_CLOCK_LF_SRC - SoftDevice clock source. + +// <0=> NRF_CLOCK_LF_SRC_RC +// <1=> NRF_CLOCK_LF_SRC_XTAL +// <2=> NRF_CLOCK_LF_SRC_SYNTH + +#ifndef NRF_SDH_CLOCK_LF_SRC +#define NRF_SDH_CLOCK_LF_SRC 1 +#endif + +// NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. +#ifndef NRF_SDH_CLOCK_LF_RC_CTIV +#define NRF_SDH_CLOCK_LF_RC_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. +// How often (in number of calibration intervals) the RC oscillator shall be calibrated +// if the temperature has not changed. + +#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV +#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0 +#endif + +// NRF_SDH_CLOCK_LF_ACCURACY - External clock accuracy used in the LL to compute timing. + +// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM +// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM +// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM +// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM +// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM +// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM +// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM +// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM +// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM +// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM +// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM +// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM + +#ifndef NRF_SDH_CLOCK_LF_ACCURACY +#define NRF_SDH_CLOCK_LF_ACCURACY 7 +#endif + +// +//========================================================== + +// SDH Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. +// This setting configures the number of priority levels available for the SoftDevice request event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS +#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. +// This setting configures the number of priority levels available for the SoftDevice state event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2 +#endif + +// NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. +// This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC). +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS +#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2 +#endif + + +// State Observers priorities - Invididual priorities + +//========================================================== +// CLOCK_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO +#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO +#define POWER_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// RNG_CONFIG_STATE_OBSERVER_PRIO +// Priority with which state events are dispatched to this module. + +#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO +#define RNG_CONFIG_STATE_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// Stack Event Observers priorities - Invididual priorities + +//========================================================== +// NRF_SDH_ANT_STACK_OBSERVER_PRIO +// This setting configures the priority with which ANT events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO +#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_BLE_STACK_OBSERVER_PRIO +// This setting configures the priority with which BLE events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC. +// Zero is the highest priority. + +#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO +#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0 +#endif + +// NRF_SDH_SOC_STACK_OBSERVER_PRIO +// This setting configures the priority with which SoC events are processed with respect to other events coming from the stack. +// Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE. +// Zero is the highest priority. + +#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO +#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler +//========================================================== +#ifndef NRF_SDH_SOC_ENABLED +#define NRF_SDH_SOC_ENABLED 1 +#endif +// SoC Observers - Observers and priority levels + +//========================================================== +// NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. +// This setting configures the number of priority levels available for the SoC event handlers. +// The priority level of a handler determines the order in which it receives events, with respect to other handlers. + +#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS +#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2 +#endif + +// SoC Observers priorities - Invididual priorities + +//========================================================== +// BLE_ADV_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Advertising module. + +#ifndef BLE_ADV_SOC_OBSERVER_PRIO +#define BLE_ADV_SOC_OBSERVER_PRIO 1 +#endif + +// BLE_DFU_SOC_OBSERVER_PRIO +// Priority with which BLE events are dispatched to the DFU Service. + +#ifndef BLE_DFU_SOC_OBSERVER_PRIO +#define BLE_DFU_SOC_OBSERVER_PRIO 1 +#endif + +// CLOCK_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Clock driver. + +#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO +#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// POWER_CONFIG_SOC_OBSERVER_PRIO +// Priority with which SoC events are dispatched to the Power driver. + +#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO +#define POWER_CONFIG_SOC_OBSERVER_PRIO 0 +#endif + +// +//========================================================== + +// +//========================================================== + + +// + +// +//========================================================== + +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H + diff --git a/HAL_Driver/inc/bmlite.h b/HAL_Driver/inc/bmlite.h new file mode 100755 index 0000000..c4a97e4 --- /dev/null +++ b/HAL_Driver/inc/bmlite.h @@ -0,0 +1,13 @@ +/** + * @file bmlite.h + * @brief BM-Lite control functions. + */ + +#ifndef BMLITE_H +#define BMLITE_H + +bool nordic_bmlite_get_status(void); +void nordic_board_init(uint32_t speed_hz); +void nordic_bmlite_reset(bool state); + +#endif /* BMLITE_H */ diff --git a/HAL_Driver/inc/btns_leds.h b/HAL_Driver/inc/btns_leds.h new file mode 100644 index 0000000..5472743 --- /dev/null +++ b/HAL_Driver/inc/btns_leds.h @@ -0,0 +1,14 @@ +/** + * @file btns_leds.h + * @brief Buttons and LEDs control functions + */ + +#ifndef BTNS_LEDS_H +#define BTNS_LEDS_H + +#include "platform.h" + +void board_set_led(platform_led_status_t color); +uint32_t board_get_button_press_time(); + +#endif \ No newline at end of file diff --git a/HAL_Driver/inc/nrfx_config.h b/HAL_Driver/inc/nrfx_config.h new file mode 120000 index 0000000..a98a764 --- /dev/null +++ b/HAL_Driver/inc/nrfx_config.h @@ -0,0 +1 @@ +../config/sdk_config.h \ No newline at end of file diff --git a/HAL_Driver/inc/platform_spi.h b/HAL_Driver/inc/platform_spi.h new file mode 100755 index 0000000..62175cd --- /dev/null +++ b/HAL_Driver/inc/platform_spi.h @@ -0,0 +1,16 @@ +/** + * @file platform_spi.h + * @brief Platform SPI functions. + */ + +#ifndef PLATFORM_SPI_H +#define PLATFORM_SPI_H + +#include "fpc_bep_types.h" + +fpc_bep_result_t nordic_bmlite_spi_write_read(uint8_t *write, uint8_t *read, size_t size, + bool leave_cs_asserted); + +void nordic_bmlite_spi_init(uint32_t speed_hz); + +#endif /* PLATFORM_SPI_H */ diff --git a/HAL_Driver/inc/startup_config.h b/HAL_Driver/inc/startup_config.h new file mode 100644 index 0000000..5d2f7b2 --- /dev/null +++ b/HAL_Driver/inc/startup_config.h @@ -0,0 +1,14 @@ +/* Define size of stack. Size must be multiple of 4. */ +#define __STARTUP_CONFIG_STACK_SIZE 0x2000 + +/* Define alignement of stack. Alignment will be 2 to the power of __STARTUP_CONFIG_STACK_ALIGNEMENT. Since calling convention requires that the stack is aligned to 8-bytes when a function is called, the minimum __STARTUP_CONFIG_STACK_ALIGNEMENT is therefore 3. */ +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + +/* Define size of heap. Size must be multiple of 4. */ +#define __STARTUP_CONFIG_HEAP_SIZE 0x12000 + +/* Define entry point */ +#define __START main + +/* Clear BSS at startup */ +#define __STARTUP_CLEAR_BSS \ No newline at end of file diff --git a/HAL_Driver/nordic.mk b/HAL_Driver/nordic.mk new file mode 100644 index 0000000..99a9d90 --- /dev/null +++ b/HAL_Driver/nordic.mk @@ -0,0 +1,157 @@ +# +# Copyright (c) 2020 Fingerprint Cards AB +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# https://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +CPU = cortex_m4 +LOG := + +CFLAGS +=\ + -mcpu=cortex-m4\ + -mthumb -mabi=aapcs\ + -ffunction-sections -fdata-sections -fno-strict-aliasing\ + -fno-builtin --short-enums \ + -Wno-expansion-to-defined \ + -Wno-unused-parameter + +# SDK definitions +CFLAGS +=\ + -DBOARD_PCA10056\ + -DCONFIG_GPIO_AS_PINRESET\ + -DNRF52840_XXAA\ + -D__STARTUP_CONFIG \ + -DMALLOC_PROVIDED \ + -DFPC_MALLOC \ + -DBSP_SIMPLE \ + -Wa,--defsym,_STARTUP_CONFIG=1 \ + -DUART_CMDS \ + +CFLAGS +=\ + -DUSE_HAL_DRIVER \ + -DARM_MATH_CM4\ + -MP -MD + +# Define FS storage type: RAM_STORAGE or NVM_STORAGE +CFLAGS +=\ + -DRAM_STORAGE + +NHAL := $(DEPTH)../HAL_Driver +SDK_ROOT := $(NHAL)/sdk + +# Linker flags +LDFILE = $(NHAL)/spi_gcc_nrf52.ld +TEMPLATE_PATH := $(SDK_ROOT)/modules/nrfx/mdk + +LDFLAGS += -T $(LDFILE) -L $(TEMPLATE_PATH) + +LDLAGS +=\ + -mthumb -mabi=aapcs\ + -mcpu=cortex-m4\ + -L $(TEMPLATE_PATH) + +LDFLAGS +=\ + -lc -lgcc \ + +AR_LIBS +=\ + $(NHAL)/CMSIS/dsp/GCC/libarm_cortexM4lf_math.a + +HAL_SRCS += \ + $(SDK_ROOT)/components/boards/boards.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_backend_rtt.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_backend_serial.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_backend_uart.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_default_backends.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_frontend.c \ + $(SDK_ROOT)/components/libraries/log/src/nrf_log_str_formatter.c \ + $(SDK_ROOT)/components/libraries/button/app_button.c \ + $(SDK_ROOT)/components/libraries/util/app_error.c \ + $(SDK_ROOT)/components/libraries/util/app_error_handler_gcc.c \ + $(SDK_ROOT)/components/libraries/util/app_error_weak.c \ + $(SDK_ROOT)/components/libraries/util/app_util_platform.c \ + $(SDK_ROOT)/components/libraries/util/nrf_assert.c \ + $(SDK_ROOT)/components/libraries/fifo/app_fifo.c \ + $(SDK_ROOT)/components/libraries/uart/app_uart_fifo.c \ + $(SDK_ROOT)/components/libraries/scheduler/app_scheduler.c \ + $(SDK_ROOT)/components/libraries/timer/app_timer.c \ + $(SDK_ROOT)/components/libraries/atomic/nrf_atomic.c \ + $(SDK_ROOT)/components/libraries/balloc/nrf_balloc.c \ + $(SDK_ROOT)/components/libraries/memobj/nrf_memobj.c \ + $(SDK_ROOT)/components/libraries/ringbuf/nrf_ringbuf.c \ + $(SDK_ROOT)/components/libraries/strerror/nrf_strerror.c \ + $(SDK_ROOT)/components/libraries/bsp/bsp.c \ + $(SDK_ROOT)/integration/nrfx/legacy/nrf_drv_spi.c \ + $(SDK_ROOT)/integration/nrfx/legacy/nrf_drv_uart.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_gpiote.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/prs/nrfx_prs.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_spi.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_spim.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_uart.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_uarte.c \ + $(SDK_ROOT)/modules/nrfx/drivers/src/nrfx_timer.c \ + $(SDK_ROOT)/modules/nrfx/soc/nrfx_atomic.c \ + $(SDK_ROOT)/modules/nrfx/mdk/system_nrf52840.c \ + $(SDK_ROOT)/modules/nrfx/hal/nrf_nvmc.c \ + $(SDK_ROOT)/external/fprintf/nrf_fprintf.c \ + $(SDK_ROOT)/external/fprintf/nrf_fprintf_format.c \ + $(SDK_ROOT)/external/segger_rtt/SEGGER_RTT.c \ + $(SDK_ROOT)/external/segger_rtt/SEGGER_RTT_Syscalls_GCC.c \ + $(SDK_ROOT)/external/segger_rtt/SEGGER_RTT_printf.c \ +# $(PROJ_DIR)/main.c \ + +VPATH += $(dir $(HAL_SRCS)) +C_SRCS += $(notdir $(HAL_SRCS)) + +# Source Folders +VPATH += $(NHAL)/src/ + +# C Sources +C_SRCS += $(notdir $(wildcard $(NHAL)/src/*.c)) + +# S Sources +S_SRCS += $(NHAL)/src/gcc_startup_nrf52840.S + +# Includes +C_INC +=\ + -I$(NHAL)/config \ + -I$(NHAL)/inc \ + -I$(NHAL)/CMSIS/Include \ + -I$(SDK_ROOT)/components \ + -I$(SDK_ROOT)/components/libraries/scheduler \ + -I$(SDK_ROOT)/components/libraries/timer \ + -I$(SDK_ROOT)/components/libraries/strerror \ + -I$(SDK_ROOT)/components/toolchain/cmsis/include \ + -I$(SDK_ROOT)/components/libraries/util \ + -I$(SDK_ROOT)/components/libraries/balloc \ + -I$(SDK_ROOT)/components/libraries/ringbuf \ + -I$(SDK_ROOT)/components/libraries/fifo \ + -I$(SDK_ROOT)/components/libraries/bsp \ + -I$(SDK_ROOT)/components/libraries/log \ + -I$(SDK_ROOT)/components/libraries/uart \ + -I$(SDK_ROOT)/components/libraries/button \ + -I$(SDK_ROOT)/components/libraries/experimental_section_vars \ + -I$(SDK_ROOT)/integration/nrfx/legacy \ + -I$(SDK_ROOT)/components/libraries/delay \ + -I$(SDK_ROOT)/integration/nrfx \ + -I$(SDK_ROOT)/components/drivers_nrf/nrf_soc_nosd \ + -I$(SDK_ROOT)/external/segger_rtt \ + -I$(SDK_ROOT)/components/boards \ + -I$(SDK_ROOT)/components/libraries/memobj \ + -I$(SDK_ROOT)/modules/nrfx/drivers/include \ + -I$(SDK_ROOT)/components/libraries/log/src \ + -I$(SDK_ROOT)/external/fprintf \ + -I$(SDK_ROOT)/components/libraries/atomic \ + -I$(SDK_ROOT)/modules/nrfx \ + -I$(SDK_ROOT)/modules/nrfx/hal \ + -I$(SDK_ROOT)/modules/nrfx/mdk \ + -I$(NHAL)/inc \ diff --git a/HAL_Driver/sdk/components/boards/boards.c b/HAL_Driver/sdk/components/boards/boards.c new file mode 100644 index 0000000..1580578 --- /dev/null +++ b/HAL_Driver/sdk/components/boards/boards.c @@ -0,0 +1,228 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "boards.h" +#if defined(BOARDS_WITH_USB_DFU_TRIGGER) && defined(BOARD_PCA10059) +#include "nrf_dfu_trigger_usb.h" +#endif +#include +#include + +#if LEDS_NUMBER > 0 +static const uint8_t m_board_led_list[LEDS_NUMBER] = LEDS_LIST; +#endif + +#if BUTTONS_NUMBER > 0 +static const uint8_t m_board_btn_list[BUTTONS_NUMBER] = BUTTONS_LIST; +#endif + +#if LEDS_NUMBER > 0 +bool bsp_board_led_state_get(uint32_t led_idx) +{ + ASSERT(led_idx < LEDS_NUMBER); + bool pin_set = nrf_gpio_pin_out_read(m_board_led_list[led_idx]) ? true : false; + return (pin_set == (LEDS_ACTIVE_STATE ? true : false)); +} + +void bsp_board_led_on(uint32_t led_idx) +{ + ASSERT(led_idx < LEDS_NUMBER); + nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 1 : 0); +} + +void bsp_board_led_off(uint32_t led_idx) +{ + ASSERT(led_idx < LEDS_NUMBER); + nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 0 : 1); +} + +void bsp_board_leds_off(void) +{ + uint32_t i; + for (i = 0; i < LEDS_NUMBER; ++i) + { + bsp_board_led_off(i); + } +} + +void bsp_board_leds_on(void) +{ + uint32_t i; + for (i = 0; i < LEDS_NUMBER; ++i) + { + bsp_board_led_on(i); + } +} + +void bsp_board_led_invert(uint32_t led_idx) +{ + ASSERT(led_idx < LEDS_NUMBER); + nrf_gpio_pin_toggle(m_board_led_list[led_idx]); +} + +#if defined(BOARD_PCA10059) +/** + * Function for configuring UICR_REGOUT0 register + * to set GPIO output voltage to 3.0V. + */ +static void gpio_output_voltage_setup(void) +{ + // Configure UICR_REGOUT0 register only if it is set to default value. + if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) == + (UICR_REGOUT0_VOUT_DEFAULT << UICR_REGOUT0_VOUT_Pos)) + { + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + + NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~((uint32_t)UICR_REGOUT0_VOUT_Msk)) | + (UICR_REGOUT0_VOUT_3V0 << UICR_REGOUT0_VOUT_Pos); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + + // System reset is needed to update UICR registers. + NVIC_SystemReset(); + } +} +#endif + +static void bsp_board_leds_init(void) +{ + #if defined(BOARD_PCA10059) + // If nRF52 USB Dongle is powered from USB (high voltage mode), + // GPIO output voltage is set to 1.8 V by default, which is not + // enough to turn on green and blue LEDs. Therefore, GPIO voltage + // needs to be increased to 3.0 V by configuring the UICR register. + if (NRF_POWER->MAINREGSTATUS & + (POWER_MAINREGSTATUS_MAINREGSTATUS_High << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos)) + { + gpio_output_voltage_setup(); + } + #endif + + uint32_t i; + for (i = 0; i < LEDS_NUMBER; ++i) + { + nrf_gpio_cfg_output(m_board_led_list[i]); + } + bsp_board_leds_off(); +} + +uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx) +{ + ASSERT(led_idx < LEDS_NUMBER); + return m_board_led_list[led_idx]; +} + +uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number) +{ + uint32_t ret = 0xFFFFFFFF; + uint32_t i; + for (i = 0; i < LEDS_NUMBER; ++i) + { + if (m_board_led_list[i] == pin_number) + { + ret = i; + break; + } + } + return ret; +} +#endif //LEDS_NUMBER > 0 + +#if BUTTONS_NUMBER > 0 +bool bsp_board_button_state_get(uint32_t button_idx) +{ + ASSERT(button_idx < BUTTONS_NUMBER); + bool pin_set = nrf_gpio_pin_read(m_board_btn_list[button_idx]) ? true : false; + return (pin_set == (BUTTONS_ACTIVE_STATE ? true : false)); +} + +static void bsp_board_buttons_init(void) +{ + uint32_t i; + for (i = 0; i < BUTTONS_NUMBER; ++i) + { + nrf_gpio_cfg_input(m_board_btn_list[i], BUTTON_PULL); + } +} + +uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number) +{ + uint32_t i; + uint32_t ret = 0xFFFFFFFF; + for (i = 0; i < BUTTONS_NUMBER; ++i) + { + if (m_board_btn_list[i] == pin_number) + { + ret = i; + break; + } + } + return ret; +} + +uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx) +{ + ASSERT(button_idx < BUTTONS_NUMBER); + return m_board_btn_list[button_idx]; +} +#endif //BUTTONS_NUMBER > 0 + + +void bsp_board_init(uint32_t init_flags) +{ + #if defined(BOARDS_WITH_USB_DFU_TRIGGER) && defined(BOARD_PCA10059) + (void) nrf_dfu_trigger_usb_init(); + #endif + + #if LEDS_NUMBER > 0 + if (init_flags & BSP_INIT_LEDS) + { + bsp_board_leds_init(); + } + #endif //LEDS_NUMBER > 0 + + #if BUTTONS_NUMBER > 0 + if (init_flags & BSP_INIT_BUTTONS) + { + bsp_board_buttons_init(); + } + #endif //BUTTONS_NUMBER > 0 +} diff --git a/HAL_Driver/sdk/components/boards/boards.h b/HAL_Driver/sdk/components/boards/boards.h new file mode 100644 index 0000000..741cd46 --- /dev/null +++ b/HAL_Driver/sdk/components/boards/boards.h @@ -0,0 +1,355 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef BOARDS_H +#define BOARDS_H + +#include "nrf_gpio.h" +#include "nordic_common.h" + +#if defined(BOARD_NRF6310) + #include "nrf6310.h" +#elif defined(BOARD_PCA10000) + #include "pca10000.h" +#elif defined(BOARD_PCA10001) + #include "pca10001.h" +#elif defined(BOARD_PCA10002) + #include "pca10000.h" +#elif defined(BOARD_PCA10003) + #include "pca10003.h" +#elif defined(BOARD_PCA20006) + #include "pca20006.h" +#elif defined(BOARD_PCA10028) + #include "pca10028.h" +#elif defined(BOARD_PCA10031) + #include "pca10031.h" +#elif defined(BOARD_PCA10036) + #include "pca10036.h" +#elif defined(BOARD_PCA10040) + #include "pca10040.h" +#elif defined(BOARD_PCA10056) + #include "pca10056.h" +#elif defined(BOARD_PCA20020) + #include "pca20020.h" +#elif defined(BOARD_PCA10059) + #include "pca10059.h" +#elif defined(BOARD_WT51822) + #include "wt51822.h" +#elif defined(BOARD_N5DK1) + #include "n5_starterkit.h" +#elif defined (BOARD_D52DK1) + #include "d52_starterkit.h" +#elif defined (BOARD_ARDUINO_PRIMO) + #include "arduino_primo.h" +#elif defined (CUSTOM_BOARD_INC) + #include STRINGIFY(CUSTOM_BOARD_INC.h) +#elif defined(BOARD_CUSTOM) + #include "custom_board.h" +#else +#error "Board is not defined" + +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/**@defgroup BSP_BOARD_INIT_FLAGS Board initialization flags. + * @{ */ +#define BSP_INIT_NONE 0 /**< No initialization of LEDs or buttons (@ref bsp_board_init).*/ +#define BSP_INIT_LEDS (1 << 0) /**< Enable LEDs during initialization (@ref bsp_board_init).*/ +#define BSP_INIT_BUTTONS (1 << 1) /**< Enable buttons during initialization (@ref bsp_board_init).*/ +/**@} */ + +/** + * Function for returning the state of an LED. + * + * @param led_idx LED index (starting from 0), as defined in the board-specific header. + * + * @return True if the LED is turned on. + */ +bool bsp_board_led_state_get(uint32_t led_idx); + +/** + * Function for turning on an LED. + * + * @param led_idx LED index (starting from 0), as defined in the board-specific header. + */ +void bsp_board_led_on(uint32_t led_idx); + +/** + * Function for turning off an LED. + * + * @param led_idx LED index (starting from 0), as defined in the board-specific header. + */ +void bsp_board_led_off(uint32_t led_idx); + +/** + * Function for inverting the state of an LED. + * + * @param led_idx LED index (starting from 0), as defined in the board-specific header. + */ +void bsp_board_led_invert(uint32_t led_idx); +/** + * Function for turning off all LEDs. + */ +void bsp_board_leds_off(void); + +/** + * Function for turning on all LEDs. + */ +void bsp_board_leds_on(void); + +/** + * Function for initializing the BSP handling for the board. + * + * @note This also initializes the USB DFU trigger library if @ref BOARDS_WITH_USB_DFU_TRIGGER is 1. + * + * @param[in] init_flags Flags specifying what to initialize (LEDs/buttons). + * See @ref BSP_BOARD_INIT_FLAGS. + */ +void bsp_board_init(uint32_t init_flags); + +/** + * Function for converting pin number to LED index. + * + * @param pin_number Pin number. + * + * @return LED index of the given pin or 0xFFFFFFFF if invalid pin provided. + */ +uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number); + +/** + * Function for converting LED index to pin number. + * + * @param led_idx LED index. + * + * @return Pin number. + */ +uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx); + +/** + * Function for returning the state of a button. + * + * @param button_idx Button index (starting from 0), as defined in the board-specific header. + * + * @return True if the button is pressed. + */ +bool bsp_board_button_state_get(uint32_t button_idx); + +/** + * Function for converting pin number to button index. + * + * @param pin_number Pin number. + * + * @return Button index of the given pin or 0xFFFFFFFF if invalid pin provided. + */ +uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number); + + +/** + * Function for converting button index to pin number. + * + * @param button_idx Button index. + * + * @return Pin number. + */ +uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx); + +#define BSP_BOARD_LED_0 0 +#define BSP_BOARD_LED_1 1 +#define BSP_BOARD_LED_2 2 +#define BSP_BOARD_LED_3 3 +#define BSP_BOARD_LED_4 4 +#define BSP_BOARD_LED_5 5 +#define BSP_BOARD_LED_6 6 +#define BSP_BOARD_LED_7 7 + +#define PIN_MASK(_pin) /*lint -save -e504 */ \ + (1u << (uint32_t)((_pin) & (~P0_PIN_NUM))) \ + /*lint -restore */ + +#define PIN_PORT(_pin) (((_pin) >= P0_PIN_NUM) ? NRF_P1 : NRF_GPIO) + +#ifdef BSP_LED_0 +#define BSP_LED_0_MASK PIN_MASK(BSP_LED_0) +#define BSP_LED_0_PORT PIN_PORT(BSP_LED_0) +#else +#define BSP_LED_0_MASK 0 +#define BSP_LED_0_PORT 0 +#endif +#ifdef BSP_LED_1 +#define BSP_LED_1_MASK PIN_MASK(BSP_LED_1) +#define BSP_LED_1_PORT PIN_PORT(BSP_LED_1) +#else +#define BSP_LED_1_MASK 0 +#define BSP_LED_1_PORT 0 +#endif +#ifdef BSP_LED_2 +#define BSP_LED_2_MASK PIN_MASK(BSP_LED_2) +#define BSP_LED_2_PORT PIN_PORT(BSP_LED_2) +#else +#define BSP_LED_2_MASK 0 +#define BSP_LED_2_PORT 0 +#endif +#ifdef BSP_LED_3 +#define BSP_LED_3_MASK PIN_MASK(BSP_LED_3) +#define BSP_LED_3_PORT PIN_PORT(BSP_LED_3) +#else +#define BSP_LED_3_MASK 0 +#define BSP_LED_3_PORT 0 +#endif +#ifdef BSP_LED_4 +#define BSP_LED_4_MASK PIN_MASK(BSP_LED_4) +#define BSP_LED_4_PORT PIN_PORT(BSP_LED_4) +#else +#define BSP_LED_4_MASK 0 +#define BSP_LED_4_PORT 0 +#endif +#ifdef BSP_LED_5 +#define BSP_LED_5_MASK PIN_MASK(BSP_LED_5) +#define BSP_LED_5_PORT PIN_PORT(BSP_LED_5) +#else +#define BSP_LED_5_MASK 0 +#define BSP_LED_5_PORT 0 +#endif +#ifdef BSP_LED_6 +#define BSP_LED_6_MASK PIN_MASK(BSP_LED_6) +#define BSP_LED_6_PORT PIN_PORT(BSP_LED_6) +#else +#define BSP_LED_6_MASK 0 +#define BSP_LED_6_PORT 0 +#endif +#ifdef BSP_LED_7 +#define BSP_LED_7_MASK PIN_MASK(BSP_LED_7) +#define BSP_LED_7_PORT PIN_PORT(BSP_LED_7) +#else +#define BSP_LED_7_MASK 0 +#define BSP_LED_7_PORT 0 +#endif + + +#define LEDS_MASK (BSP_LED_0_MASK | BSP_LED_1_MASK | \ + BSP_LED_2_MASK | BSP_LED_3_MASK | \ + BSP_LED_4_MASK | BSP_LED_5_MASK | \ + BSP_LED_6_MASK | BSP_LED_7_MASK) + +#define BSP_BOARD_BUTTON_0 0 +#define BSP_BOARD_BUTTON_1 1 +#define BSP_BOARD_BUTTON_2 2 +#define BSP_BOARD_BUTTON_3 3 +#define BSP_BOARD_BUTTON_4 4 +#define BSP_BOARD_BUTTON_5 5 +#define BSP_BOARD_BUTTON_6 6 +#define BSP_BOARD_BUTTON_7 7 + + +#ifdef BSP_BUTTON_0 +#define BSP_BUTTON_0_MASK (1<OUTSET = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \ + NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0) + +#define LEDS_ON(leds_mask) do { ASSERT(sizeof(leds_mask) == 4); \ + NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \ + NRF_GPIO->OUTSET = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0) + +#define LED_IS_ON(leds_mask) ((leds_mask) & (NRF_GPIO->OUT ^ LEDS_INV_MASK) ) + +#define LEDS_INVERT(leds_mask) do { uint32_t gpio_state = NRF_GPIO->OUT; \ + ASSERT(sizeof(leds_mask) == 4); \ + NRF_GPIO->OUTSET = ((leds_mask) & ~gpio_state); \ + NRF_GPIO->OUTCLR = ((leds_mask) & gpio_state); } while (0) + +#define LEDS_CONFIGURE(leds_mask) do { uint32_t pin; \ + ASSERT(sizeof(leds_mask) == 4); \ + for (pin = 0; pin < 32; pin++) \ + if ( (leds_mask) & (1 << pin) ) \ + nrf_gpio_cfg_output(pin); } while (0) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/HAL_Driver/sdk/components/boards/pca10056.h b/HAL_Driver/sdk/components/boards/pca10056.h new file mode 100644 index 0000000..ac43159 --- /dev/null +++ b/HAL_Driver/sdk/components/boards/pca10056.h @@ -0,0 +1,163 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef PCA10056_H +#define PCA10056_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nrf_gpio.h" + +// LEDs definitions for PCA10056 +#define LEDS_NUMBER 4 + +#define LED_1 NRF_GPIO_PIN_MAP(0,13) +#define LED_2 NRF_GPIO_PIN_MAP(0,14) +#define LED_3 NRF_GPIO_PIN_MAP(0,15) +#define LED_4 NRF_GPIO_PIN_MAP(0,16) +#define LED_START LED_1 +#define LED_STOP LED_4 + +#define LEDS_ACTIVE_STATE 0 + +#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 } + +#define LEDS_INV_MASK LEDS_MASK + +#define BSP_LED_0 13 +#define BSP_LED_1 14 +#define BSP_LED_2 15 +#define BSP_LED_3 16 + +#define BUTTONS_NUMBER 4 + +#define BUTTON_1 11 +#define BUTTON_2 12 +#define BUTTON_3 24 +#define BUTTON_4 25 +#define BUTTON_PULL NRF_GPIO_PIN_PULLUP + +#define BUTTONS_ACTIVE_STATE 0 + +#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 } + +#define BSP_BUTTON_0 BUTTON_1 +#define BSP_BUTTON_1 BUTTON_2 +#define BSP_BUTTON_2 BUTTON_3 +#define BSP_BUTTON_3 BUTTON_4 + +#define RX_PIN_NUMBER 8 +#define TX_PIN_NUMBER 6 +#define CTS_PIN_NUMBER 7 +#define RTS_PIN_NUMBER 5 +#define HWFC true + +#define BSP_QSPI_SCK_PIN 19 +#define BSP_QSPI_CSN_PIN 17 +#define BSP_QSPI_IO0_PIN 20 +#define BSP_QSPI_IO1_PIN 21 +#define BSP_QSPI_IO2_PIN 22 +#define BSP_QSPI_IO3_PIN 23 + + +// serialization APPLICATION board - temp. setup for running serialized MEMU tests +#define SER_APP_RX_PIN NRF_GPIO_PIN_MAP(1,13) // UART RX pin number. +#define SER_APP_TX_PIN NRF_GPIO_PIN_MAP(1,14) // UART TX pin number. +#define SER_APP_CTS_PIN NRF_GPIO_PIN_MAP(0,2) // UART Clear To Send pin number. +#define SER_APP_RTS_PIN NRF_GPIO_PIN_MAP(1,15) // UART Request To Send pin number. + +#define SER_APP_SPIM0_SCK_PIN NRF_GPIO_PIN_MAP(0,27) // SPI clock GPIO pin number. +#define SER_APP_SPIM0_MOSI_PIN NRF_GPIO_PIN_MAP(0,2) // SPI Master Out Slave In GPIO pin number +#define SER_APP_SPIM0_MISO_PIN NRF_GPIO_PIN_MAP(0,26) // SPI Master In Slave Out GPIO pin number +#define SER_APP_SPIM0_SS_PIN NRF_GPIO_PIN_MAP(1,13) // SPI Slave Select GPIO pin number +#define SER_APP_SPIM0_RDY_PIN NRF_GPIO_PIN_MAP(1,15) // SPI READY GPIO pin number +#define SER_APP_SPIM0_REQ_PIN NRF_GPIO_PIN_MAP(1,14) // SPI REQUEST GPIO pin number + +// serialization CONNECTIVITY board +#define SER_CON_RX_PIN NRF_GPIO_PIN_MAP(1,14) // UART RX pin number. +#define SER_CON_TX_PIN NRF_GPIO_PIN_MAP(1,13) // UART TX pin number. +#define SER_CON_CTS_PIN NRF_GPIO_PIN_MAP(1,15) // UART Clear To Send pin number. Not used if HWFC is set to false. +#define SER_CON_RTS_PIN NRF_GPIO_PIN_MAP(0,2) // UART Request To Send pin number. Not used if HWFC is set to false. + + +#define SER_CON_SPIS_SCK_PIN NRF_GPIO_PIN_MAP(0,27) // SPI SCK signal. +#define SER_CON_SPIS_MOSI_PIN NRF_GPIO_PIN_MAP(0,2) // SPI MOSI signal. +#define SER_CON_SPIS_MISO_PIN NRF_GPIO_PIN_MAP(0,26) // SPI MISO signal. +#define SER_CON_SPIS_CSN_PIN NRF_GPIO_PIN_MAP(1,13) // SPI CSN signal. +#define SER_CON_SPIS_RDY_PIN NRF_GPIO_PIN_MAP(1,15) // SPI READY GPIO pin number. +#define SER_CON_SPIS_REQ_PIN NRF_GPIO_PIN_MAP(1,14) // SPI REQUEST GPIO pin number. + +#define SER_CONN_CHIP_RESET_PIN NRF_GPIO_PIN_MAP(1,1) // Pin used to reset connectivity chip + +// Arduino board mappings +#define ARDUINO_SCL_PIN 27 // SCL signal pin +#define ARDUINO_SDA_PIN 26 // SDA signal pin +#define ARDUINO_AREF_PIN 2 // Aref pin + +#define ARDUINO_13_PIN NRF_GPIO_PIN_MAP(1, 15) // Digital pin 13 +#define ARDUINO_12_PIN NRF_GPIO_PIN_MAP(1, 14) // Digital pin 12 +#define ARDUINO_11_PIN NRF_GPIO_PIN_MAP(1, 13) // Digital pin 11 +#define ARDUINO_10_PIN NRF_GPIO_PIN_MAP(1, 12) // Digital pin 10 +#define ARDUINO_9_PIN NRF_GPIO_PIN_MAP(1, 11) // Digital pin 9 +#define ARDUINO_8_PIN NRF_GPIO_PIN_MAP(1, 10) // Digital pin 8 + +#define ARDUINO_7_PIN NRF_GPIO_PIN_MAP(1, 8) // Digital pin 7 +#define ARDUINO_6_PIN NRF_GPIO_PIN_MAP(1, 7) // Digital pin 6 +#define ARDUINO_5_PIN NRF_GPIO_PIN_MAP(1, 6) // Digital pin 5 +#define ARDUINO_4_PIN NRF_GPIO_PIN_MAP(1, 5) // Digital pin 4 +#define ARDUINO_3_PIN NRF_GPIO_PIN_MAP(1, 4) // Digital pin 3 +#define ARDUINO_2_PIN NRF_GPIO_PIN_MAP(1, 3) // Digital pin 2 +#define ARDUINO_1_PIN NRF_GPIO_PIN_MAP(1, 2) // Digital pin 1 +#define ARDUINO_0_PIN NRF_GPIO_PIN_MAP(1, 1) // Digital pin 0 + +#define ARDUINO_A0_PIN 3 // Analog channel 0 +#define ARDUINO_A1_PIN 4 // Analog channel 1 +#define ARDUINO_A2_PIN 28 // Analog channel 2 +#define ARDUINO_A3_PIN 29 // Analog channel 3 +#define ARDUINO_A4_PIN 30 // Analog channel 4 +#define ARDUINO_A5_PIN 31 // Analog channel 5 + + +#ifdef __cplusplus +} +#endif + +#endif // PCA10056_H diff --git a/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h b/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h new file mode 100644 index 0000000..1656aa7 --- /dev/null +++ b/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_error.h @@ -0,0 +1,95 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/* Header guard */ + +#ifndef SOFTDEVICE_PRESENT + +/** + @defgroup nrf_error Global Error Codes + @{ + + @brief Global Error definitions +*/ + +#ifndef NRF_ERROR_H__ +#define NRF_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions + * @{ */ +#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base +#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base +#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base +#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base +/** @} */ + +#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command +#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing +#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled +#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error +#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation +#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found +#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported +#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter +#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state +#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length +#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags +#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data +#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Data size exceeds limit +#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out +#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer +#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation +#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address +#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy + +#ifdef __cplusplus +} +#endif + +#endif // NRF_ERROR_H__ + +/** + @} +*/ + +#endif // SOFTDEVICE_PRESENT diff --git a/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h b/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h new file mode 100644 index 0000000..0201ffe --- /dev/null +++ b/HAL_Driver/sdk/components/drivers_nrf/nrf_soc_nosd/nrf_soc.h @@ -0,0 +1,80 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_SOC_H__ +#define NRF_SOC_H__ + +#include +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@brief Waits for an application event. + * + * An application event is either an application interrupt or a pended interrupt when the + * interrupt is disabled. When the interrupt is enabled it will be taken immediately since + * this function will wait in thread mode, then the execution will return in the application's + * main thread. When an interrupt is disabled and gets pended it will return to the application's + * thread main. The application must ensure that the pended flag is cleared using + * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for + * disabled interrupts, as the interrupt handler will clear the pending flag automatically for + * enabled interrupts. + * + * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0 + * System Control Register (SCR). @sa CMSIS_SCB + * + * @note If an application interrupt has happened since the last time sd_app_evt_wait was + * called this function will return immediately and not go to sleep. This is to avoid race + * conditions that can occur when a flag is updated in the interrupt handler and processed + * in the main loop. + * + * @post An application interrupt has happened or a interrupt pending flag is set. + * + * @retval ::NRF_SUCCESS + */ +uint32_t sd_app_evt_wait(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_SOC_H__ */ diff --git a/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.c b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.c new file mode 100644 index 0000000..7aefb35 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.c @@ -0,0 +1,449 @@ +/** + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "nrf_atomic.h" + +#ifndef NRF_ATOMIC_USE_BUILD_IN +#if (defined(__GNUC__) && defined(WIN32)) + #define NRF_ATOMIC_USE_BUILD_IN 1 +#else + #define NRF_ATOMIC_USE_BUILD_IN 0 +#endif +#endif // NRF_ATOMIC_USE_BUILD_IN + +#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) +#define STREX_LDREX_PRESENT +#else +#include "app_util_platform.h" +#endif + + +#if (NRF_ATOMIC_USE_BUILD_IN == 0) && defined(STREX_LDREX_PRESENT) +#include "nrf_atomic_internal.h" +#endif + +uint32_t nrf_atomic_u32_fetch_store(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST); + +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRF_ATOMIC_OP(mov, old_val, new_val, p_data, value); + + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data = value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_store(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + __atomic_store_n(p_data, value, __ATOMIC_SEQ_CST); + return value; +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(mov, old_val, new_val, p_data, value); + + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data = value; + CRITICAL_REGION_EXIT(); + return value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_fetch_or(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_fetch_or(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(orr, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data |= value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_or(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_or_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(orr, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data |= value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_fetch_and(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_fetch_and(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(and, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data &= value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_and(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_and_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(and, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data &= value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_fetch_xor(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_fetch_xor(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(eor, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data ^= value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_xor(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_xor_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(eor, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data ^= value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_fetch_add(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_fetch_add(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(add, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data += value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_add(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_add_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(add, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data += value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_fetch_sub(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_fetch_sub(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(sub, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data -= value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_sub(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_sub_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(sub, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data -= value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +bool nrf_atomic_u32_cmp_exch(nrf_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t desired) +{ +#if NRF_ATOMIC_USE_BUILD_IN + return __atomic_compare_exchange(p_data, + p_expected, + &desired, + 1, + __ATOMIC_SEQ_CST, + __ATOMIC_SEQ_CST); +#elif defined(STREX_LDREX_PRESENT) + return nrf_atomic_internal_cmp_exch(p_data, p_expected, desired); +#else + bool ret; + CRITICAL_REGION_ENTER(); + if (*p_data == *p_expected) + { + *p_data = desired; + ret = true; + } + else + { + *p_expected = *p_data; + ret = false; + } + CRITICAL_REGION_EXIT(); + return ret; +#endif +} + +uint32_t nrf_atomic_u32_fetch_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + uint32_t expected = *p_data; + uint32_t new_val; + bool success; + + do + { + if (expected >= value) + { + new_val = expected - value; + } + else + { + new_val = expected; + } + success = __atomic_compare_exchange(p_data, + &expected, + &new_val, + 1, + __ATOMIC_SEQ_CST, + __ATOMIC_SEQ_CST); + } while(!success); + return expected; +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return old_val; +#else + CRITICAL_REGION_ENTER(); + uint32_t old_val = *p_data; + *p_data -= value; + CRITICAL_REGION_EXIT(); + return old_val; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_u32_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value) +{ +#if NRF_ATOMIC_USE_BUILD_IN + uint32_t expected = *p_data; + uint32_t new_val; + bool success; + + do + { + if (expected >= value) + { + new_val = expected - value; + } + else + { + new_val = expected; + } + success = __atomic_compare_exchange(p_data, + &expected, + &new_val, + 1, + __ATOMIC_SEQ_CST, + __ATOMIC_SEQ_CST); + } while(!success); + return new_val; +#elif defined(STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + + NRF_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); + UNUSED_PARAMETER(old_val); + UNUSED_PARAMETER(new_val); + return new_val; +#else + CRITICAL_REGION_ENTER(); + *p_data -= value; + uint32_t new_value = *p_data; + CRITICAL_REGION_EXIT(); + return new_value; +#endif //NRF_ATOMIC_USE_BUILD_IN +} + +uint32_t nrf_atomic_flag_set_fetch(nrf_atomic_flag_t * p_data) +{ + return nrf_atomic_u32_fetch_or(p_data, 1); +} + +uint32_t nrf_atomic_flag_set(nrf_atomic_flag_t * p_data) +{ + return nrf_atomic_u32_or(p_data, 1); +} + +uint32_t nrf_atomic_flag_clear_fetch(nrf_atomic_flag_t * p_data) +{ + return nrf_atomic_u32_fetch_and(p_data, 0); +} + +uint32_t nrf_atomic_flag_clear(nrf_atomic_flag_t * p_data) +{ + return nrf_atomic_u32_and(p_data, 0); +} + diff --git a/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.h b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.h new file mode 100644 index 0000000..6406c17 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic.h @@ -0,0 +1,274 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup nrf_atomic Atomic operations API + * @ingroup app_common + * @{ + * + * @brief @tagAPI52 This module implements C11 stdatomic.h simplified API. + At this point only Cortex-M3/M4 cores are supported (LDREX/STREX instructions). + * Atomic types are limited to @ref nrf_atomic_u32_t and @ref nrf_atomic_flag_t. + */ + +#ifndef NRF_ATOMIC_H__ +#define NRF_ATOMIC_H__ + +#include "sdk_common.h" + +/** + * @brief Atomic 32 bit unsigned type + * */ +typedef volatile uint32_t nrf_atomic_u32_t; + +/** + * @brief Atomic 1 bit flag type (technically 32 bit) + * */ +typedef volatile uint32_t nrf_atomic_flag_t; + + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Stores value to an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value to store + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_store(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Stores value to an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value to store + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_store(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical OR operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand OR operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_or(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical OR operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand OR operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_or(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical AND operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand AND operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_and(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical AND operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand AND operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_and(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical XOR operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand XOR operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_xor(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Logical XOR operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand XOR operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_xor(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Arithmetic ADD operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand ADD operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_add(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Arithmetic ADD operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand ADD operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_add(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Arithmetic SUB operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand SUB operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_sub(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Arithmetic SUB operation on an atomic object + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand SUB operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_sub(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief If value at pointer is equal to expected value, changes value at pointer to desired + * + * Atomically compares the value pointed to by p_data with the value pointed to by p_expected, + * and if those are equal, replaces the former with desired. Otherwise, loads the actual value + * pointed to by p_data into *p_expected. + * + * @param p_data Atomic memory pointer to test and modify. + * @param p_expected Pointer to test value. + * @param desired Value to be stored to atomic memory. + * + * @retval true *p_data was equal to *p_expected + * @retval false *p_data was not equal to *p_expected + */ +bool nrf_atomic_u32_cmp_exch(nrf_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t desired); + +/** + * @brief Arithmetic SUB operation on an atomic object performed if object >= value. + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand SUB operation + * + * @return Old value stored into atomic object + * */ +uint32_t nrf_atomic_u32_fetch_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Arithmetic SUB operation on an atomic object performed if object >= value. + * + * @param[in] p_data Atomic memory pointer + * @param[in] value Value of second operand SUB operation + * + * @return New value stored into atomic object + * */ +uint32_t nrf_atomic_u32_sub_hs(nrf_atomic_u32_t * p_data, uint32_t value); + +/**************************************************************************************************/ + +/** + * @brief Logic one bit flag set operation on an atomic object + * + * @param[in] p_data Atomic flag memory pointer + * + * @return Old flag value + * */ +uint32_t nrf_atomic_flag_set_fetch(nrf_atomic_flag_t * p_data); + +/** + * @brief Logic one bit flag set operation on an atomic object + * + * @param[in] p_data Atomic flag memory pointer + * + * @return New flag value + * */ +uint32_t nrf_atomic_flag_set(nrf_atomic_flag_t * p_data); + +/** + * @brief Logic one bit flag clear operation on an atomic object + * + * @param[in] p_data Atomic flag memory pointer + * + * @return Old flag value + * */ +uint32_t nrf_atomic_flag_clear_fetch(nrf_atomic_flag_t * p_data); + +/** + * @brief Logic one bit flag clear operation on an atomic object + * + * @param[in] p_data Atomic flag memory pointer + * + * @return New flag value + * */ +uint32_t nrf_atomic_flag_clear(nrf_atomic_flag_t * p_data); + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_ATOMIC_H__ */ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic_internal.h b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic_internal.h new file mode 100644 index 0000000..136f40e --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/atomic/nrf_atomic_internal.h @@ -0,0 +1,343 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_ATOMIC_INTERNAL_H__ +#define NRF_ATOMIC_INTERNAL_H__ + +#include "sdk_common.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @defgroup nrf_atomic_internal Atomic operations internals + * @ingroup nrf_atomic + * @{ + * + */ + +/* Only Cortex M cores > 3 support LDREX/STREX instructions*/ +#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) == 0 +#error "Unsupported core version" +#endif + +#if defined ( __CC_ARM ) +static __asm uint32_t nrf_atomic_internal_mov(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + /* The base standard provides for passing arguments in core registers (r0-r3) and on the stack. + * Registers r4 and r5 have to be saved on stack. Note that only even number of register push are + * allowed. This is a requirement of the Procedure Call Standard for the ARM Architecture [AAPCS]. + * */ + push {r4, r5} + mov r4, r0 + +loop_mov + ldrex r0, [r4] + mov r5, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_mov + + str r5, [r2] + pop {r4, r5} + bx lr +} + + +static __asm uint32_t nrf_atomic_internal_orr(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_orr + ldrex r0, [r4] + orr r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_orr + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrf_atomic_internal_and(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_and + ldrex r0, [r4] + and r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_and + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrf_atomic_internal_eor(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_eor + ldrex r0, [r4] + eor r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_eor + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrf_atomic_internal_add(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_add + ldrex r0, [r4] + add r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_add + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrf_atomic_internal_sub(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_sub + ldrex r0, [r4] + sub r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_sub + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm bool nrf_atomic_internal_cmp_exch(nrf_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t value) +{ +#define RET_REG r0 +#define P_EXPC r1 +#define VALUE r2 +#define STR_RES r3 +#define P_DATA r4 +#define EXPC_VAL r5 +#define ACT_VAL r6 + + push {r4-r6} + mov P_DATA, r0 + mov RET_REG, #0 + +loop_cmp_exch + ldrex ACT_VAL, [P_DATA] + ldr EXPC_VAL, [P_EXPC] + cmp ACT_VAL, EXPC_VAL + ittee eq + strexeq STR_RES, VALUE, [P_DATA] + moveq RET_REG, #1 + strexne STR_RES, ACT_VAL, [P_DATA] + strne ACT_VAL, [P_EXPC] + cmp STR_RES, #0 + itt ne + movne RET_REG, #0 + bne loop_cmp_exch + + pop {r4-r6} + bx lr + +#undef RET_REG +#undef P_EXPC +#undef VALUE +#undef STR_RES +#undef P_DATA +#undef EXPC_VAL +#undef ACT_VAL +} + +static __asm uint32_t nrf_atomic_internal_sub_hs(nrf_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_sub_ge + ldrex r0, [r4] + cmp r0, r1 + ite hs + subhs r5, r0, r1 + movlo r5, r0 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_sub_ge + + str r5, [r2] + pop {r4, r5} + bx lr +} + + +#define NRF_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ + old_val = nrf_atomic_internal_##asm_op(ptr, value, &new_val) + +#elif defined ( __ICCARM__ ) || defined ( __GNUC__ ) + +/** + * @brief Atomic operation generic macro + * @param[in] asm_op operation: mov, orr, and, eor, add, sub + * @param[out] old_val atomic object output (uint32_t), value before operation + * @param[out] new_val atomic object output (uint32_t), value after operation + * @param[in] value atomic operation operand + * */ +#define NRF_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ +{ \ + uint32_t str_res; \ + __ASM volatile( \ + "1: ldrex %["#old_val"], [%["#ptr"]]\n" \ + NRF_ATOMIC_OP_##asm_op(new_val, old_val, value) \ + " strex %[str_res], %["#new_val"], [%["#ptr"]]\n" \ + " teq %[str_res], #0\n" \ + " bne.n 1b" \ + : \ + [old_val]"=&r" (old_val), \ + [new_val]"=&r" (new_val), \ + [str_res]"=&r" (str_res) \ + : \ + [ptr]"r" (ptr), \ + [value]"r" (value) \ + : "cc"); \ + UNUSED_PARAMETER(str_res); \ +} + +#define NRF_ATOMIC_OP_mov(new_val, old_val, value) "mov %["#new_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_orr(new_val, old_val, value) "orr %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_and(new_val, old_val, value) "and %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_eor(new_val, old_val, value) "eor %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_add(new_val, old_val, value) "add %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_sub(new_val, old_val, value) "sub %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRF_ATOMIC_OP_sub_hs(new_val, old_val, value) \ + "cmp %["#old_val"], %["#value"]\n " \ + "ite hs\n" \ + "subhs %["#new_val"], %["#old_val"], %["#value"]\n" \ + "movlo %["#new_val"], %["#old_val"]\n" + +static inline bool nrf_atomic_internal_cmp_exch(nrf_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t value) +{ + bool res = false; + uint32_t str_res = 0; + uint32_t act_val = 0; + uint32_t exp_val = 0; + UNUSED_VARIABLE(str_res); + UNUSED_VARIABLE(act_val); + UNUSED_VARIABLE(exp_val); + __ASM volatile( + "1: ldrex %[act_val], [%[ptr]]\n" + " ldr %[exp_val], [%[expc]]\n" + " cmp %[act_val], %[exp_val]\n" + " ittee eq\n" + " strexeq %[str_res], %[value], [%[ptr]]\n" + " moveq %[res], #1\n" + " strexne %[str_res], %[act_val], [%[ptr]]\n" + " strne %[act_val], [%[expc]]\n" + " cmp %[str_res], #0\n" + " itt ne\n" + " movne %[res], #0\n" + " bne.n 1b" + : + [res] "=&r" (res), + [exp_val] "=&r" (exp_val), + [act_val] "=&r" (act_val), + [str_res] "=&r" (str_res) + : + "0" (res), + "1" (exp_val), + "2" (act_val), + [expc] "r" (p_expected), + [ptr] "r" (p_data), + [value] "r" (value) + : "cc"); + return res; +} + +#else +#error "Unsupported compiler" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_ATOMIC_INTERNAL_H__ */ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.c b/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.c new file mode 100644 index 0000000..945ae2d --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.c @@ -0,0 +1,399 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" + #if NRF_MODULE_ENABLED(NRF_BALLOC) + +#include "nrf_section.h" +#include "nrf_balloc.h" +#include "app_util_platform.h" + + +#if NRF_BALLOC_CONFIG_LOG_ENABLED + #define NRF_LOG_LEVEL NRF_BALLOC_CONFIG_LOG_LEVEL + #define NRF_LOG_INITIAL_LEVEL NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL + #define NRF_LOG_INFO_COLOR NRF_BALLOC_CONFIG_INFO_COLOR + #define NRF_LOG_DEBUG_COLOR NRF_BALLOC_CONFIG_DEBUG_COLOR +#else + #define NRF_LOG_LEVEL 0 +#endif // NRF_BALLOC_CONFIG_LOG_ENABLED +#include "nrf_log.h" + +#define HEAD_GUARD_FILL 0xBAADF00D /**< Magic number used to mark head guard.*/ +#define TAIL_GUARD_FILL 0xBAADCAFE /**< Magic number used to mark tail guard.*/ +#define FREE_MEM_FILL 0xBAADBAAD /**< Magic number used to mark free memory.*/ + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define POOL_ID(_p_pool) _p_pool->p_name +#define POOL_MARKER "%s" +#else +#define POOL_ID(_p_pool) _p_pool +#define POOL_MARKER "0x%08X" +#endif + +NRF_SECTION_DEF(nrf_balloc, nrf_balloc_t); + +#if NRF_BALLOC_CLI_CMDS +#include "nrf_cli.h" + +static void nrf_balloc_status(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + UNUSED_PARAMETER(argv); + + if (nrf_cli_help_requested(p_cli)) + { + nrf_cli_help_print(p_cli, NULL, 0); + return; + } + + if (argc > 1) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Bad argument count"); + return; + } + + uint32_t num_of_instances = NRF_SECTION_ITEM_COUNT(nrf_balloc, nrf_balloc_t); + uint32_t i; + + for (i = 0; i < num_of_instances; i++) + { + const nrf_balloc_t * p_instance = NRF_SECTION_ITEM_GET(nrf_balloc, nrf_balloc_t, i); + + uint32_t element_size = NRF_BALLOC_ELEMENT_SIZE(p_instance); + uint32_t dbg_addon = p_instance->block_size - element_size; + uint32_t pool_size = p_instance->p_stack_limit - p_instance->p_stack_base; + uint32_t max_util = nrf_balloc_max_utilization_get(p_instance); + uint32_t util = nrf_balloc_utilization_get(p_instance); + const char * p_name = p_instance->p_name; + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, + "%s\r\n\t- Element size:\t%d + %d bytes of debug information\r\n" + "\t- Usage:\t%u%% (%u out of %u elements)\r\n" + "\t- Maximum:\t%u%% (%u out of %u elements)\r\n\r\n", + p_name, element_size, dbg_addon, + 100ul * util/pool_size, util,pool_size, + 100ul * max_util/pool_size, max_util,pool_size); + + } +} +// Register "balloc" command and its subcommands in CLI. +NRF_CLI_CREATE_STATIC_SUBCMD_SET(nrf_balloc_commands) +{ + NRF_CLI_CMD(status, NULL, "Print status of balloc instances.", nrf_balloc_status), + NRF_CLI_SUBCMD_SET_END +}; + +NRF_CLI_CMD_REGISTER(balloc, &nrf_balloc_commands, "Commands for BALLOC management", nrf_balloc_status); +#endif //NRF_BALLOC_CLI_CMDS + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED +/**@brief Validate block memory, prepare block guards, and calculate pointer to the element. + * + * @param[in] p_pool Pointer to the memory pool. + * @param[in] p_head Pointer to the beginning of the block. + * + * @return Pointer to the element. + */ +__STATIC_INLINE void * nrf_balloc_block_unwrap(nrf_balloc_t const * p_pool, void * p_head) +{ + ASSERT((p_pool != NULL) && ((p_pool->block_size % sizeof(uint32_t)) == 0)); + ASSERT((p_head != NULL) && (((uint32_t)(p_head) % sizeof(uint32_t)) == 0)); + + uint32_t head_words = NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(p_pool->debug_flags); + uint32_t tail_words = NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(p_pool->debug_flags); + + uint32_t * p_tail = (uint32_t *)((size_t)(p_head) + p_pool->block_size); + uint32_t * p_element = (uint32_t *)p_head + head_words; + + if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) + { + for (uint32_t * ptr = p_head; ptr < p_tail; ptr++) + { + if (*ptr != FREE_MEM_FILL) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Detected free memory corruption at 0x%08X (0x%08X != 0x%08X)", + ptr, *ptr, FREE_MEM_FILL); + APP_ERROR_CHECK_BOOL(false); + } + } + } + + for (uint32_t * ptr = p_head; ptr < p_element; ptr++) + { + *ptr = HEAD_GUARD_FILL; + } + + for (uint32_t * ptr = ( p_tail - tail_words); ptr < p_tail; ptr++) + { + *ptr = TAIL_GUARD_FILL; + } + + return p_element; +} + +/**@brief Calculate pointer to the block, validate block guards, and mark block memory as free. + * + * @param[in] p_pool Pointer to the memory pool. + * @param[in] p_element Pointer to the element. + * + * @return Pointer to the beginning of the block. + */ +__STATIC_INLINE void * nrf_balloc_element_wrap(nrf_balloc_t const * p_pool, void * p_element) +{ + ASSERT((p_pool != NULL) && ((p_pool->block_size % sizeof(uint32_t)) == 0)); + ASSERT((p_element != NULL) && (((uint32_t)(p_element) % sizeof(uint32_t)) == 0)); + + uint32_t head_words = NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(p_pool->debug_flags); + uint32_t tail_words = NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(p_pool->debug_flags); + + uint32_t * p_head = (uint32_t *)p_element - head_words; + uint32_t * p_tail = (uint32_t *)((size_t)(p_head) + p_pool->block_size); + + for (uint32_t * ptr = p_head; ptr < (uint32_t *)p_element; ptr++) + { + if (*ptr != HEAD_GUARD_FILL) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Detected Head Guard corruption at 0x%08X (0x%08X != 0x%08X)", + ptr, *ptr, HEAD_GUARD_FILL); + APP_ERROR_CHECK_BOOL(false); + } + } + + for (uint32_t * ptr = ( p_tail - tail_words); ptr < p_tail; ptr++) + { + if (*ptr != TAIL_GUARD_FILL) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Detected Tail Guard corruption at 0x%08X (0x%08X != 0x%08X)", + ptr, *ptr, TAIL_GUARD_FILL); + APP_ERROR_CHECK_BOOL(false); + } + } + + if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) + { + for (uint32_t * ptr = p_head; ptr < p_tail; ptr++) + { + *ptr = FREE_MEM_FILL; + } + } + + return p_head; +} + +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + +/**@brief Convert block index to a pointer. + * + * @param[in] p_pool Pointer to the memory pool. + * @param[in] idx Index of the block. + * + * @return Pointer to the beginning of the block. + */ +static void * nrf_balloc_idx2block(nrf_balloc_t const * p_pool, uint8_t idx) +{ + ASSERT(p_pool != NULL); + return (uint8_t *)(p_pool->p_memory_begin) + ((size_t)(idx) * p_pool->block_size); +} + +/**@brief Convert block pointer to index. + * + * @param[in] p_pool Pointer to the memory pool. + * @param[in] p_block Pointer to the beginning of the block. + * + * @return Index of the block. + */ +static uint8_t nrf_balloc_block2idx(nrf_balloc_t const * p_pool, void const * p_block) +{ + ASSERT(p_pool != NULL); + return ((size_t)(p_block) - (size_t)(p_pool->p_memory_begin)) / p_pool->block_size; +} + +ret_code_t nrf_balloc_init(nrf_balloc_t const * p_pool) +{ + uint8_t pool_size; + + VERIFY_PARAM_NOT_NULL(p_pool); + + ASSERT(p_pool->p_cb); + ASSERT(p_pool->p_stack_base); + ASSERT(p_pool->p_stack_limit); + ASSERT(p_pool->p_memory_begin); + ASSERT(p_pool->block_size); + + pool_size = p_pool->p_stack_limit - p_pool->p_stack_base; + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + void *p_memory_end = (uint8_t *)(p_pool->p_memory_begin) + (pool_size * p_pool->block_size); + if (NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(p_pool->debug_flags)) + { + for (uint32_t * ptr = p_pool->p_memory_begin; ptr < (uint32_t *)(p_memory_end); ptr++) + { + *ptr = FREE_MEM_FILL; + } + } +#endif + + NRF_LOG_INST_INFO(p_pool->p_log, "Initialized (size: %u x %u = %u bytes)", + pool_size, + p_pool->block_size, + pool_size * p_pool->block_size); + + p_pool->p_cb->p_stack_pointer = p_pool->p_stack_base; + while (pool_size--) + { + *(p_pool->p_cb->p_stack_pointer)++ = pool_size; + } + + p_pool->p_cb->max_utilization = 0; + + return NRF_SUCCESS; +} + +void * nrf_balloc_alloc(nrf_balloc_t const * p_pool) +{ + ASSERT(p_pool != NULL); + + void * p_block = NULL; + + CRITICAL_REGION_ENTER(); + + if (p_pool->p_cb->p_stack_pointer > p_pool->p_stack_base) + { + // Allocate block. + p_block = nrf_balloc_idx2block(p_pool, *--(p_pool->p_cb->p_stack_pointer)); + + // Update utilization statistics. + uint8_t utilization = p_pool->p_stack_limit - p_pool->p_cb->p_stack_pointer; + if (p_pool->p_cb->max_utilization < utilization) + { + p_pool->p_cb->max_utilization = utilization; + } + } + + CRITICAL_REGION_EXIT(); + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + if (p_block != NULL) + { + p_block = nrf_balloc_block_unwrap(p_pool, p_block); + } +#endif + + NRF_LOG_INST_DEBUG(p_pool->p_log, "Allocating element: 0x%08X", p_block); + + return p_block; +} + +void nrf_balloc_free(nrf_balloc_t const * p_pool, void * p_element) +{ + ASSERT(p_pool != NULL); + ASSERT(p_element != NULL) + + NRF_LOG_INST_DEBUG(p_pool->p_log, "Freeing element: 0x%08X", p_element); + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + void * p_block = nrf_balloc_element_wrap(p_pool, p_element); + + // These checks could be done outside critical region as they use only pool configuration data. + if (NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(p_pool->debug_flags)) + { + uint8_t pool_size = p_pool->p_stack_limit - p_pool->p_stack_base; + void *p_memory_end = (uint8_t *)(p_pool->p_memory_begin) + (pool_size * p_pool->block_size); + + // Check if the element belongs to this pool. + if ((p_block < p_pool->p_memory_begin) || (p_block >= p_memory_end)) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Attempted to free element (0x%08X) that does not belong to the pool.", + p_element); + APP_ERROR_CHECK_BOOL(false); + } + + // Check if the pointer is valid. + if ((((size_t)(p_block) - (size_t)(p_pool->p_memory_begin)) % p_pool->block_size) != 0) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Attempted to free corrupted element address (0x%08X).", p_element); + APP_ERROR_CHECK_BOOL(false); + } + } +#else + void * p_block = p_element; +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + + CRITICAL_REGION_ENTER(); + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + // These checks have to be done in critical region as they use p_pool->p_stack_pointer. + if (NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(p_pool->debug_flags)) + { + // Check for allocated/free ballance. + if (p_pool->p_cb->p_stack_pointer >= p_pool->p_stack_limit) + { + NRF_LOG_INST_ERROR(p_pool->p_log, + "Attempted to free an element (0x%08X) while the pool is full.", + p_element); + APP_ERROR_CHECK_BOOL(false); + } + } + + if (NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_GET(p_pool->debug_flags)) + { + // Check for double free. + for (uint8_t * p_idx = p_pool->p_stack_base; p_idx < p_pool->p_cb->p_stack_pointer; p_idx++) + { + if (nrf_balloc_idx2block(p_pool, *p_idx) == p_block) + { + NRF_LOG_INST_ERROR(p_pool->p_log, "Attempted to double-free an element (0x%08X).", + p_element); + APP_ERROR_CHECK_BOOL(false); + } + } + } +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + + // Free the element. + *(p_pool->p_cb->p_stack_pointer)++ = nrf_balloc_block2idx(p_pool, p_block); + + CRITICAL_REGION_EXIT(); +} + +#endif // NRF_MODULE_ENABLED(NRF_BALLOC) diff --git a/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.h b/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.h new file mode 100644 index 0000000..68dd329 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/balloc/nrf_balloc.h @@ -0,0 +1,351 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** + * @defgroup nrf_balloc Block memory allocator + * @{ + * @ingroup app_common + * @brief This module handles block memory allocator features. + */ + + +#ifndef NRF_BALLOC_H__ +#define NRF_BALLOC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sdk_errors.h" +#include "sdk_config.h" +#include "app_util_platform.h" +#include "app_util.h" +#include "nrf_log_instance.h" +#include "nrf_section.h" + +/** @brief Name of the module used for logger messaging. + */ +#define NRF_BALLOC_LOG_NAME balloc + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED || NRF_BALLOC_CLI_CMDS +#define NRF_BALLOC_HAS_NAME 1 +#else +#define NRF_BALLOC_HAS_NAME 0 +#endif + +/**@defgroup NRF_BALLOC_DEBUG Macros for preparing debug flags for block allocator module. + * @{ */ +#define NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_SET(words) (((words) & 0xFF) << 0) +#define NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(flags) (((flags) >> 0) & 0xFF) +#define NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_SET(words) (((words) & 0xFF) << 8) +#define NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(flags) (((flags) >> 8) & 0xFF) + +#define NRF_BALLOC_DEBUG_BASIC_CHECKS_SET(enable) (!!(enable) << 16) +#define NRF_BALLOC_DEBUG_BASIC_CHECKS_GET(flags) (flags & (1 << 16)) +#define NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_SET(enable) (!!(enable) << 17) +#define NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_GET(flags) (flags & (1 << 17)) +#define NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_SET(enable) (!!(enable) << 18) +#define NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_GET(flags) (flags & (1 << 18)) +/**@} */ + +/**@brief Default debug flags for @ref nrf_balloc. This is used by the @ref NRF_BALLOC_DEF macro. + * Flags can be changed in @ref sdk_config. + */ +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + #define NRF_BALLOC_DEFAULT_DEBUG_FLAGS \ + ( \ + NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_SET(NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS) | \ + NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_SET(NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS) | \ + NRF_BALLOC_DEBUG_BASIC_CHECKS_SET(NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED) | \ + NRF_BALLOC_DEBUG_DOUBLE_FREE_CHECK_SET(NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED) | \ + NRF_BALLOC_DEBUG_DATA_TRASHING_CHECK_SET(NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED) \ + ) +#else + #define NRF_BALLOC_DEFAULT_DEBUG_FLAGS 0 +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + +/**@brief Block memory allocator control block.*/ +typedef struct +{ + uint8_t * p_stack_pointer; //!< Current allocation stack pointer. + uint8_t max_utilization; //!< Maximum utilization of the memory pool. +} nrf_balloc_cb_t; + +/**@brief Block memory allocator pool instance. The pool is made of elements of the same size. */ +typedef struct +{ + nrf_balloc_cb_t * p_cb; //!< Pointer to the instance control block. + uint8_t * p_stack_base; //!< Base of the allocation stack. + /**< + * Stack is used to store handlers to not allocated elements. + */ + uint8_t * p_stack_limit; //!< Maximum possible value of the allocation stack pointer. + void * p_memory_begin; //!< Pointer to the start of the memory pool. + /**< + * Memory is used as a heap for blocks. + */ + NRF_LOG_INSTANCE_PTR_DECLARE(p_log) //!< Pointer to instance of the logger object (Conditionally compiled). +#if NRF_BALLOC_HAS_NAME + const char * p_name; //!< Pointer to string with pool name. +#endif +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + uint32_t debug_flags; //!< Debugging settings. + /**< + * Debug flag should be created by @ref NRF_BALLOC_DEBUG. + */ +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + uint16_t block_size; //!< Size of the allocated block (including debug overhead). + /**< + * Single block contains user element with header and tail + * words. + */ +} nrf_balloc_t; + +/**@brief Get total memory consumed by single block (element size with overhead caused by debug + * flags). + * + * @param[in] _element_size Size of an element. + * @param[in] _debug_flags Debug flags. + */ +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED + #define NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) \ + ( \ + (sizeof(uint32_t) * NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET(_debug_flags)) + \ + ALIGN_NUM(sizeof(uint32_t), (_element_size)) + \ + (sizeof(uint32_t) * NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET(_debug_flags)) \ + ) +#else + #define NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) \ + ALIGN_NUM(sizeof(uint32_t), (_element_size)) +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + + +/**@brief Get element size ( excluding debugging overhead is present) + * flags). + * + * @param[in] _p_balloc Pointer to balloc instance. + */ +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_ELEMENT_SIZE(_p_balloc) \ + (ALIGN_NUM(sizeof(uint32_t), (_p_balloc)->block_size) - \ + ((sizeof(uint32_t) * NRF_BALLOC_DEBUG_HEAD_GUARD_WORDS_GET((_p_balloc)->debug_flags)) + \ + (sizeof(uint32_t) * NRF_BALLOC_DEBUG_TAIL_GUARD_WORDS_GET((_p_balloc)->debug_flags)))) +#else +#define NRF_BALLOC_ELEMENT_SIZE(_p_balloc) \ + (_p_balloc)->block_size +#endif // NRF_BALLOC_CONFIG_DEBUG_ENABLED + +#if NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) .debug_flags = (_debug_flags), +#else +#define __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) +#endif + +#if NRF_BALLOC_HAS_NAME +#define __NRF_BALLOC_ASSIGN_POOL_NAME(_name) .p_name = STRINGIFY(_name), +#else +#define __NRF_BALLOC_ASSIGN_POOL_NAME(_name) +#endif + + +/**@brief Create a block allocator instance with custom debug flags. + * + * @note This macro reserves memory for the given block allocator instance. + * + * @param[in] _name Name of the allocator. + * @param[in] _element_size Size of one element. + * @param[in] _pool_size Size of the pool. + * @param[in] _debug_flags Debug flags (@ref NRF_BALLOC_DEBUG). + */ +#define NRF_BALLOC_DBG_DEF(_name, _element_size, _pool_size, _debug_flags) \ + STATIC_ASSERT((_pool_size) <= UINT8_MAX); \ + static uint8_t CONCAT_2(_name, _nrf_balloc_pool_stack)[(_pool_size)]; \ + static uint32_t CONCAT_2(_name,_nrf_balloc_pool_mem) \ + [NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags) * (_pool_size) / sizeof(uint32_t)]; \ + static nrf_balloc_cb_t CONCAT_2(_name,_nrf_balloc_cb); \ + NRF_LOG_INSTANCE_REGISTER(NRF_BALLOC_LOG_NAME, _name, \ + NRF_BALLOC_CONFIG_INFO_COLOR, \ + NRF_BALLOC_CONFIG_DEBUG_COLOR, \ + NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL, \ + NRF_BALLOC_CONFIG_LOG_ENABLED ? \ + NRF_BALLOC_CONFIG_LOG_LEVEL : NRF_LOG_SEVERITY_NONE); \ + NRF_SECTION_ITEM_REGISTER(nrf_balloc, const nrf_balloc_t _name) = \ + { \ + .p_cb = &CONCAT_2(_name,_nrf_balloc_cb), \ + .p_stack_base = CONCAT_2(_name,_nrf_balloc_pool_stack), \ + .p_stack_limit = CONCAT_2(_name,_nrf_balloc_pool_stack) + (_pool_size), \ + .p_memory_begin = CONCAT_2(_name,_nrf_balloc_pool_mem), \ + .block_size = NRF_BALLOC_BLOCK_SIZE(_element_size, _debug_flags), \ + \ + NRF_LOG_INSTANCE_PTR_INIT(p_log, NRF_BALLOC_LOG_NAME, _name) \ + __NRF_BALLOC_ASSIGN_POOL_NAME(_name) \ + __NRF_BALLOC_ASSIGN_DEBUG_FLAGS(_debug_flags) \ + } + +/**@brief Create a block allocator instance. + * + * @note This macro reserves memory for the given block allocator instance. + * + * @param[in] _name Name of the allocator. + * @param[in] _element_size Size of one element. + * @param[in] _pool_size Size of the pool. + */ +#define NRF_BALLOC_DEF(_name, _element_size, _pool_size) \ + NRF_BALLOC_DBG_DEF(_name, _element_size, _pool_size, NRF_BALLOC_DEFAULT_DEBUG_FLAGS) + +/**@brief Create a block allocator interface. + * + * @param[in] _type Type which is allocated. + * @param[in] _name Name of the allocator. + */ +#define NRF_BALLOC_INTERFACE_DEC(_type, _name) \ + _type * CONCAT_2(_name,_alloc)(void); \ + void CONCAT_2(_name,_free)(_type * p_element) + +/**@brief Define a custom block allocator interface. + * + * @param[in] _attr Function attribute that will be added to allocator function definition. + * @param[in] _type Type which is allocated. + * @param[in] _name Name of the allocator. + * @param[in] _p_pool Pool from which data will be allocated. + */ +#define NRF_BALLOC_INTERFACE_CUSTOM_DEF(_attr, _type, _name, _p_pool) \ + _attr _type * CONCAT_2(_name,_alloc)(void) \ + { \ + GCC_PRAGMA("GCC diagnostic push") \ + GCC_PRAGMA("GCC diagnostic ignored \"-Waddress\"") \ + ASSERT((_p_pool) != NULL); \ + ASSERT((_p_pool)->block_size >= \ + NRF_BALLOC_BLOCK_SIZE(sizeof(_type), (_p_pool)->debug_flags)); \ + GCC_PRAGMA("GCC diagnostic pop") \ + return (_type *)(nrf_balloc_alloc(_p_pool)); \ + } \ + \ + _attr void CONCAT_2(_name,_free)(_type * p_element) \ + { \ + GCC_PRAGMA("GCC diagnostic push") \ + GCC_PRAGMA("GCC diagnostic ignored \"-Waddress\"") \ + ASSERT((_p_pool) != NULL); \ + ASSERT((_p_pool)->block_size >= \ + NRF_BALLOC_BLOCK_SIZE(sizeof(_type), (_p_pool)->debug_flags)); \ + GCC_PRAGMA("GCC diagnostic pop") \ + nrf_balloc_free((_p_pool), p_element); \ + } + +/**@brief Define block allocator interface. + * + * @param[in] _type Type which is allocated. + * @param[in] _name Name of the allocator. + * @param[in] _p_pool Pool from which data will be allocated. + */ +#define NRF_BALLOC_INTERFACE_DEF(_type, _name, _p_pool) \ + NRF_BALLOC_INTERFACE_CUSTOM_DEF(/* empty */, _type, _name, _p_pool) + +/**@brief Define a local block allocator interface. + * + * @param[in] _type Type which is allocated. + * @param[in] _name Name of the allocator. + * @param[in] _p_pool Pool from which data will be allocated. + */ +#define NRF_BALLOC_INTERFACE_LOCAL_DEF(_type, _name, _p_pool) \ + NRF_BALLOC_INTERFACE_CUSTOM_DEF(static, _type, _name, _p_pool) + +/**@brief Function for initializing a block memory allocator pool. + * + * @param[out] p_pool Pointer to the pool that is to be initialized. + * + * @return NRF_SUCCESS on success, otherwise error code. + */ +ret_code_t nrf_balloc_init(nrf_balloc_t const * p_pool); + +/**@brief Function for allocating an element from the pool. + * + * @note This module guarantees that the returned memory is aligned to 4. + * + * @param[in] p_pool Pointer to the memory pool from which the element will be allocated. + * + * @return Allocated element or NULL if the specified pool is empty. + */ +void * nrf_balloc_alloc(nrf_balloc_t const * p_pool); + +/**@brief Function for freeing an element back to the pool. + * + * @param[in] p_pool Pointer to the memory pool. + * @param[in] p_element Element to be freed. + */ +void nrf_balloc_free(nrf_balloc_t const * p_pool, void * p_element); + +/**@brief Function for getting maximum memory pool utilization. + * + * @param[in] p_pool Pointer to the memory pool instance. + * + * @return Maximum number of elements allocated from the pool. + */ +__STATIC_INLINE uint8_t nrf_balloc_max_utilization_get(nrf_balloc_t const * p_pool); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint8_t nrf_balloc_max_utilization_get(nrf_balloc_t const * p_pool) +{ + ASSERT(p_pool != NULL); + return p_pool->p_cb->max_utilization; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/**@brief Function for getting current memory pool utilization. + * + * @param[in] p_pool Pointer to the memory pool instance. + * + * @return Maximum number of elements allocated from the pool. + */ +__STATIC_INLINE uint8_t nrf_balloc_utilization_get(nrf_balloc_t const * p_pool); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint8_t nrf_balloc_utilization_get(nrf_balloc_t const * p_pool) +{ + ASSERT(p_pool != NULL); + return (p_pool->p_stack_limit - p_pool->p_cb->p_stack_pointer); +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +#ifdef __cplusplus +} +#endif + +#endif // NRF_BALLOC_H__ +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/bsp/bsp.c b/HAL_Driver/sdk/components/libraries/bsp/bsp.c new file mode 100644 index 0000000..209f11b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/bsp/bsp.c @@ -0,0 +1,638 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "bsp.h" +#include +#include +#include "nordic_common.h" +#include "nrf.h" +#include "nrf_gpio.h" +#include "nrf_error.h" +#include "bsp_config.h" +#include "boards.h" + +#ifndef BSP_SIMPLE +#include "app_timer.h" +#include "app_button.h" +#endif // BSP_SIMPLE + +#if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) +static bsp_indication_t m_stable_state = BSP_INDICATE_IDLE; +static bool m_leds_clear = false; +static uint32_t m_indication_type = 0; +static bool m_alert_on = false; +APP_TIMER_DEF(m_bsp_leds_tmr); +APP_TIMER_DEF(m_bsp_alert_tmr); +#endif // LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + +#if BUTTONS_NUMBER > 0 +#ifndef BSP_SIMPLE +static bsp_event_callback_t m_registered_callback = NULL; +static bsp_button_event_cfg_t m_events_list[BUTTONS_NUMBER] = {{BSP_EVENT_NOTHING, BSP_EVENT_NOTHING}}; +APP_TIMER_DEF(m_bsp_button_tmr); +static void bsp_button_event_handler(uint8_t pin_no, uint8_t button_action); +#endif // BSP_SIMPLE + +#ifndef BSP_SIMPLE +static const app_button_cfg_t app_buttons[BUTTONS_NUMBER] = +{ + #ifdef BSP_BUTTON_0 + {BSP_BUTTON_0, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_0 + + #ifdef BSP_BUTTON_1 + {BSP_BUTTON_1, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_1 + + #ifdef BSP_BUTTON_2 + {BSP_BUTTON_2, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_2 + + #ifdef BSP_BUTTON_3 + {BSP_BUTTON_3, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_3 + + #ifdef BSP_BUTTON_4 + {BSP_BUTTON_4, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_4 + + #ifdef BSP_BUTTON_5 + {BSP_BUTTON_5, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_5 + + #ifdef BSP_BUTTON_6 + {BSP_BUTTON_6, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_6 + + #ifdef BSP_BUTTON_7 + {BSP_BUTTON_7, false, BUTTON_PULL, bsp_button_event_handler}, + #endif // BUTTON_7 + +}; +#endif // BSP_SIMPLE +#endif // BUTTONS_NUMBER > 0 + +#if (BUTTONS_NUMBER > 0) +bool bsp_button_is_pressed(uint32_t button) +{ + if (button < BUTTONS_NUMBER) + { + return bsp_board_button_state_get(button); + } + else + { + //If button is not present always return false + return false; + } +} +#endif + +#if (BUTTONS_NUMBER > 0) && !(defined BSP_SIMPLE) +/**@brief Function for handling button events. + * + * @param[in] pin_no The pin number of the button pressed. + * @param[in] button_action Action button. + */ +static void bsp_button_event_handler(uint8_t pin_no, uint8_t button_action) +{ + bsp_event_t event = BSP_EVENT_NOTHING; + uint32_t button = 0; + uint32_t err_code; + static uint8_t current_long_push_pin_no; /**< Pin number of a currently pushed button, that could become a long push if held long enough. */ + static bsp_event_t release_event_at_push[BUTTONS_NUMBER]; /**< Array of what the release event of each button was last time it was pushed, so that no release event is sent if the event was bound after the push of the button. */ + + button = bsp_board_pin_to_button_idx(pin_no); + + if (button < BUTTONS_NUMBER) + { + switch (button_action) + { + case APP_BUTTON_PUSH: + event = m_events_list[button].push_event; + if (m_events_list[button].long_push_event != BSP_EVENT_NOTHING) + { + err_code = app_timer_start(m_bsp_button_tmr, APP_TIMER_TICKS(BSP_LONG_PUSH_TIMEOUT_MS), (void*)¤t_long_push_pin_no); + if (err_code == NRF_SUCCESS) + { + current_long_push_pin_no = pin_no; + } + } + release_event_at_push[button] = m_events_list[button].release_event; + break; + case APP_BUTTON_RELEASE: + (void)app_timer_stop(m_bsp_button_tmr); + if (release_event_at_push[button] == m_events_list[button].release_event) + { + event = m_events_list[button].release_event; + } + break; + case BSP_BUTTON_ACTION_LONG_PUSH: + event = m_events_list[button].long_push_event; + } + } + + if ((event != BSP_EVENT_NOTHING) && (m_registered_callback != NULL)) + { + m_registered_callback(event); + } +} + +/**@brief Handle events from button timer. + * + * @param[in] p_context parameter registered in timer start function. + */ +static void button_timer_handler(void * p_context) +{ + bsp_button_event_handler(*(uint8_t *)p_context, BSP_BUTTON_ACTION_LONG_PUSH); +} + + +#endif // (BUTTONS_NUMBER > 0) && !(defined BSP_SIMPLE) + + +#if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) +static void leds_off(void) +{ + if (m_alert_on) + { + uint32_t i; + for (i = 0; i < LEDS_NUMBER; i++) + { + if (i != BSP_LED_ALERT) + { + bsp_board_led_off(i); + } + } + } + else + { + bsp_board_leds_off(); + } +} + + +/**@brief Configure leds to indicate required state. + * @param[in] indicate State to be indicated. + */ +static uint32_t bsp_led_indication(bsp_indication_t indicate) +{ + uint32_t err_code = NRF_SUCCESS; + uint32_t next_delay = 0; + + if (m_leds_clear) + { + m_leds_clear = false; + leds_off(); + } + + switch (indicate) + { + case BSP_INDICATE_IDLE: + leds_off(); + err_code = app_timer_stop(m_bsp_leds_tmr); + m_stable_state = indicate; + break; + + case BSP_INDICATE_SCANNING: + case BSP_INDICATE_ADVERTISING: + // in advertising blink LED_0 + if (bsp_board_led_state_get(BSP_LED_INDICATE_INDICATE_ADVERTISING)) + { + bsp_board_led_off(BSP_LED_INDICATE_INDICATE_ADVERTISING); + next_delay = indicate == + BSP_INDICATE_ADVERTISING ? ADVERTISING_LED_OFF_INTERVAL : + ADVERTISING_SLOW_LED_OFF_INTERVAL; + } + else + { + bsp_board_led_on(BSP_LED_INDICATE_INDICATE_ADVERTISING); + next_delay = indicate == + BSP_INDICATE_ADVERTISING ? ADVERTISING_LED_ON_INTERVAL : + ADVERTISING_SLOW_LED_ON_INTERVAL; + } + + m_stable_state = indicate; + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(next_delay), NULL); + break; + + case BSP_INDICATE_ADVERTISING_WHITELIST: + // in advertising quickly blink LED_0 + if (bsp_board_led_state_get(BSP_LED_INDICATE_ADVERTISING_WHITELIST)) + { + bsp_board_led_off(BSP_LED_INDICATE_ADVERTISING_WHITELIST); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_WHITELIST ? + ADVERTISING_WHITELIST_LED_OFF_INTERVAL : + ADVERTISING_SLOW_LED_OFF_INTERVAL; + } + else + { + bsp_board_led_on(BSP_LED_INDICATE_ADVERTISING_WHITELIST); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_WHITELIST ? + ADVERTISING_WHITELIST_LED_ON_INTERVAL : + ADVERTISING_SLOW_LED_ON_INTERVAL; + } + m_stable_state = indicate; + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(next_delay), NULL); + break; + + case BSP_INDICATE_ADVERTISING_SLOW: + // in advertising slowly blink LED_0 + if (bsp_board_led_state_get(BSP_LED_INDICATE_ADVERTISING_SLOW)) + { + bsp_board_led_off(BSP_LED_INDICATE_ADVERTISING_SLOW); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_SLOW ? ADVERTISING_SLOW_LED_OFF_INTERVAL : + ADVERTISING_SLOW_LED_OFF_INTERVAL; + } + else + { + bsp_board_led_on(BSP_LED_INDICATE_ADVERTISING_SLOW); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_SLOW ? ADVERTISING_SLOW_LED_ON_INTERVAL : + ADVERTISING_SLOW_LED_ON_INTERVAL; + } + m_stable_state = indicate; + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(next_delay), NULL); + break; + + case BSP_INDICATE_ADVERTISING_DIRECTED: + // in advertising very quickly blink LED_0 + if (bsp_board_led_state_get(BSP_LED_INDICATE_ADVERTISING_DIRECTED)) + { + bsp_board_led_off(BSP_LED_INDICATE_ADVERTISING_DIRECTED); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_DIRECTED ? + ADVERTISING_DIRECTED_LED_OFF_INTERVAL : + ADVERTISING_SLOW_LED_OFF_INTERVAL; + } + else + { + bsp_board_led_on(BSP_LED_INDICATE_ADVERTISING_DIRECTED); + next_delay = indicate == + BSP_INDICATE_ADVERTISING_DIRECTED ? + ADVERTISING_DIRECTED_LED_ON_INTERVAL : + ADVERTISING_SLOW_LED_ON_INTERVAL; + } + m_stable_state = indicate; + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(next_delay), NULL); + break; + + case BSP_INDICATE_BONDING: + // in bonding fast blink LED_0 + bsp_board_led_invert(BSP_LED_INDICATE_BONDING); + + m_stable_state = indicate; + err_code = + app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(BONDING_INTERVAL), NULL); + break; + + case BSP_INDICATE_CONNECTED: + bsp_board_led_on(BSP_LED_INDICATE_CONNECTED); + m_stable_state = indicate; + break; + + case BSP_INDICATE_SENT_OK: + // when sending shortly invert LED_1 + m_leds_clear = true; + bsp_board_led_invert(BSP_LED_INDICATE_SENT_OK); + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(SENT_OK_INTERVAL), NULL); + break; + + case BSP_INDICATE_SEND_ERROR: + // on receving error invert LED_1 for long time + m_leds_clear = true; + bsp_board_led_invert(BSP_LED_INDICATE_SEND_ERROR); + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(SEND_ERROR_INTERVAL), NULL); + break; + + case BSP_INDICATE_RCV_OK: + // when receving shortly invert LED_1 + m_leds_clear = true; + bsp_board_led_invert(BSP_LED_INDICATE_RCV_OK); + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(RCV_OK_INTERVAL), NULL); + break; + + case BSP_INDICATE_RCV_ERROR: + // on receving error invert LED_1 for long time + m_leds_clear = true; + bsp_board_led_invert(BSP_LED_INDICATE_RCV_ERROR); + err_code = app_timer_start(m_bsp_leds_tmr, APP_TIMER_TICKS(RCV_ERROR_INTERVAL), NULL); + break; + + case BSP_INDICATE_FATAL_ERROR: + // on fatal error turn on all leds + bsp_board_leds_on(); + m_stable_state = indicate; + break; + + case BSP_INDICATE_ALERT_0: + case BSP_INDICATE_ALERT_1: + case BSP_INDICATE_ALERT_2: + case BSP_INDICATE_ALERT_3: + case BSP_INDICATE_ALERT_OFF: + err_code = app_timer_stop(m_bsp_alert_tmr); + next_delay = (uint32_t)BSP_INDICATE_ALERT_OFF - (uint32_t)indicate; + + // a little trick to find out that if it did not fall through ALERT_OFF + if (next_delay && (err_code == NRF_SUCCESS)) + { + if (next_delay > 1) + { + err_code = app_timer_start(m_bsp_alert_tmr, + APP_TIMER_TICKS(((uint16_t)next_delay * ALERT_INTERVAL)), + NULL); + } + bsp_board_led_on(BSP_LED_ALERT); + m_alert_on = true; + } + else + { + bsp_board_led_off(BSP_LED_ALERT); + m_alert_on = false; + + } + break; + + case BSP_INDICATE_USER_STATE_OFF: + leds_off(); + m_stable_state = indicate; + break; + + case BSP_INDICATE_USER_STATE_0: + leds_off(); + bsp_board_led_on(BSP_LED_INDICATE_USER_LED1); + m_stable_state = indicate; + break; + + case BSP_INDICATE_USER_STATE_1: + leds_off(); + bsp_board_led_on(BSP_LED_INDICATE_USER_LED2); + m_stable_state = indicate; + break; + + case BSP_INDICATE_USER_STATE_2: + leds_off(); + bsp_board_led_on(BSP_LED_INDICATE_USER_LED1); + bsp_board_led_on(BSP_LED_INDICATE_USER_LED2); + m_stable_state = indicate; + break; + + case BSP_INDICATE_USER_STATE_3: + + case BSP_INDICATE_USER_STATE_ON: + bsp_board_leds_on(); + m_stable_state = indicate; + break; + + default: + break; + } + + return err_code; +} + + +/**@brief Handle events from leds timer. + * + * @note Timer handler does not support returning an error code. + * Errors from bsp_led_indication() are not propagated. + * + * @param[in] p_context parameter registered in timer start function. + */ +static void leds_timer_handler(void * p_context) +{ + UNUSED_PARAMETER(p_context); + + if (m_indication_type & BSP_INIT_LEDS) + { + UNUSED_VARIABLE(bsp_led_indication(m_stable_state)); + } +} + + +/**@brief Handle events from alert timer. + * + * @param[in] p_context parameter registered in timer start function. + */ +static void alert_timer_handler(void * p_context) +{ + UNUSED_PARAMETER(p_context); + bsp_board_led_invert(BSP_LED_ALERT); +} +#endif // #if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + + +/**@brief Configure indicators to required state. + */ +uint32_t bsp_indication_set(bsp_indication_t indicate) +{ + uint32_t err_code = NRF_SUCCESS; + +#if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + + if (m_indication_type & BSP_INIT_LEDS) + { + err_code = bsp_led_indication(indicate); + } + +#endif // LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + return err_code; +} + + +uint32_t bsp_init(uint32_t type, bsp_event_callback_t callback) +{ + uint32_t err_code = NRF_SUCCESS; + +#if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + m_indication_type = type; +#endif // LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + +#if (BUTTONS_NUMBER > 0) && !(defined BSP_SIMPLE) + m_registered_callback = callback; + + // BSP will support buttons and generate events + if (type & BSP_INIT_BUTTONS) + { + uint32_t num; + + for (num = 0; ((num < BUTTONS_NUMBER) && (err_code == NRF_SUCCESS)); num++) + { + err_code = bsp_event_to_button_action_assign(num, BSP_BUTTON_ACTION_PUSH, BSP_EVENT_DEFAULT); + } + + if (err_code == NRF_SUCCESS) + { + err_code = app_button_init((app_button_cfg_t *)app_buttons, + BUTTONS_NUMBER, + APP_TIMER_TICKS(50)); + } + + if (err_code == NRF_SUCCESS) + { + err_code = app_button_enable(); + } + + if (err_code == NRF_SUCCESS) + { + err_code = app_timer_create(&m_bsp_button_tmr, + APP_TIMER_MODE_SINGLE_SHOT, + button_timer_handler); + } + } +#elif (BUTTONS_NUMBER > 0) && (defined BSP_SIMPLE) + bsp_board_init(type); +#endif // (BUTTONS_NUMBER > 0) && !(defined BSP_SIMPLE) + +#if LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + if (type & BSP_INIT_LEDS) + { + //handle LEDs only. Buttons are already handled. + bsp_board_init(BSP_INIT_LEDS); + + // timers module must be already initialized! + if (err_code == NRF_SUCCESS) + { + err_code = + app_timer_create(&m_bsp_leds_tmr, APP_TIMER_MODE_SINGLE_SHOT, leds_timer_handler); + } + + if (err_code == NRF_SUCCESS) + { + err_code = + app_timer_create(&m_bsp_alert_tmr, APP_TIMER_MODE_REPEATED, alert_timer_handler); + } + } +#endif // LEDS_NUMBER > 0 && !(defined BSP_SIMPLE) + + return err_code; +} + + +#ifndef BSP_SIMPLE +/**@brief Assign specific event to button. + */ +uint32_t bsp_event_to_button_action_assign(uint32_t button, bsp_button_action_t action, bsp_event_t event) +{ + uint32_t err_code = NRF_SUCCESS; + +#if BUTTONS_NUMBER > 0 + if (button < BUTTONS_NUMBER) + { + if (event == BSP_EVENT_DEFAULT) + { + // Setting default action: BSP_EVENT_KEY_x for PUSH actions, BSP_EVENT_NOTHING for RELEASE and LONG_PUSH actions. + event = (action == BSP_BUTTON_ACTION_PUSH) ? (bsp_event_t)(BSP_EVENT_KEY_0 + button) : BSP_EVENT_NOTHING; + } + switch (action) + { + case BSP_BUTTON_ACTION_PUSH: + m_events_list[button].push_event = event; + break; + case BSP_BUTTON_ACTION_LONG_PUSH: + m_events_list[button].long_push_event = event; + break; + case BSP_BUTTON_ACTION_RELEASE: + m_events_list[button].release_event = event; + break; + default: + err_code = NRF_ERROR_INVALID_PARAM; + break; + } + } + else + { + err_code = NRF_ERROR_INVALID_PARAM; + } +#else + err_code = NRF_ERROR_INVALID_PARAM; +#endif // BUTTONS_NUMBER > 0 + + return err_code; +} + +#endif // BSP_SIMPLE + + +uint32_t bsp_buttons_enable() +{ +#if (BUTTONS_NUMBER > 0) && !defined(BSP_SIMPLE) + return app_button_enable(); +#else + return NRF_ERROR_NOT_SUPPORTED; +#endif +} + +uint32_t bsp_buttons_disable() +{ +#if (BUTTONS_NUMBER > 0) && !defined(BSP_SIMPLE) + return app_button_disable(); +#else + return NRF_ERROR_NOT_SUPPORTED; +#endif +} +static uint32_t wakeup_button_cfg(uint32_t button_idx, bool enable) +{ +#if !defined(BSP_SIMPLE) + if (button_idx < BUTTONS_NUMBER) + { + nrf_gpio_pin_sense_t sense = enable ? + (BUTTONS_ACTIVE_STATE ? NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW) : + NRF_GPIO_PIN_NOSENSE; + nrf_gpio_cfg_sense_set(bsp_board_button_idx_to_pin(button_idx), sense); + return NRF_SUCCESS; + } +#else + UNUSED_PARAMETER(button_idx); + UNUSED_PARAMETER(enable); +#endif + return NRF_ERROR_NOT_SUPPORTED; + +} +uint32_t bsp_wakeup_button_enable(uint32_t button_idx) +{ + return wakeup_button_cfg(button_idx, true); +} + +uint32_t bsp_wakeup_button_disable(uint32_t button_idx) +{ + return wakeup_button_cfg(button_idx, false); +} diff --git a/HAL_Driver/sdk/components/libraries/bsp/bsp.h b/HAL_Driver/sdk/components/libraries/bsp/bsp.h new file mode 100644 index 0000000..d8f9be9 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/bsp/bsp.h @@ -0,0 +1,307 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup bsp Board Support Package + * @{ + * @ingroup app_common + * + * @brief BSP module. + * @details This module provides a layer of abstraction from the board. + * It allows the user to indicate certain states on LEDs in a simple way. + * Module functionality can be modified by defining BSP_SIMPLE to reduce + * functionality of this module to enable and read state of the buttons. + */ + +#ifndef BSP_H__ +#define BSP_H__ + +#include +#include +#include "boards.h" + +#if !defined(BSP_DEFINES_ONLY) && !defined(BSP_SIMPLE) +#include "app_button.h" + +#define BSP_BUTTON_ACTION_PUSH (APP_BUTTON_PUSH) /**< Represents pushing a button. See @ref bsp_button_action_t. */ +#define BSP_BUTTON_ACTION_RELEASE (APP_BUTTON_RELEASE) /**< Represents releasing a button. See @ref bsp_button_action_t. */ +#define BSP_BUTTON_ACTION_LONG_PUSH (2) /**< Represents pushing and holding a button for @ref BSP_LONG_PUSH_TIMEOUT_MS milliseconds. See also @ref bsp_button_action_t. */ + +#endif + +/* BSP_UART_SUPPORT + * This define enables UART support module. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef uint8_t bsp_button_action_t; /**< The different actions that can be performed on a button. */ + +#define BSP_INDICATIONS_LIST { \ + "BSP_INDICATE_IDLE", \ + "BSP_INDICATE_SCANNING", \ + "BSP_INDICATE_ADVERTISING", \ + "BSP_INDICATE_ADVERTISING_WHITELIST", \ + "BSP_INDICATE_ADVERTISING_SLOW", \ + "BSP_INDICATE_ADVERTISING_DIRECTED", \ + "BSP_INDICATE_BONDING", \ + "BSP_INDICATE_CONNECTED", \ + "BSP_INDICATE_SENT_OK", \ + "BSP_INDICATE_SEND_ERROR", \ + "BSP_INDICATE_RCV_OK", \ + "BSP_INDICATE_RCV_ERROR", \ + "BSP_INDICATE_FATAL_ERROR", \ + "BSP_INDICATE_ALERT_0", \ + "BSP_INDICATE_ALERT_1", \ + "BSP_INDICATE_ALERT_2", \ + "BSP_INDICATE_ALERT_3", \ + "BSP_INDICATE_ALERT_OFF", \ + "BSP_INDICATE_USER_STATE_OFF", \ + "BSP_INDICATE_USER_STATE_0", \ + "BSP_INDICATE_USER_STATE_1", \ + "BSP_INDICATE_USER_STATE_2", \ + "BSP_INDICATE_USER_STATE_3", \ + "BSP_INDICATE_USER_STATE_ON" \ +} /**< See @ref examples_bsp_states for a list of how these states are indicated for the PCA10028/PCA10040 board and the PCA10031 dongle.*/ + + +/**@brief BSP indication states. + * + * @details See @ref examples_bsp_states for a list of how these states are indicated for the PCA10028/PCA10040 board and the PCA10031 dongle. + */ +typedef enum +{ + BSP_INDICATE_FIRST = 0, + BSP_INDICATE_IDLE = BSP_INDICATE_FIRST, /**< See \ref BSP_INDICATE_IDLE.*/ + BSP_INDICATE_SCANNING, /**< See \ref BSP_INDICATE_SCANNING.*/ + BSP_INDICATE_ADVERTISING, /**< See \ref BSP_INDICATE_ADVERTISING.*/ + BSP_INDICATE_ADVERTISING_WHITELIST, /**< See \ref BSP_INDICATE_ADVERTISING_WHITELIST.*/ + BSP_INDICATE_ADVERTISING_SLOW, /**< See \ref BSP_INDICATE_ADVERTISING_SLOW.*/ + BSP_INDICATE_ADVERTISING_DIRECTED, /**< See \ref BSP_INDICATE_ADVERTISING_DIRECTED.*/ + BSP_INDICATE_BONDING, /**< See \ref BSP_INDICATE_BONDING.*/ + BSP_INDICATE_CONNECTED, /**< See \ref BSP_INDICATE_CONNECTED.*/ + BSP_INDICATE_SENT_OK, /**< See \ref BSP_INDICATE_SENT_OK.*/ + BSP_INDICATE_SEND_ERROR, /**< See \ref BSP_INDICATE_SEND_ERROR.*/ + BSP_INDICATE_RCV_OK, /**< See \ref BSP_INDICATE_RCV_OK.*/ + BSP_INDICATE_RCV_ERROR, /**< See \ref BSP_INDICATE_RCV_ERROR.*/ + BSP_INDICATE_FATAL_ERROR, /**< See \ref BSP_INDICATE_FATAL_ERROR.*/ + BSP_INDICATE_ALERT_0, /**< See \ref BSP_INDICATE_ALERT_0.*/ + BSP_INDICATE_ALERT_1, /**< See \ref BSP_INDICATE_ALERT_1.*/ + BSP_INDICATE_ALERT_2, /**< See \ref BSP_INDICATE_ALERT_2.*/ + BSP_INDICATE_ALERT_3, /**< See \ref BSP_INDICATE_ALERT_3.*/ + BSP_INDICATE_ALERT_OFF, /**< See \ref BSP_INDICATE_ALERT_OFF.*/ + BSP_INDICATE_USER_STATE_OFF, /**< See \ref BSP_INDICATE_USER_STATE_OFF.*/ + BSP_INDICATE_USER_STATE_0, /**< See \ref BSP_INDICATE_USER_STATE_0.*/ + BSP_INDICATE_USER_STATE_1, /**< See \ref BSP_INDICATE_USER_STATE_1.*/ + BSP_INDICATE_USER_STATE_2, /**< See \ref BSP_INDICATE_USER_STATE_2.*/ + BSP_INDICATE_USER_STATE_3, /**< See \ref BSP_INDICATE_USER_STATE_3.*/ + BSP_INDICATE_USER_STATE_ON, /**< See \ref BSP_INDICATE_USER_STATE_ON.*/ + BSP_INDICATE_LAST = BSP_INDICATE_USER_STATE_ON +} bsp_indication_t; + +/**@brief BSP events. + * + * @note Events from BSP_EVENT_KEY_0 to BSP_EVENT_KEY_LAST are by default assigned to buttons. + */ +typedef enum +{ + BSP_EVENT_NOTHING = 0, /**< Assign this event to an action to prevent the action from generating an event (disable the action). */ + BSP_EVENT_DEFAULT, /**< Assign this event to an action to assign the default event to the action. */ + BSP_EVENT_CLEAR_BONDING_DATA, /**< Persistent bonding data should be erased. */ + BSP_EVENT_CLEAR_ALERT, /**< An alert should be cleared. */ + BSP_EVENT_DISCONNECT, /**< A link should be disconnected. */ + BSP_EVENT_ADVERTISING_START, /**< The device should start advertising. */ + BSP_EVENT_ADVERTISING_STOP, /**< The device should stop advertising. */ + BSP_EVENT_WHITELIST_OFF, /**< The device should remove its advertising whitelist. */ + BSP_EVENT_BOND, /**< The device should bond to the currently connected peer. */ + BSP_EVENT_RESET, /**< The device should reset. */ + BSP_EVENT_SLEEP, /**< The device should enter sleep mode. */ + BSP_EVENT_WAKEUP, /**< The device should wake up from sleep mode. */ + BSP_EVENT_SYSOFF, /**< The device should enter system off mode (without wakeup). */ + BSP_EVENT_DFU, /**< The device should enter DFU mode. */ + BSP_EVENT_KEY_0, /**< Default event of the push action of BSP_BUTTON_0 (only if this button is present). */ + BSP_EVENT_KEY_1, /**< Default event of the push action of BSP_BUTTON_1 (only if this button is present). */ + BSP_EVENT_KEY_2, /**< Default event of the push action of BSP_BUTTON_2 (only if this button is present). */ + BSP_EVENT_KEY_3, /**< Default event of the push action of BSP_BUTTON_3 (only if this button is present). */ + BSP_EVENT_KEY_4, /**< Default event of the push action of BSP_BUTTON_4 (only if this button is present). */ + BSP_EVENT_KEY_5, /**< Default event of the push action of BSP_BUTTON_5 (only if this button is present). */ + BSP_EVENT_KEY_6, /**< Default event of the push action of BSP_BUTTON_6 (only if this button is present). */ + BSP_EVENT_KEY_7, /**< Default event of the push action of BSP_BUTTON_7 (only if this button is present). */ + BSP_EVENT_KEY_LAST = BSP_EVENT_KEY_7, +} bsp_event_t; + + +typedef struct +{ + bsp_event_t push_event; /**< The event to fire on regular button press. */ + bsp_event_t long_push_event; /**< The event to fire on long button press. */ + bsp_event_t release_event; /**< The event to fire on button release. */ +} bsp_button_event_cfg_t; + +/**@brief BSP module event callback function type. + * + * @details Upon an event in the BSP module, this callback function will be called to notify + * the application about the event. + * + * @param[in] bsp_event_t BSP event type. + */ +typedef void (* bsp_event_callback_t)(bsp_event_t); + + +/**@brief Function for initializing BSP. + * + * @details The function initializes the board support package to allow state indication and + * button reaction. Default events are assigned to buttons. + * @note Before calling this function, you must initiate the following required modules: + * - @ref app_timer for LED support + * - @ref app_gpiote for button support + * + * @param[in] type Type of peripherals used. + * @param[in] callback Function to be called when button press/event is detected. + * + * @retval NRF_SUCCESS If the BSP module was successfully initialized. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized. + * @retval NRF_ERROR_NO_MEM If the maximum number of timers has already been reached. + * @retval NRF_ERROR_INVALID_PARAM If GPIOTE has too many users. + * @retval NRF_ERROR_INVALID_STATE If button or GPIOTE has not been initialized. + */ +uint32_t bsp_init(uint32_t type, bsp_event_callback_t callback); + + +/**@brief Function for checking button states. + * + * @details This function checks if the button is pressed. If the button ID is out of range, + * the function returns false. + * + * @param[in] button Button ID to check. + * + * @retval true If the button is pressed. + * @retval false If the button is not pressed. + */ +bool bsp_button_is_pressed(uint32_t button); + + +/**@brief Function for assigning a specific event to a button. + * + * @details This function allows redefinition of standard events assigned to buttons. + * To unassign events, provide the event @ref BSP_EVENT_NOTHING. + * + * @param[in] button Button ID to be redefined. + * @param[in] action Button action to assign event to. + * @param[in] event Event to be assigned to button. + * + * @retval NRF_SUCCESS If the event was successfully assigned to button. + * @retval NRF_ERROR_INVALID_PARAM If the button ID or button action was invalid. + */ +uint32_t bsp_event_to_button_action_assign(uint32_t button, bsp_button_action_t action, bsp_event_t event); + + +/**@brief Function for configuring indicators to required state. + * + * @details This function indicates the required state by means of LEDs (if enabled). + * + * @note Alerts are indicated independently. + * + * @param[in] indicate State to be indicated. + * + * @retval NRF_SUCCESS If the state was successfully indicated. + * @retval NRF_ERROR_NO_MEM If the internal timer operations queue was full. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized, + * or internal timer has not been created. + */ +uint32_t bsp_indication_set(bsp_indication_t indicate); + + +/**@brief Function for enabling all buttons. + * + * @details After calling this function, all buttons will generate events when pressed, and + * all buttons will be able to wake the system up from sleep mode. + * + * @retval NRF_SUCCESS If the buttons were successfully enabled. + * @retval NRF_ERROR_NOT_SUPPORTED If the board has no buttons or BSP_SIMPLE is defined. + * @return A propagated error. + */ +uint32_t bsp_buttons_enable(void); + + +/**@brief Function for disabling all buttons. + * + * @details After calling this function, no buttons will generate events when pressed, and + * no buttons will be able to wake the system up from sleep mode. + * + * @retval NRF_SUCCESS If the buttons were successfully disabled. + * @retval NRF_ERROR_NOT_SUPPORTED If the board has no buttons or BSP_SIMPLE is defined. + * @return A propagated error. + */ +uint32_t bsp_buttons_disable(void); + + +/**@brief Function for enabling wakeup from SYSTEM OFF for given button. + * + * @details After calling this function, button can be used to wake up the chip. + * This function should only be called immediately before going into sleep. + * + * @param[in] button_idx Index of the button. + * + * @retval NRF_SUCCESS If the button was successfully enabled. + * @retval NRF_ERROR_NOT_SUPPORTED If the board has no buttons or BSP_SIMPLE is defined. + */ +uint32_t bsp_wakeup_button_enable(uint32_t button_idx); + + +/**@brief Function for disabling wakeup for the given button. + * + * @param[in] button_idx index of the button. + * + * @retval NRF_SUCCESS If the button was successfully disabled. + * @retval NRF_ERROR_NOT_SUPPORTED If the board has no buttons or BSP_SIMPLE is defined. + */ +uint32_t bsp_wakeup_button_disable(uint32_t button_idx); + + +#ifdef __cplusplus +} +#endif + +#endif // BSP_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/bsp/bsp_config.h b/HAL_Driver/sdk/components/libraries/bsp/bsp_config.h new file mode 100644 index 0000000..999b218 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/bsp/bsp_config.h @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup bsp Board Support Package + * @{ + * @ingroup app_common + * + * @brief BSP module. + * @details This module provides a layer of abstraction from the board. + * It allows the user to indicate certain states on LEDs in a simple way. + * Module functionality can be modified by additional defines: + * - BSP_SIMPLE - reduces functionality of this module to enable + * and read state of the buttons. + * - BSP_UART_SUPPORT - enables support for UART. + */ + +#ifndef BSP_CONFIG_H__ +#define BSP_CONFIG_H__ + +#include +#include +#include "boards.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(BSP_DEFINES_ONLY) && !defined(BSP_SIMPLE) +#include "app_button.h" + +#define BSP_BUTTON_ACTION_PUSH (APP_BUTTON_PUSH) /**< Represents pushing a button. See @ref bsp_button_action_t. */ +#define BSP_BUTTON_ACTION_RELEASE (APP_BUTTON_RELEASE) /**< Represents releasing a button. See @ref bsp_button_action_t. */ +#define BSP_BUTTON_ACTION_LONG_PUSH (2) /**< Represents pushing and holding a button for @ref BSP_LONG_PUSH_TIMEOUT_MS milliseconds. See also @ref bsp_button_action_t. */ +#endif + +#define BSP_MS_TO_TICK(MS) (m_app_ticks_per_100ms * (MS / 100)) + + +#define BUTTON_ERASE_BONDING BSP_BUTTON_0_MASK +#define BUTTON_ERASE_ALL BSP_BUTTON_1_MASK +#define BUTTON_ADVERTISE BSP_BUTTON_0_MASK +#define BUTTON_CLEAR_EVT BSP_BUTTON_1_MASK +#define BUTTON_CAPSLOCK BSP_BUTTON_2_MASK +#define BSP_BUTTONS_ALL 0xFFFFFFFF +#define BSP_BUTTONS_NONE 0 + +#define BSP_LONG_PUSH_TIMEOUT_MS (1000) /**< The time to hold for a long push (in milliseconds). */ +/**@brief Types of BSP initialization. + */ + +#define ADVERTISING_LED_ON_INTERVAL 200 +#define ADVERTISING_LED_OFF_INTERVAL 1800 + +#define ADVERTISING_DIRECTED_LED_ON_INTERVAL 200 +#define ADVERTISING_DIRECTED_LED_OFF_INTERVAL 200 + +#define ADVERTISING_WHITELIST_LED_ON_INTERVAL 200 +#define ADVERTISING_WHITELIST_LED_OFF_INTERVAL 800 + +#define ADVERTISING_SLOW_LED_ON_INTERVAL 400 +#define ADVERTISING_SLOW_LED_OFF_INTERVAL 4000 + +#define BONDING_INTERVAL 100 + +#define SENT_OK_INTERVAL 100 +#define SEND_ERROR_INTERVAL 500 + +#define RCV_OK_INTERVAL 100 +#define RCV_ERROR_INTERVAL 500 + +#define ALERT_INTERVAL 200 + +#define BSP_LED_INDICATE_SENT_OK BSP_BOARD_LED_1 +#define BSP_LED_INDICATE_SEND_ERROR BSP_BOARD_LED_1 +#define BSP_LED_INDICATE_RCV_OK BSP_BOARD_LED_1 +#define BSP_LED_INDICATE_RCV_ERROR BSP_BOARD_LED_1 +#define BSP_LED_INDICATE_CONNECTED BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_BONDING BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_ADVERTISING_DIRECTED BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_ADVERTISING_SLOW BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_ADVERTISING_WHITELIST BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_INDICATE_ADVERTISING BSP_BOARD_LED_0 + +#define BSP_LED_INDICATE_USER_LED1 BSP_BOARD_LED_0 +#define BSP_LED_INDICATE_USER_LED2 BSP_BOARD_LED_1 +#define BSP_LED_INDICATE_USER_LED3 BSP_BOARD_LED_2 +#define BSP_LED_INDICATE_USER_LED4 BSP_BOARD_LED_3 + +#define BSP_LED_ALERT BSP_BOARD_LED_2 + +#ifdef __cplusplus +} +#endif + +#endif // BSP_CONFIG_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/button/app_button.c b/HAL_Driver/sdk/components/libraries/button/app_button.c new file mode 100644 index 0000000..4e82c41 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/button/app_button.c @@ -0,0 +1,223 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(BUTTON) +#include "app_button.h" +#include "app_timer.h" +#include "app_error.h" +#include "nrf_drv_gpiote.h" +#include "nrf_assert.h" + + +static app_button_cfg_t const * mp_buttons = NULL; /**< Button configuration. */ +static uint8_t m_button_count; /**< Number of configured buttons. */ +static uint32_t m_detection_delay; /**< Delay before a button is reported as pushed. */ +APP_TIMER_DEF(m_detection_delay_timer_id); /**< Polling timer id. */ + + +static uint64_t m_pin_state; +static uint64_t m_pin_transition; + +/**@brief Function for handling the timeout that delays reporting buttons as pushed. + * + * @details The detection_delay_timeout_handler(...) is a call-back issued from the app_timer + * module. It is called with the p_context parameter. The p_context parameter is + * provided to the app_timer module when a timer is started, using the call + * @ref app_timer_start. On @ref app_timer_start the p_context will be holding the + * currently pressed buttons. + * + * @param[in] p_context Pointer used for passing information app_start_timer() was called. + * In the app_button module the p_context holds information on pressed + * buttons. + */ +static void detection_delay_timeout_handler(void * p_context) +{ + uint8_t i; + + // Pushed button(s) detected, execute button handler(s). + for (i = 0; i < m_button_count; i++) + { + app_button_cfg_t const * p_btn = &mp_buttons[i]; + uint64_t btn_mask = 1ULL << p_btn->pin_no; + if (btn_mask & m_pin_transition) + { + m_pin_transition &= ~btn_mask; + bool pin_is_set = nrf_drv_gpiote_in_is_set(p_btn->pin_no); + if ((m_pin_state & (1ULL << p_btn->pin_no)) == (((uint64_t)pin_is_set) << p_btn->pin_no)) + { + uint64_t transition = !(pin_is_set ^ (p_btn->active_state == APP_BUTTON_ACTIVE_HIGH)); + + if (p_btn->button_handler) + { + p_btn->button_handler(p_btn->pin_no, transition); + } + } + } + } +} + +static void gpiote_event_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action) +{ + uint32_t err_code; + uint64_t pin_mask = 1ULL << pin; + + // Start detection timer. If timer is already running, the detection period is restarted. + // NOTE: Using the p_context parameter of app_timer_start() to transfer the pin states to the + // timeout handler (by casting event_pins_mask into the equally sized void * p_context + // parameter). + err_code = app_timer_stop(m_detection_delay_timer_id); + if (err_code != NRF_SUCCESS) + { + // The impact in app_button of the app_timer queue running full is losing a button press. + // The current implementation ensures that the system will continue working as normal. + return; + } + + if (!(m_pin_transition & pin_mask)) + { + if (nrf_drv_gpiote_in_is_set(pin)) + { + m_pin_state |= pin_mask; + } + else + { + m_pin_state &= ~(pin_mask); + } + m_pin_transition |= (pin_mask); + + err_code = app_timer_start(m_detection_delay_timer_id, m_detection_delay, NULL); + if (err_code != NRF_SUCCESS) + { + // The impact in app_button of the app_timer queue running full is losing a button press. + // The current implementation ensures that the system will continue working as normal. + } + } + else + { + m_pin_transition &= ~pin_mask; + } +} + +uint32_t app_button_init(app_button_cfg_t const * p_buttons, + uint8_t button_count, + uint32_t detection_delay) +{ + uint32_t err_code; + + if (detection_delay < APP_TIMER_MIN_TIMEOUT_TICKS) + { + return NRF_ERROR_INVALID_PARAM; + } + + if (!nrf_drv_gpiote_is_init()) + { + err_code = nrf_drv_gpiote_init(); + VERIFY_SUCCESS(err_code); + } + + // Save configuration. + mp_buttons = p_buttons; + m_button_count = button_count; + m_detection_delay = detection_delay; + + m_pin_state = 0; + m_pin_transition = 0; + + while (button_count--) + { + app_button_cfg_t const * p_btn = &p_buttons[button_count]; + +#if defined(BUTTON_HIGH_ACCURACY_ENABLED) && (BUTTON_HIGH_ACCURACY_ENABLED == 1) + nrf_drv_gpiote_in_config_t config = GPIOTE_CONFIG_IN_SENSE_TOGGLE(p_btn->hi_accuracy); +#else + nrf_drv_gpiote_in_config_t config = GPIOTE_CONFIG_IN_SENSE_TOGGLE(false); +#endif + config.pull = p_btn->pull_cfg; + + err_code = nrf_drv_gpiote_in_init(p_btn->pin_no, &config, gpiote_event_handler); + VERIFY_SUCCESS(err_code); + } + + // Create polling timer. + return app_timer_create(&m_detection_delay_timer_id, + APP_TIMER_MODE_SINGLE_SHOT, + detection_delay_timeout_handler); +} + +uint32_t app_button_enable(void) +{ + ASSERT(mp_buttons); + + uint32_t i; + for (i = 0; i < m_button_count; i++) + { + nrf_drv_gpiote_in_event_enable(mp_buttons[i].pin_no, true); + } + + return NRF_SUCCESS; +} + + +uint32_t app_button_disable(void) +{ + ASSERT(mp_buttons); + + uint32_t i; + for (i = 0; i < m_button_count; i++) + { + nrf_drv_gpiote_in_event_disable(mp_buttons[i].pin_no); + } + + // Make sure polling timer is not running. + return app_timer_stop(m_detection_delay_timer_id); +} + + +bool app_button_is_pushed(uint8_t button_id) +{ + ASSERT(button_id <= m_button_count); + ASSERT(mp_buttons != NULL); + + app_button_cfg_t const * p_btn = &mp_buttons[button_id]; + bool is_set = nrf_drv_gpiote_in_is_set(p_btn->pin_no); + + return !(is_set ^ (p_btn->active_state == APP_BUTTON_ACTIVE_HIGH)); +} +#endif //NRF_MODULE_ENABLED(BUTTON) diff --git a/HAL_Driver/sdk/components/libraries/button/app_button.h b/HAL_Driver/sdk/components/libraries/button/app_button.h new file mode 100644 index 0000000..2e4f529 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/button/app_button.h @@ -0,0 +1,142 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_button Button Handler + * @{ + * @ingroup app_common + * + * @brief Buttons handling module. + * + * @details The button handler uses the @ref app_gpiote to detect that a button has been + * pushed. To handle debouncing, it will start a timer in the GPIOTE event handler. + * The button will only be reported as pushed if the corresponding pin is still active when + * the timer expires. If there is a new GPIOTE event while the timer is running, the timer + * is restarted. + * + * @note The app_button module uses the app_timer module. The user must ensure that the queue in + * app_timer is large enough to hold the app_timer_stop() / app_timer_start() operations + * which will be executed on each event from GPIOTE module (2 operations), as well as other + * app_timer operations queued simultaneously in the application. + * + * @note Even if the scheduler is not used, app_button.h will include app_scheduler.h, so when + * compiling, app_scheduler.h must be available in one of the compiler include paths. + */ + +#ifndef APP_BUTTON_H__ +#define APP_BUTTON_H__ + +#include +#include +#include "nrf.h" +#include "app_error.h" +#include "nrf_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APP_BUTTON_PUSH 1 /**< Indicates that a button is pushed. */ +#define APP_BUTTON_RELEASE 0 /**< Indicates that a button is released. */ +#define APP_BUTTON_ACTIVE_HIGH 1 /**< Indicates that a button is active high. */ +#define APP_BUTTON_ACTIVE_LOW 0 /**< Indicates that a button is active low. */ + +/**@brief Button event handler type. */ +typedef void (*app_button_handler_t)(uint8_t pin_no, uint8_t button_action); + +/**@brief Button configuration structure. */ +typedef struct +{ + uint8_t pin_no; /**< Pin to be used as a button. */ + uint8_t active_state; /**< APP_BUTTON_ACTIVE_HIGH or APP_BUTTON_ACTIVE_LOW. */ +#if defined(BUTTON_HIGH_ACCURACY_ENABLED) && (BUTTON_HIGH_ACCURACY_ENABLED == 1) + bool hi_accuracy; /**< True if GPIOTE high accuracy (IN_EVENT) is used. */ +#endif + nrf_gpio_pin_pull_t pull_cfg; /**< Pull-up or -down configuration. */ + app_button_handler_t button_handler; /**< Handler to be called when button is pushed. */ +} app_button_cfg_t; + +/**@brief Function for initializing the Buttons. + * + * @details This function will initialize the specified pins as buttons, and configure the Button + * Handler module as a GPIOTE user (but it will not enable button detection). + * + * @note Normally initialization should be done using the APP_BUTTON_INIT() macro + * + * @note app_button_enable() function must be called in order to enable the button detection. + * + * @param[in] p_buttons Array of buttons to be used (NOTE: Must be static!). + * @param[in] button_count Number of buttons. + * @param[in] detection_delay Delay from a GPIOTE event until a button is reported as pushed. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +uint32_t app_button_init(app_button_cfg_t const * p_buttons, + uint8_t button_count, + uint32_t detection_delay); + +/**@brief Function for enabling button detection. + * + * @retval NRF_SUCCESS Module successfully enabled. + */ +uint32_t app_button_enable(void); + +/**@brief Function for disabling button detection. + * + * @retval NRF_SUCCESS Button detection successfully disabled. Error code otherwise. + */ +uint32_t app_button_disable(void); + +/**@brief Function for checking if a button is currently being pushed. + * + * @param[in] button_id Button index (in the app_button_cfg_t array given to app_button_init) to be checked. + * + * @return Button state. + */ +bool app_button_is_pushed(uint8_t button_id); + + +#ifdef __cplusplus +} +#endif + +#endif // APP_BUTTON_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/delay/nrf_delay.h b/HAL_Driver/sdk/components/libraries/delay/nrf_delay.h new file mode 100644 index 0000000..e6ca841 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/delay/nrf_delay.h @@ -0,0 +1,80 @@ +/** + * Copyright (c) 2011 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _NRF_DELAY_H +#define _NRF_DELAY_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Function for delaying execution for a number of microseconds. + * + * @param us_time Number of microseconds to wait. + */ +#define nrf_delay_us(us_time) NRFX_DELAY_US(us_time) + + +/** + * @brief Function for delaying execution for a number of milliseconds. + * + * @param ms_time Number of milliseconds to wait. + */ + +__STATIC_INLINE void nrf_delay_ms(uint32_t ms_time) +{ + if (ms_time == 0) + { + return; + } + + do { + nrf_delay_us(1000); + } while (--ms_time); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/HAL_Driver/sdk/components/libraries/experimental_section_vars/nrf_section.h b/HAL_Driver/sdk/components/libraries/experimental_section_vars/nrf_section.h new file mode 100644 index 0000000..69546cb --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/experimental_section_vars/nrf_section.h @@ -0,0 +1,191 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_SECTION_H__ +#define NRF_SECTION_H__ + +#include "nordic_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup section_vars Section variables + * @ingroup app_common + * @{ + * + * @brief Section variables. + */ + +//lint -save -e27 -esym(526,*) + +#if defined(__ICCARM__) +// Enable IAR language extensions +#pragma language=extended +#endif + +/**@brief Macro for obtaining the address of the beginning of a section. + * + * param[in] section_name Name of the section. + * @hideinitializer + */ +#if defined(__CC_ARM) +#define NRF_SECTION_START_ADDR(section_name) &CONCAT_2(section_name, $$Base) + +#elif defined(__GNUC__) +#define NRF_SECTION_START_ADDR(section_name) &CONCAT_2(__start_, section_name) + +#elif defined(__ICCARM__) +#define NRF_SECTION_START_ADDR(section_name) __section_begin(STRINGIFY(section_name)) +#endif + + +/**@brief Macro for obtaining the address of the end of a section. + * + * @param[in] section_name Name of the section. + * @hideinitializer + */ +#if defined(__CC_ARM) +#define NRF_SECTION_END_ADDR(section_name) &CONCAT_2(section_name, $$Limit) + +#elif defined(__GNUC__) +#define NRF_SECTION_END_ADDR(section_name) &CONCAT_2(__stop_, section_name) + +#elif defined(__ICCARM__) +#define NRF_SECTION_END_ADDR(section_name) __section_end(STRINGIFY(section_name)) +#endif + + +/**@brief Macro for retrieving the length of a given section, in bytes. + * + * @param[in] section_name Name of the section. + * @hideinitializer + */ +#define NRF_SECTION_LENGTH(section_name) \ + ((size_t)NRF_SECTION_END_ADDR(section_name) - \ + (size_t)NRF_SECTION_START_ADDR(section_name)) + + +/**@brief Macro for creating a section. + * + * @param[in] section_name Name of the section. + * @param[in] data_type Data type of the variables to be registered in the section. + * + * @warning Data type must be word aligned to prevent padding. + * @hideinitializer + */ +#if defined(__CC_ARM) +#define NRF_SECTION_DEF(section_name, data_type) \ + extern data_type * CONCAT_2(section_name, $$Base); \ + extern void * CONCAT_2(section_name, $$Limit) + +#elif defined(__GNUC__) +#define NRF_SECTION_DEF(section_name, data_type) \ + extern data_type * CONCAT_2(__start_, section_name); \ + extern void * CONCAT_2(__stop_, section_name) + +#elif defined(__ICCARM__) +#define NRF_SECTION_DEF(section_name, data_type) \ + _Pragma(STRINGIFY(section = STRINGIFY(section_name))); + +#endif + + +/**@brief Macro for declaring a variable and registering it in a section. + * + * @details Declares a variable and registers it in a named section. This macro ensures that the + * variable is not stripped away when using optimizations. + * + * @note The order in which variables are placed in a section is dependent on the order in + * which the linker script encounters the variables during linking. + * + * @param[in] section_name Name of the section. + * @param[in] section_var Variable to register in the given section. + * @hideinitializer + */ +#if defined(__CC_ARM) +#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ + section_var __attribute__ ((section(STRINGIFY(section_name)))) __attribute__((used)) + +#elif defined(__GNUC__) +#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ + section_var __attribute__ ((section("." STRINGIFY(section_name)))) __attribute__((used)) + +#elif defined(__ICCARM__) +#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \ + __root section_var @ STRINGIFY(section_name) +#endif + + +/**@brief Macro for retrieving a variable from a section. + * + * @warning The stored symbol can only be resolved using this macro if the + * type of the data is word aligned. The operation of acquiring + * the stored symbol relies on the size of the stored type. No + * padding can exist in the named section in between individual + * stored items or this macro will fail. + * + * @param[in] section_name Name of the section. + * @param[in] data_type Data type of the variable. + * @param[in] i Index of the variable in section. + * @hideinitializer + */ +#define NRF_SECTION_ITEM_GET(section_name, data_type, i) \ + ((data_type*)NRF_SECTION_START_ADDR(section_name) + (i)) + + +/**@brief Macro for getting the number of variables in a section. + * + * @param[in] section_name Name of the section. + * @param[in] data_type Data type of the variables in the section. + * @hideinitializer + */ +#define NRF_SECTION_ITEM_COUNT(section_name, data_type) \ + NRF_SECTION_LENGTH(section_name) / sizeof(data_type) + +/** @} */ + +//lint -restore + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SECTION_H__ diff --git a/HAL_Driver/sdk/components/libraries/fifo/app_fifo.c b/HAL_Driver/sdk/components/libraries/fifo/app_fifo.c new file mode 100644 index 0000000..d4602fa --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/fifo/app_fifo.c @@ -0,0 +1,214 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(APP_FIFO) +#include "app_fifo.h" + +static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo) +{ + uint32_t tmp = p_fifo->read_pos; + return p_fifo->write_pos - tmp; +} + + +#define FIFO_LENGTH() fifo_length(p_fifo) /**< Macro for calculating the FIFO length. */ + + +/**@brief Put one byte to the FIFO. */ +static __INLINE void fifo_put(app_fifo_t * p_fifo, uint8_t byte) +{ + p_fifo->p_buf[p_fifo->write_pos & p_fifo->buf_size_mask] = byte; + p_fifo->write_pos++; +} + + +/**@brief Look at one byte in the FIFO. */ +static __INLINE void fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) +{ + *p_byte = p_fifo->p_buf[(p_fifo->read_pos + index) & p_fifo->buf_size_mask]; +} + + +/**@brief Get one byte from the FIFO. */ +static __INLINE void fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) +{ + fifo_peek(p_fifo, 0, p_byte); + p_fifo->read_pos++; +} + + +uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size) +{ + // Check buffer for null pointer. + if (p_buf == NULL) + { + return NRF_ERROR_NULL; + } + + // Check that the buffer size is a power of two. + if (!IS_POWER_OF_TWO(buf_size)) + { + return NRF_ERROR_INVALID_LENGTH; + } + + p_fifo->p_buf = p_buf; + p_fifo->buf_size_mask = buf_size - 1; + p_fifo->read_pos = 0; + p_fifo->write_pos = 0; + + return NRF_SUCCESS; +} + + +uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte) +{ + if (FIFO_LENGTH() <= p_fifo->buf_size_mask) + { + fifo_put(p_fifo, byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NO_MEM; +} + + +uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte) +{ + if (FIFO_LENGTH() != 0) + { + fifo_get(p_fifo, p_byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NOT_FOUND; + +} + + +uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte) +{ + if (FIFO_LENGTH() > index) + { + fifo_peek(p_fifo, index, p_byte); + return NRF_SUCCESS; + } + + return NRF_ERROR_NOT_FOUND; +} + + +uint32_t app_fifo_flush(app_fifo_t * p_fifo) +{ + p_fifo->read_pos = p_fifo->write_pos; + return NRF_SUCCESS; +} + + +uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size) +{ + VERIFY_PARAM_NOT_NULL(p_fifo); + VERIFY_PARAM_NOT_NULL(p_size); + + const uint32_t byte_count = fifo_length(p_fifo); + const uint32_t requested_len = (*p_size); + uint32_t index = 0; + uint32_t read_size = MIN(requested_len, byte_count); + + (*p_size) = byte_count; + + // Check if the FIFO is empty. + if (byte_count == 0) + { + return NRF_ERROR_NOT_FOUND; + } + + // Check if application has requested only the size. + if (p_byte_array == NULL) + { + return NRF_SUCCESS; + } + + // Fetch bytes from the FIFO. + while (index < read_size) + { + fifo_get(p_fifo, &p_byte_array[index++]); + } + + (*p_size) = read_size; + + return NRF_SUCCESS; +} + + +uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size) +{ + VERIFY_PARAM_NOT_NULL(p_fifo); + VERIFY_PARAM_NOT_NULL(p_size); + + const uint32_t available_count = p_fifo->buf_size_mask - fifo_length(p_fifo) + 1; + const uint32_t requested_len = (*p_size); + uint32_t index = 0; + uint32_t write_size = MIN(requested_len, available_count); + + (*p_size) = available_count; + + // Check if the FIFO is FULL. + if (available_count == 0) + { + return NRF_ERROR_NO_MEM; + } + + // Check if application has requested only the size. + if (p_byte_array == NULL) + { + return NRF_SUCCESS; + } + + //Fetch bytes from the FIFO. + while (index < write_size) + { + fifo_put(p_fifo, p_byte_array[index++]); + } + + (*p_size) = write_size; + + return NRF_SUCCESS; +} +#endif //NRF_MODULE_ENABLED(APP_FIFO) diff --git a/HAL_Driver/sdk/components/libraries/fifo/app_fifo.h b/HAL_Driver/sdk/components/libraries/fifo/app_fifo.h new file mode 100644 index 0000000..4fad6ef --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/fifo/app_fifo.h @@ -0,0 +1,181 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup app_fifo FIFO implementation + * @{ + * @ingroup app_common + * + * @brief FIFO implementation. + */ + +#ifndef APP_FIFO_H__ +#define APP_FIFO_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/**@brief A FIFO instance structure. + * @details Keeps track of which bytes to read and write next. + * Also, it keeps the information about which memory is allocated for the buffer + * and its size. This structure must be initialized by app_fifo_init() before use. + */ +typedef struct +{ + uint8_t * p_buf; /**< Pointer to FIFO buffer memory. */ + uint16_t buf_size_mask; /**< Read/write index mask. Also used for size checking. */ + volatile uint32_t read_pos; /**< Next read position in the FIFO buffer. */ + volatile uint32_t write_pos; /**< Next write position in the FIFO buffer. */ +} app_fifo_t; + +/**@brief Function for initializing the FIFO. + * + * @param[out] p_fifo FIFO object. + * @param[in] p_buf FIFO buffer for storing data. The buffer size must be a power of two. + * @param[in] buf_size Size of the FIFO buffer provided. This size must be a power of two. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_NULL If a NULL pointer is provided as buffer. + * @retval NRF_ERROR_INVALID_LENGTH If size of buffer provided is not a power of two. + */ +uint32_t app_fifo_init(app_fifo_t * p_fifo, uint8_t * p_buf, uint16_t buf_size); + +/**@brief Function for adding an element to the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[in] byte Data byte to add to the FIFO. + * + * @retval NRF_SUCCESS If an element has been successfully added to the FIFO. + * @retval NRF_ERROR_NO_MEM If the FIFO is full. + */ +uint32_t app_fifo_put(app_fifo_t * p_fifo, uint8_t byte); + +/**@brief Function for getting the next element from the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[out] p_byte Byte fetched from the FIFO. + * + * @retval NRF_SUCCESS If an element was returned. + * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue. + */ +uint32_t app_fifo_get(app_fifo_t * p_fifo, uint8_t * p_byte); + +/**@brief Function for looking at an element in the FIFO, without consuming it. + * + * @param[in] p_fifo Pointer to the FIFO. + * @param[in] index Which element to look at. The lower the index, the earlier it was put. + * @param[out] p_byte Byte fetched from the FIFO. + * + * @retval NRF_SUCCESS If an element was returned. + * @retval NRF_ERROR_NOT_FOUND If there are no more elements in the queue, or the index was + * too large. + */ +uint32_t app_fifo_peek(app_fifo_t * p_fifo, uint16_t index, uint8_t * p_byte); + +/**@brief Function for flushing the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. + * + * @retval NRF_SUCCESS If the FIFO was flushed successfully. + */ +uint32_t app_fifo_flush(app_fifo_t * p_fifo); + +/**@brief Function for reading bytes from the FIFO. + * + * This function can also be used to get the number of bytes in the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. + * @param[out] p_byte_array Memory pointer where the read bytes are fetched from the FIFO. + * Can be NULL. If NULL, the number of bytes that can be read in the FIFO + * are returned in the p_size parameter. + * @param[inout] p_size Address to memory indicating the maximum number of bytes to be read. + * The provided memory is overwritten with the actual number of bytes + * read if the procedure was successful. This field must not be NULL. + * If p_byte_array is set to NULL by the application, this parameter + * returns the number of bytes in the FIFO. + * + * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes read might + * be less than the requested maximum, depending on how many elements exist + * in the FIFO. Even if less bytes are returned, the procedure is considered + * successful. + * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not + * be NULL. + * @retval NRF_ERROR_NOT_FOUND If the FIFO is empty. + */ +uint32_t app_fifo_read(app_fifo_t * p_fifo, uint8_t * p_byte_array, uint32_t * p_size); + +/**@brief Function for writing bytes to the FIFO. + * + * This function can also be used to get the available size on the FIFO. + * + * @param[in] p_fifo Pointer to the FIFO. Must not be NULL. + * @param[in] p_byte_array Memory pointer containing the bytes to be written to the FIFO. + * Can be NULL. If NULL, this function returns the number of bytes + * that can be written to the FIFO. + * @param[inout] p_size Address to memory indicating the maximum number of bytes to be written. + * The provided memory is overwritten with the number of bytes that were actually + * written if the procedure is successful. This field must not be NULL. + * If p_byte_array is set to NULL by the application, this parameter + * returns the number of bytes available in the FIFO. + * + * @retval NRF_SUCCESS If the procedure is successful. The actual number of bytes written might + * be less than the requested maximum, depending on how much room there is in + * the FIFO. Even if less bytes are written, the procedure is considered + * successful. If the write was partial, the application should use + * subsequent calls to attempt writing the data again. + * @retval NRF_ERROR_NULL If a NULL parameter was passed for a parameter that must not + * be NULL. + * @retval NRF_ERROR_NO_MEM If the FIFO is full. + * + */ +uint32_t app_fifo_write(app_fifo_t * p_fifo, uint8_t const * p_byte_array, uint32_t * p_size); + + +#ifdef __cplusplus +} +#endif + +#endif // APP_FIFO_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log.h b/HAL_Driver/sdk/components/libraries/log/nrf_log.h new file mode 100644 index 0000000..b0d1d5a --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log.h @@ -0,0 +1,296 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup nrf_log Logger module + * @{ + * @ingroup app_common + * + * @brief The nrf_log module interface. + */ + +#ifndef NRF_LOG_H_ +#define NRF_LOG_H_ + +#include "sdk_common.h" +#include "nrf_section.h" +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "nrf_strerror.h" +#define NRF_LOG_ERROR_STRING_GET(code) nrf_strerror_get(code) +#else +#define NRF_LOG_ERROR_STRING_GET(code) "" +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Severity level for the module. + * + * The severity level can be defined in a module to override the default. + */ +#ifndef NRF_LOG_LEVEL + #define NRF_LOG_LEVEL NRF_LOG_DEFAULT_LEVEL +#endif + +/** @brief Initial severity if filtering is enabled. + */ +#ifndef NRF_LOG_INITIAL_LEVEL + #define NRF_LOG_INITIAL_LEVEL NRF_LOG_LEVEL +#endif + + +#include "nrf_log_internal.h" + +/** @def NRF_LOG_ERROR + * @brief Macro for logging error messages. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + */ + +/** @def NRF_LOG_WARNING + * @brief Macro for logging error messages. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs. + */ + +/** @def NRF_LOG_INFO + * @brief Macro for logging error messages. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs. + */ + +/** @def NRF_LOG_DEBUG + * @brief Macro for logging error messages. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs. + */ + +#define NRF_LOG_ERROR(...) NRF_LOG_INTERNAL_ERROR(__VA_ARGS__) +#define NRF_LOG_WARNING(...) NRF_LOG_INTERNAL_WARNING( __VA_ARGS__) +#define NRF_LOG_INFO(...) NRF_LOG_INTERNAL_INFO( __VA_ARGS__) +#define NRF_LOG_DEBUG(...) NRF_LOG_INTERNAL_DEBUG( __VA_ARGS__) + +/** @def NRF_LOG_INST_ERROR + * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @param p_inst Pointer to the instance with logging support. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + */ + +/** @def NRF_LOG_INST_WARNING + * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @param p_inst Pointer to the instance with logging support. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + */ + +/** @def NRF_LOG_INST_INFO + * @brief Macro for logging error messages for a given module instance. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @param p_inst Pointer to the instance with logging support. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + */ + +/** @def NRF_LOG_INST_DEBUG + * @brief Macro for logging error messages for given module instance. It takes a printf-like, formatted + * string with up to seven arguments. + * + * @param p_inst Pointer to the instance with logging support. + * + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + */ +#define NRF_LOG_INST_ERROR(p_inst,...) NRF_LOG_INTERNAL_INST_ERROR(p_inst,__VA_ARGS__) +#define NRF_LOG_INST_WARNING(p_inst,...) NRF_LOG_INTERNAL_INST_WARNING(p_inst,__VA_ARGS__) +#define NRF_LOG_INST_INFO(p_inst,...) NRF_LOG_INTERNAL_INST_INFO(p_inst, __VA_ARGS__) +#define NRF_LOG_INST_DEBUG(p_inst,...) NRF_LOG_INTERNAL_INST_DEBUG(p_inst, __VA_ARGS__) + +/** + * @brief Macro for logging a formatted string without any prefix or timestamp. + */ +#define NRF_LOG_RAW_INFO(...) NRF_LOG_INTERNAL_RAW_INFO( __VA_ARGS__) + +/** @def NRF_LOG_HEXDUMP_ERROR + * @brief Macro for logging raw bytes. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + * + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_WARNING + * @brief Macro for logging raw bytes. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs. + * + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_INFO + * @brief Macro for logging raw bytes. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs. + * + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_DEBUG + * @brief Macro for logging raw bytes. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs. + * + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +#define NRF_LOG_HEXDUMP_ERROR(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len) +#define NRF_LOG_HEXDUMP_WARNING(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len) +#define NRF_LOG_HEXDUMP_INFO(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len) +#define NRF_LOG_HEXDUMP_DEBUG(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len) + +/** @def NRF_LOG_HEXDUMP_INST_ERROR + * @brief Macro for logging raw bytes for a specific module instance. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + * + * @param p_inst Pointer to the instance with logging support. + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_INST_WARNING + * @brief Macro for logging raw bytes for a specific module instance. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + * + * @param p_inst Pointer to the instance with logging support. + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_INST_INFO + * @brief Macro for logging raw bytes for a specific module instance. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + * + * @param p_inst Pointer to the instance with logging support. + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +/** @def NRF_LOG_HEXDUMP_INST_DEBUG + * @brief Macro for logging raw bytes for a specific module instance. + * @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs. + * + * @param p_inst Pointer to the instance with logging support. + * @param p_data Pointer to data. + * @param len Data length in bytes. + */ +#define NRF_LOG_HEXDUMP_INST_ERROR(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_ERROR(p_inst, p_data, len) +#define NRF_LOG_HEXDUMP_INST_WARNING(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_WARNING(p_inst, p_data, len) +#define NRF_LOG_HEXDUMP_INST_INFO(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_INFO(p_inst, p_data, len) +#define NRF_LOG_HEXDUMP_INST_DEBUG(p_inst, p_data, len) NRF_LOG_INTERNAL_HEXDUMP_INST_DEBUG(p_inst, p_data, len) + +/** + * @brief Macro for logging hexdump without any prefix or timestamp. + */ +#define NRF_LOG_RAW_HEXDUMP_INFO(p_data, len) NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len) + + +/** + * @brief Macro for copying a string to internal logger buffer if logs are deferred. + * + * @param _str String. + */ +#define NRF_LOG_PUSH(_str) NRF_LOG_INTERNAL_LOG_PUSH(_str) + +/** + * @brief Function for copying a string to the internal logger buffer if logs are deferred. + * + * Use this function to store a string that is volatile (for example allocated + * on stack) or that may change before the deferred logs are processed. Such string is copied + * into the internal logger buffer (see @ref NRF_LOG_STR_PUSH_BUFFER_SIZE). + * + * @note String storing is not reliable. It means that string is copied to the buffer but there is + * no indication when it was used and could be freed. String may be overwritten by another + * @ref nrf_log_push call before being processed. For reliable data dumping use + * hexdump macros (e.g. @ref NRF_LOG_HEXDUMP_INFO). + * + * @note If the logs are not deferred, then this function returns the input parameter. + * + * @param p_str Pointer to the user string. + * + * @return Address to the location where the string is stored in the internal logger buffer. + */ +char const * nrf_log_push(char * const p_str); + +/** + * @brief Macro to be used in a formatted string to a pass float number to the log. + * + * Use this macro in a formatted string instead of the %f specifier together with + * @ref NRF_LOG_FLOAT macro. + * Example: NRF_LOG_INFO("My float number" NRF_LOG_FLOAT_MARKER "\r\n", NRF_LOG_FLOAT(f))) + */ +#define NRF_LOG_FLOAT_MARKER "%s%d.%02d" + +/** + * @brief Macro for dissecting a float number into two numbers (integer and residuum). + */ +#define NRF_LOG_FLOAT(val) (uint32_t)(((val) < 0 && (val) > -1.0) ? "-" : ""), \ + (int32_t)(val), \ + (int32_t)((((val) > 0) ? (val) - (int32_t)(val) \ + : (int32_t)(val) - (val))*100) + + +/** + * @brief Macro for registering an independent module. + * + * Registration creates set of dynamic (RAM) and constant variables associated with the module. + */ +#define NRF_LOG_MODULE_REGISTER() NRF_LOG_INTERNAL_MODULE_REGISTER() + + +#ifdef __cplusplus +} +#endif + +#endif // NRF_LOG_H_ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_interface.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_interface.h new file mode 100644 index 0000000..10c0da9 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_interface.h @@ -0,0 +1,271 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_BACKEND_INTERFACE_H +#define NRF_LOG_BACKEND_INTERFACE_H + +/**@file + * @addtogroup nrf_log Logger module + * @ingroup app_common + * + * @defgroup nrf_log_backend_interface Logger backend interface + * @{ + * @ingroup nrf_log + * @brief The nrf_log backend interface. + */ + +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "nrf_memobj.h" +#endif + +#include "nrf_section.h" +#include "nordic_common.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief nrf_log entry. + */ +#if NRF_LOG_ENABLED +typedef nrf_memobj_t nrf_log_entry_t; +#else +typedef void nrf_log_entry_t; +#endif + +/* Forward declaration of the nrf_log_backend_t type. */ +typedef struct nrf_log_backend_s nrf_log_backend_t; + +/** + * @brief Logger backend API. + */ +typedef struct +{ + /** + * @brief @ref nrf_log_backend_put + */ + void (*put)(nrf_log_backend_t const * p_backend, nrf_log_entry_t * p_entry); + + /** + * @brief @ref nrf_log_backend_panic_set + */ + void (*panic_set)(nrf_log_backend_t const * p_backend); + + /** + * @brief @ref nrf_log_backend_flush + */ + void (*flush)(nrf_log_backend_t const * p_backend); +} nrf_log_backend_api_t; + +/** + * @brief Logger backend control block. + */ +typedef struct +{ + nrf_log_backend_t const * p_next; //!< Pointer to the next backend in the logger. + uint8_t id; //!< ID of the backend. + bool enabled; //!< Enable flag. +} nrf_log_backend_cb_t; + +/** + * @brief Logger backend structure. + */ +struct nrf_log_backend_s +{ + nrf_log_backend_api_t const * p_api; //!< Pointer to interface. + void * p_ctx; //!< User context. + char * p_name; //!< Name of the backend. + nrf_log_backend_cb_t * p_cb; //!< Pointer to the backend control block. +}; + + +#define NRF_LOG_BACKEND_SECTION_NAME log_backends + +#define NRF_LOG_BACKEND_SUBSECTION_NAME(_name) NRF_LOG_BACKEND_SECTION_NAME + +/** @brief Invalid ID value indicating that logger backend is not attached to the logger frontend.*/ +#define NRF_LOG_BACKEND_INVALID_ID 0xFF + +/** @brief Memory section where backends are located. */ +NRF_SECTION_DEF(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t); + +/** + * @brief Macro for creating a logger backend instance. + * + * @param _name Name of the backend instance. + * @param _api Logger backend API. + * @param _p_ctx Pointer to the user context. + */ +#define NRF_LOG_BACKEND_DEF(_name, _api, _p_ctx) \ + static nrf_log_backend_cb_t CONCAT_2(log_backend_cb_, _name) = { \ + .enabled = false, \ + .id = NRF_LOG_BACKEND_INVALID_ID, \ + .p_next = NULL \ + }; \ + NRF_SECTION_ITEM_REGISTER(NRF_LOG_BACKEND_SUBSECTION_NAME(_name), \ + static const nrf_log_backend_t _name) = { \ + .p_api = &_api, \ + .p_ctx = _p_ctx, \ + .p_cb = &CONCAT_2(log_backend_cb_, _name), \ + .p_name = (char *)STRINGIFY(_name) \ + } + + +/** + * @brief Function for putting message with log entry to the backend. + * + * @param[in] p_backend Pointer to the backend instance. + * @param[in] p_msg Pointer to message with log entry. + */ +__STATIC_INLINE void nrf_log_backend_put(nrf_log_backend_t const * const p_backend, + nrf_log_entry_t * p_msg); + +/** + * @brief Function for reconfiguring backend to panic mode. + * + * @param[in] p_backend Pointer to the backend instance. + */ +__STATIC_INLINE void nrf_log_backend_panic_set(nrf_log_backend_t const * const p_backend); + +/** + * @brief Function for flushing backend. + * + * On flushing request backend should release log message(s). + * + * @param[in] p_backend Pointer to the backend instance. + */ +__STATIC_INLINE void nrf_log_backend_flush(nrf_log_backend_t const * const p_backend); + + +/** + * @brief Function for setting backend id. + * + * @note It is used internally by the logger. + * + * @param[in] p_backend Pointer to the backend instance. + * @param[in] id Id. + */ +__STATIC_INLINE void nrf_log_backend_id_set(nrf_log_backend_t const * const p_backend, uint8_t id); + +/** + * @brief Function for getting backend id. + * + * @note It is used internally by the logger. + * + * @param[in] p_backend Pointer to the backend instance. + * @return Id. + */ +__STATIC_INLINE uint8_t nrf_log_backend_id_get(nrf_log_backend_t const * const p_backend); + +/** + * @brief Function for enabling backend. + * + * @param[in] p_backend Pointer to the backend instance. + */ +__STATIC_INLINE void nrf_log_backend_enable(nrf_log_backend_t const * const p_backend); + +/** + * @brief Function for disabling backend. + * + * @param[in] p_backend Pointer to the backend instance. + */ +__STATIC_INLINE void nrf_log_backend_disable(nrf_log_backend_t const * const p_backend); + +/** + * @brief Function for checking state of the backend. + * + * @param[in] p_backend Pointer to the backend instance. + * + * @return True if backend is enabled, false otherwise. + */ +__STATIC_INLINE bool nrf_log_backend_is_enabled(nrf_log_backend_t const * const p_backend); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_log_backend_put(nrf_log_backend_t const * const p_backend, + nrf_log_entry_t * p_msg) +{ + p_backend->p_api->put(p_backend, p_msg); +} + +__STATIC_INLINE void nrf_log_backend_panic_set(nrf_log_backend_t const * const p_backend) +{ + p_backend->p_api->panic_set(p_backend); +} + +__STATIC_INLINE void nrf_log_backend_flush(nrf_log_backend_t const * const p_backend) +{ + p_backend->p_api->flush(p_backend); +} + +__STATIC_INLINE void nrf_log_backend_id_set(nrf_log_backend_t const * const p_backend, uint8_t id) +{ + p_backend->p_cb->id = id; +} + +__STATIC_INLINE uint8_t nrf_log_backend_id_get(nrf_log_backend_t const * const p_backend) +{ + return p_backend->p_cb->id; +} + +__STATIC_INLINE void nrf_log_backend_enable(nrf_log_backend_t const * const p_backend) +{ + p_backend->p_cb->enabled = true; +} + +__STATIC_INLINE void nrf_log_backend_disable(nrf_log_backend_t const * const p_backend) +{ + p_backend->p_cb->enabled = false; +} + +__STATIC_INLINE bool nrf_log_backend_is_enabled(nrf_log_backend_t const * const p_backend) +{ + return p_backend->p_cb->enabled; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#ifdef __cplusplus +} +#endif + +#endif //NRF_LOG_BACKEND_INTERFACE_H + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_rtt.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_rtt.h new file mode 100644 index 0000000..726bafa --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_backend_rtt.h @@ -0,0 +1,80 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + /**@file + * + * @defgroup nrf_log_backend_rtt Log RTT backend + * @{ + * @ingroup nrf_log + * @brief Log RTT backend. + */ + +#ifndef NRF_LOG_BACKEND_RTT_H +#define NRF_LOG_BACKEND_RTT_H + +#include "nrf_log_backend_interface.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern const nrf_log_backend_api_t nrf_log_backend_rtt_api; + +typedef struct { + nrf_log_backend_t backend; +} nrf_log_backend_rtt_t; + +/** + * @brief RTT backend definition + * + * @param _name Name of the instance. + */ +#define NRF_LOG_BACKEND_RTT_DEF(_name) \ + NRF_LOG_BACKEND_DEF(_name, nrf_log_backend_rtt_api, NULL) + +void nrf_log_backend_rtt_init(void); + +#ifdef __cplusplus +} +#endif + +#endif //NRF_LOG_BACKEND_RTT_H + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_ctrl.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_ctrl.h new file mode 100644 index 0000000..6f14cf9 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_ctrl.h @@ -0,0 +1,243 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_CTRL_H +#define NRF_LOG_CTRL_H + +/**@file + * @addtogroup nrf_log Logger module + * @ingroup app_common + * + * @defgroup nrf_log_ctrl Functions for controlling nrf_log + * @{ + * @ingroup nrf_log + * @brief The nrf_log control interface. + */ + +#include "sdk_config.h" +#include "sdk_errors.h" +#include +#include +#include "nrf_log_types.h" +#include "nrf_log_ctrl_internal.h" +#include "nrf_log_backend_interface.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Timestamp function prototype. + * + * @return Timestamp value. + */ +typedef uint32_t (*nrf_log_timestamp_func_t)(void); + + +/**@brief Macro for initializing the logs. + * + * Macro has one or two parameters. First parameter (obligatory) is the timestamp function (@ref nrf_log_timestamp_func_t). + * Additionally, as the second parameter timestamp frequency in Hz can be provided. If not provided then default + * frequency is used (@ref NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY). Frequency is used to format timestamp prefix if + * @ref NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED is set. + * + * @return NRF_SUCCESS after successful initialization, otherwise an error code. + */ +#define NRF_LOG_INIT(...) NRF_LOG_INTERNAL_INIT(__VA_ARGS__) + + +/**@brief Macro for processing a single log entry from a queue of deferred logs. + * + * You can call this macro from the main context or from the error handler to process + * log entries one by one. + * + * @note If logs are not deferred, this call has no use and is defined as 'false'. + * + * @retval true There are more logs to process in the buffer. + * @retval false No more logs in the buffer. + */ +#define NRF_LOG_PROCESS() NRF_LOG_INTERNAL_PROCESS() + +/** @brief Macro for processing all log entries from the buffer. + * It blocks until all buffered entries are processed by the backend. + * + * @note If logs are not deferred, this call has no use and is empty. + */ +#define NRF_LOG_FLUSH() NRF_LOG_INTERNAL_FLUSH() + +/** @brief Macro for flushing log data before reset. + * + * @note If logs are not deferred, this call has no use and is empty. + * + * @note If RTT is used, then a breakpoint is hit once flushed. + */ +#define NRF_LOG_FINAL_FLUSH() NRF_LOG_INTERNAL_FINAL_FLUSH() + +/** + * @brief Function for initializing the frontend and the default backend. + * + * @ref NRF_LOG_INIT calls this function to initialize the frontend and the backend. + * If custom backend is used, then @ref NRF_LOG_INIT should not be called. + * Instead, frontend and user backend should be verbosely initialized. + * + * @param timestamp_func Function for getting a 32-bit timestamp. + * @param timestamp_freq Frequency of the timestamp. + * + * @return Error status. + * + */ +ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func, uint32_t timestamp_freq); + +/** + * @brief Function for adding new backend interface to the logger. + * + * @param p_backend Pointer to the backend interface. + * @param severity Initial value of severity level for each module forwarded to the backend. This + * option is only applicable if @ref NRF_LOG_FILTERS_ENABLED is set. + * @return -1 if backend cannot be added or positive number (backend ID). + */ +int32_t nrf_log_backend_add(nrf_log_backend_t const * p_backend, nrf_log_severity_t severity); + +/** + * @brief Function for removing backend from the logger. + * + * @param p_backend Pointer to the backend interface. + * + */ +void nrf_log_backend_remove(nrf_log_backend_t const * p_backend); + +/** + * @brief Function for setting logger backends into panic mode. + * + * When this function is called all attached backends are informed about panic state of the system. + * It is up to the backend to react properly (hold or process logs in blocking mode, etc.) + */ +void nrf_log_panic(void); + +/** + * @brief Function for handling a single log entry. + * + * Use this function only if the logs are buffered. It takes a single entry from the + * buffer and attempts to process it. + * + * @retval true If there are more entries to process. + * @retval false If there are no more entries to process. + */ +bool nrf_log_frontend_dequeue(void); + +/** + * @brief Function for getting number of independent log modules registered into the logger. + * + * @return Number of registered modules. + */ +uint32_t nrf_log_module_cnt_get(void); + +/** + * @brief Function for getting module name. + * + * @param module_id Module ID. + * @param is_ordered_idx Module ID is given is index in alphabetically sorted list of modules. + * @return Pointer to string with module name. + */ +const char * nrf_log_module_name_get(uint32_t module_id, bool is_ordered_idx); + +/** + * @brief Function for getting coloring of specific logs. + * + * @param module_id Module ID. + * @param severity Log severity. + * + * @return ID of the color. + */ +uint8_t nrf_log_color_id_get(uint32_t module_id, nrf_log_severity_t severity); + +/** + * @brief Function for configuring filtering ofs logs in the module. + * + * Filtering of logs in modules is independent for each backend. + * + * @param backend_id Backend ID which want to chenge its configuration. + * @param module_id Module ID which logs will be reconfigured. + * @param severity New severity filter. + */ +void nrf_log_module_filter_set(uint32_t backend_id, + uint32_t module_id, + nrf_log_severity_t severity); + +/** + * @brief Function for getting module severity level. + * + * @param backend_id Backend ID. + * @param module_id Module ID. + * @param is_ordered_idx Module ID is given is index in alphabetically sorted list of modules. + * @param dynamic It true current filter for given backend is returned. If false then + * compiled-in level is returned (maximum available). If this parameter is + * false then backend_id parameter is not used. + * + * @return Severity. + */ +nrf_log_severity_t nrf_log_module_filter_get(uint32_t backend_id, + uint32_t module_id, + bool is_ordered_idx, + bool dynamic); + +/** + * @brief Function stores current filtering configuration into non-volatile memory using @ref fds module. + * + * @return NRF_SUCCESS or @ref fds error code. + */ +ret_code_t nrf_log_config_store(void); + +/** + * @brief Function loads configuration from non-volatile memory using @ref fds module. + * + * @retval NRF_SUCCESS On successful loading. + * @retval NRF_ERROR_NOT_FOUND Configuration file not found. + * @retval NRF_ERROR_INTERNAL Other @ref fds error on reading configuration file. + */ +ret_code_t nrf_log_config_load(void); + +#ifdef __cplusplus +} +#endif + +#endif // NRF_LOG_CTRL_H + +/** + *@} + **/ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_default_backends.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_default_backends.h new file mode 100644 index 0000000..1f14825 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_default_backends.h @@ -0,0 +1,81 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_DEFAULT_BACKENDS_H__ +#define NRF_LOG_DEFAULT_BACKENDS_H__ + +/**@file + * @addtogroup nrf_log Logger module + * @ingroup app_common + * + * @defgroup nrf_log_default_backends Functions for initializing and adding default backends + * @{ + * @ingroup nrf_log + * @brief The nrf_log default backends. + */ + +#include "sdk_config.h" +#include "sdk_errors.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @def NRF_LOG_DEFAULT_BACKENDS_INIT + * @brief Macro for initializing default backends. + * + * Each backend enabled in configuration is initialized and added as a backend to the logger. + */ +#if NRF_LOG_ENABLED +#define NRF_LOG_DEFAULT_BACKENDS_INIT() nrf_log_default_backends_init() +#else +#define NRF_LOG_DEFAULT_BACKENDS_INIT() +#endif + +void nrf_log_default_backends_init(void); + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif // NRF_LOG_DEFAULT_BACKENDS_H__ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_instance.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_instance.h new file mode 100644 index 0000000..e038a55 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_instance.h @@ -0,0 +1,163 @@ +/** + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_INSTANCE_H +#define NRF_LOG_INSTANCE_H + +#include "sdk_config.h" +#include "nrf_section.h" +#include "nrf_log_types.h" +#include + + +/* + * For GCC, sections are sorted in the group by the linker. For IAR and KEIL, it is assumed that linker will sort + * dynamic and const section in the same order (but in different locations). Proper message formatting + * is based on that assumption. + */ +#if defined(__GNUC__) +#define NRF_LOG_DYNAMIC_SECTION_NAME(_module_name) CONCAT_2(log_dynamic_data_,_module_name) +#define NRF_LOG_FILTER_SECTION_NAME(_module_name) CONCAT_2(log_filter_data_,_module_name) +#define NRF_LOG_CONST_SECTION_NAME(_module_name) CONCAT_2(log_const_data_,_module_name) +#else +#define NRF_LOG_DYNAMIC_SECTION_NAME(_module_name) log_dynamic_data +#define NRF_LOG_FILTER_SECTION_NAME(_module_name) log_filter_data +#define NRF_LOG_CONST_SECTION_NAME(_module_name) log_const_data +#endif + +#define NRF_LOG_ITEM_DATA(_name) CONCAT_3(m_nrf_log_,_name,_logs_data) +#define NRF_LOG_ITEM_DATA_DYNAMIC(_name) CONCAT_2(NRF_LOG_ITEM_DATA(_name),_dynamic) +#define NRF_LOG_ITEM_DATA_FILTER(_name) CONCAT_2(NRF_LOG_ITEM_DATA(_name),_filter) +#define NRF_LOG_ITEM_DATA_CONST(_name) CONCAT_2(NRF_LOG_ITEM_DATA(_name),_const) + +#ifdef UNIT_TEST +#define _CONST +#else +#define _CONST const +#endif + +/*lint -save -esym(526,log_const_data*) -esym(526,log_dynamic_data*)*/ +NRF_SECTION_DEF(log_dynamic_data, nrf_log_module_dynamic_data_t); +NRF_SECTION_DEF(log_filter_data, nrf_log_module_filter_data_t); +NRF_SECTION_DEF(log_const_data, nrf_log_module_const_data_t); +/*lint -restore*/ + +#define NRF_LOG_INTERNAL_CONST_ITEM_REGISTER( \ + _name, _str_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ + NRF_SECTION_ITEM_REGISTER(NRF_LOG_CONST_SECTION_NAME(_name), \ + _CONST nrf_log_module_const_data_t NRF_LOG_ITEM_DATA_CONST(_name)) = { \ + .p_module_name = _str_name, \ + .info_color_id = (_info_color), \ + .debug_color_id = (_debug_color), \ + .compiled_lvl = (nrf_log_severity_t)(_compiled_lvl), \ + .initial_lvl = (nrf_log_severity_t)(_initial_lvl), \ + } + +#if NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_INTERNAL_ITEM_REGISTER( \ + _name, _str_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ + NRF_LOG_INTERNAL_CONST_ITEM_REGISTER(_name, \ + _str_name, \ + _info_color, \ + _debug_color, \ + _initial_lvl, \ + _compiled_lvl); \ + NRF_SECTION_ITEM_REGISTER(NRF_LOG_DYNAMIC_SECTION_NAME(_name), \ + nrf_log_module_dynamic_data_t NRF_LOG_ITEM_DATA_DYNAMIC(_name)); \ + NRF_SECTION_ITEM_REGISTER(NRF_LOG_FILTER_SECTION_NAME(_name), \ + nrf_log_module_filter_data_t NRF_LOG_ITEM_DATA_FILTER(_name)) + +#else +#define NRF_LOG_INTERNAL_ITEM_REGISTER( \ + _name, _str_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ + NRF_LOG_INTERNAL_CONST_ITEM_REGISTER(_name, \ + _str_name, \ + _info_color, \ + _debug_color, \ + _initial_lvl, \ + _compiled_lvl) + +#endif +/**@file + * + * @defgroup nrf_log_instance Macros for logging on instance level + * @{ + * @ingroup nrf_log + * + * @brief Macros for logging on instance level + */ + +/** @def NRF_LOG_INSTANCE_PTR_DECLARE + * @brief Macro for declaring a logger instance pointer in the module stucture. + */ + +/** @def NRF_LOG_INSTANCE_REGISTER + * @brief Macro for creating an independent module instance. + * + * Module instance provides filtering of logs on instance level instead of module level. + */ + +/** @def NRF_LOG_INSTANCE_PTR_INIT + * @brief Macro for initializing a pointer to the logger instance. + */ + + + /** @} */ +#if NRF_LOG_ENABLED && NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_INSTANCE_PTR_DECLARE(_p_name) nrf_log_module_dynamic_data_t * _p_name; + +#define NRF_LOG_INSTANCE_REGISTER( \ + _module_name, _inst_name, _info_color, _debug_color, _initial_lvl, _compiled_lvl) \ + NRF_LOG_INTERNAL_ITEM_REGISTER(CONCAT_3(_module_name,_,_inst_name), \ + STRINGIFY(_module_name._inst_name), \ + _info_color, \ + _debug_color, \ + _initial_lvl, \ + _compiled_lvl) + +#define NRF_LOG_INSTANCE_PTR_INIT(_p_name, _module_name, _inst_name) \ + ._p_name = &NRF_LOG_ITEM_DATA_DYNAMIC(CONCAT_3(_module_name,_,_inst_name)), + +#else +#define NRF_LOG_INSTANCE_PTR_DECLARE(_p_name) +#define NRF_LOG_INSTANCE_REGISTER(_module_name, _inst_name, info_color, debug_color, _initial_lvl, compiled_lvl) +#define NRF_LOG_INSTANCE_PTR_INIT(_p_name, _module_name, _inst_name) +#endif + +#endif //NRF_LOG_INSTANCE_H diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_str_formatter.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_str_formatter.h new file mode 100644 index 0000000..85b7fd3 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_str_formatter.h @@ -0,0 +1,86 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/**@file + * + * @defgroup nrf_log_str_formatter String formatter for the logger messages + * @{ + * @ingroup nrf_log + */ + +#ifndef NRF_LOG_STR_FORMATTER_H +#define NRF_LOG_STR_FORMATTER_H + +#include +#include "nrf_fprintf.h" +#include "nrf_log_ctrl.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct +{ + uint32_t timestamp; + uint16_t module_id; + uint16_t dropped; + nrf_log_severity_t severity; + uint8_t use_colors; +} nrf_log_str_formatter_entry_params_t; + + +void nrf_log_std_entry_process(char const * p_str, + uint32_t const * p_args, + uint32_t nargs, + nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx); + +void nrf_log_hexdump_entry_process(uint8_t * p_data, + uint32_t data_len, + nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx); + +void nrf_log_str_formatter_timestamp_freq_set(uint32_t freq); +#ifdef __cplusplus +} +#endif + +#endif //NRF_LOG_STR_FORMATTER_H +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/nrf_log_types.h b/HAL_Driver/sdk/components/libraries/log/nrf_log_types.h new file mode 100644 index 0000000..38bfa2b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/nrf_log_types.h @@ -0,0 +1,93 @@ +/** + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_TYPES_H +#define NRF_LOG_TYPES_H + +#include + +/** + * @brief Logger severity levels. + */ +typedef enum +{ + NRF_LOG_SEVERITY_NONE, + NRF_LOG_SEVERITY_ERROR, + NRF_LOG_SEVERITY_WARNING, + NRF_LOG_SEVERITY_INFO, + NRF_LOG_SEVERITY_DEBUG, + NRF_LOG_SEVERITY_INFO_RAW, /* Artificial level to pass information about skipping string postprocessing.*/ +} nrf_log_severity_t; + +/** + * @brief Structure holding dynamic data associated with a module. + * + * See @ref NRF_LOG_MODULE_REGISTER and @ref NRF_LOG_INSTANCE_REGISTER. + */ +typedef struct +{ + uint16_t order_idx; ///< Ordered index of the module (used for auto-completion). + uint16_t filter; ///< Current highest severity level accepted (redundant to @ref nrf_log_module_filter_data_t::filter_lvls, used for optimization) +} nrf_log_module_dynamic_data_t; + +/** + * @brief Structure holding dynamic filters associated with a module or instance if filtering is enabled (@ref NRF_LOG_FILTERS_ENABLED). + * + * @note Backend filters logically are part of @ref nrf_log_module_dynamic_data_t but they are kept separated to enable storing them in non-volatile memory. + */ +typedef struct +{ + uint32_t filter_lvls; ///< Current severity levels for each backend (3 bits per backend). +} nrf_log_module_filter_data_t; + +/** + * @brief Structure holding constant data associated with a module or instance. + * + * See @ref NRF_LOG_MODULE_REGISTER and @ref NRF_LOG_INSTANCE_REGISTER. + */ +typedef struct +{ + const char * p_module_name; ///< Module or instance name. + uint8_t info_color_id; ///< Color code of info messages. + uint8_t debug_color_id; ///< Color code of debug messages. + nrf_log_severity_t compiled_lvl; ///< Compiled highest severity level. + nrf_log_severity_t initial_lvl; ///< Severity level for given module or instance set on backend initialization. +} nrf_log_module_const_data_t; + +#endif //NRF_LOG_TYPES_H diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_rtt.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_rtt.c new file mode 100644 index 0000000..7fb0760 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_rtt.c @@ -0,0 +1,123 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_RTT) +#include "nrf_log_backend_rtt.h" +#include "nrf_log_backend_serial.h" +#include "nrf_log_str_formatter.h" +#include "nrf_log_internal.h" +#include "nrf_delay.h" +#include +#include + +static bool m_host_present; + +static uint8_t m_string_buff[NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE]; + +void nrf_log_backend_rtt_init(void) +{ + SEGGER_RTT_Init(); +} + +static void serial_tx(void const * p_context, char const * buffer, size_t len) +{ + if (len) + { + uint32_t idx = 0; + uint32_t processed; + uint32_t watchdog_counter = NRF_LOG_BACKEND_RTT_TX_RETRY_CNT; + do + { + processed = SEGGER_RTT_WriteNoLock(0, &buffer[idx], len); + idx += processed; + len -= processed; + if (processed == 0) + { + /* There are two possible reasons for not writing any data to RTT: + * - The host is not connected and not reading the data. + * - The buffer got full and will be read by the host. + * These two situations are distinguished using the following algorithm. + * At the begining, the module assumes that the host is active, + * so when no data is read, it busy waits and retries. + * If, after retrying, the host reads the data, the module assumes that the host is active. + * If it fails, the module assumes that the host is inactive and stores that information. On next + * call, only one attempt takes place. The host is marked as active if the attempt is successful. + */ + if (!m_host_present) + { + break; + } + else + { + nrf_delay_ms(NRF_LOG_BACKEND_RTT_TX_RETRY_DELAY_MS); + watchdog_counter--; + if (watchdog_counter == 0) + { + m_host_present = false; + break; + } + } + } + m_host_present = true; + } while (len); + } +} +static void nrf_log_backend_rtt_put(nrf_log_backend_t const * p_backend, + nrf_log_entry_t * p_msg) +{ + nrf_log_backend_serial_put(p_backend, p_msg, m_string_buff, NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE, serial_tx); +} + +static void nrf_log_backend_rtt_flush(nrf_log_backend_t const * p_backend) +{ + +} + +static void nrf_log_backend_rtt_panic_set(nrf_log_backend_t const * p_backend) +{ + +} + +const nrf_log_backend_api_t nrf_log_backend_rtt_api = { + .put = nrf_log_backend_rtt_put, + .flush = nrf_log_backend_rtt_flush, + .panic_set = nrf_log_backend_rtt_panic_set, +}; +#endif //NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_RTT) diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.c new file mode 100644 index 0000000..a12266d --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.c @@ -0,0 +1,116 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "nrf_log_backend_serial.h" +#include "nrf_log_str_formatter.h" +#include "nrf_log_internal.h" + +void nrf_log_backend_serial_put(nrf_log_backend_t const * p_backend, + nrf_log_entry_t * p_msg, + uint8_t * p_buffer, + uint32_t length, + nrf_fprintf_fwrite tx_func) +{ + nrf_memobj_get(p_msg); + + nrf_fprintf_ctx_t fprintf_ctx = { + .p_io_buffer = (char *)p_buffer, + .io_buffer_size = length, + .io_buffer_cnt = 0, + .auto_flush = false, + .p_user_ctx = NULL, + .fwrite = tx_func + }; + + nrf_log_str_formatter_entry_params_t params; + + nrf_log_header_t header; + size_t memobj_offset = 0; + + nrf_memobj_read(p_msg, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); + memobj_offset = HEADER_SIZE*sizeof(uint32_t); + + params.timestamp = header.timestamp; + params.module_id = header.module_id; + params.dropped = header.dropped; + params.use_colors = NRF_LOG_USES_COLORS; + + /*lint -save -e438*/ + if (header.base.generic.type == HEADER_TYPE_STD) + { + char const * p_log_str = (char const *)((uint32_t)header.base.std.addr); + params.severity = (nrf_log_severity_t)header.base.std.severity; + uint32_t nargs = header.base.std.nargs; + uint32_t args[NRF_LOG_MAX_NUM_OF_ARGS]; + + nrf_memobj_read(p_msg, args, nargs*sizeof(uint32_t), memobj_offset); + memobj_offset += (nargs*sizeof(uint32_t)); + + nrf_log_std_entry_process(p_log_str, + args, + nargs, + ¶ms, + &fprintf_ctx); + + } + else if (header.base.generic.type == HEADER_TYPE_HEXDUMP) + { + uint32_t data_len = header.base.hexdump.len; + params.severity = (nrf_log_severity_t)header.base.hexdump.severity; + uint8_t data_buf[8]; + uint32_t chunk_len; + do + { + chunk_len = sizeof(data_buf) > data_len ? data_len : sizeof(data_buf); + nrf_memobj_read(p_msg, data_buf, chunk_len, memobj_offset); + memobj_offset += chunk_len; + data_len -= chunk_len; + + nrf_log_hexdump_entry_process(data_buf, + chunk_len, + ¶ms, + &fprintf_ctx); + } while (data_len > 0); + } + nrf_memobj_put(p_msg); + /*lint -restore*/ +} +#endif //NRF_LOG_ENABLED diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.h b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.h new file mode 100644 index 0000000..7b3ecdb --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_serial.h @@ -0,0 +1,77 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_BACKEND_SERIAL_H +#define NRF_LOG_BACKEND_SERIAL_H +/**@file + * @addtogroup nrf_log Logger module + * @ingroup app_common + * + * @defgroup nrf_log_backend_serial Common part of serial backends + * @{ + * @ingroup nrf_log + * @brief The nrf_log serial backend common put function. + */ + + +#include "nrf_log_backend_interface.h" +#include "nrf_fprintf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief A function for processing logger entry with simple serial interface as output. + * + * + */ +void nrf_log_backend_serial_put(nrf_log_backend_t const * p_backend, + nrf_log_entry_t * p_msg, + uint8_t * p_buffer, + uint32_t length, + nrf_fprintf_fwrite tx_func); + +#endif //NRF_LOG_BACKEND_SERIAL_H + +#ifdef __cplusplus +} +#endif + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_uart.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_uart.c new file mode 100644 index 0000000..e407181 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_backend_uart.c @@ -0,0 +1,116 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_UART) +#include "nrf_log_backend_uart.h" +#include "nrf_log_backend_serial.h" +#include "nrf_log_internal.h" +#include "nrf_drv_uart.h" +#include "app_error.h" + +nrf_drv_uart_t m_uart = NRF_DRV_UART_INSTANCE(0); + +static uint8_t m_string_buff[NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE]; +static volatile bool m_xfer_done; +static bool m_async_mode; +static void uart_evt_handler(nrf_drv_uart_event_t * p_event, void * p_context) +{ + m_xfer_done = true; +} + +static void uart_init(bool async_mode) +{ + nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; + config.pseltxd = NRF_LOG_BACKEND_UART_TX_PIN; + config.pselrxd = NRF_UART_PSEL_DISCONNECTED; + config.pselcts = NRF_UART_PSEL_DISCONNECTED; + config.pselrts = NRF_UART_PSEL_DISCONNECTED; + config.baudrate = (nrf_uart_baudrate_t)NRF_LOG_BACKEND_UART_BAUDRATE; + ret_code_t err_code = nrf_drv_uart_init(&m_uart, &config, async_mode ? uart_evt_handler : NULL); + APP_ERROR_CHECK(err_code); + + m_async_mode = async_mode; +} + +void nrf_log_backend_uart_init(void) +{ + bool async_mode = NRF_LOG_DEFERRED ? true : false; + uart_init(async_mode); +} + +static void serial_tx(void const * p_context, char const * p_buffer, size_t len) +{ + uint8_t len8 = (uint8_t)(len & 0x000000FF); + m_xfer_done = false; + ret_code_t err_code = nrf_drv_uart_tx(&m_uart, (uint8_t *)p_buffer, len8); + APP_ERROR_CHECK(err_code); + /* wait for completion since buffer is reused*/ + while (m_async_mode && (m_xfer_done == false)) + { + + } + +} + +static void nrf_log_backend_uart_put(nrf_log_backend_t const * p_backend, + nrf_log_entry_t * p_msg) +{ + nrf_log_backend_serial_put(p_backend, p_msg, m_string_buff, + NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE, serial_tx); +} + +static void nrf_log_backend_uart_flush(nrf_log_backend_t const * p_backend) +{ + +} + +static void nrf_log_backend_uart_panic_set(nrf_log_backend_t const * p_backend) +{ + nrf_drv_uart_uninit(&m_uart); + + uart_init(false); +} + +const nrf_log_backend_api_t nrf_log_backend_uart_api = { + .put = nrf_log_backend_uart_put, + .flush = nrf_log_backend_uart_flush, + .panic_set = nrf_log_backend_uart_panic_set, +}; +#endif //NRF_MODULE_ENABLED(NRF_LOG) && NRF_MODULE_ENABLED(NRF_LOG_BACKEND_UART) diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_ctrl_internal.h b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_ctrl_internal.h new file mode 100644 index 0000000..57abb46 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_ctrl_internal.h @@ -0,0 +1,91 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_CTRL_INTERNAL_H +#define NRF_LOG_CTRL_INTERNAL_H +/** + * @cond (NODOX) + * @defgroup nrf_log_ctrl_internal Auxiliary internal types declarations + * @{ + * @internal + */ + +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) + +#define NRF_LOG_LFCLK_FREQ 32768 + +#ifdef APP_TIMER_CONFIG_RTC_FREQUENCY +#define LOG_TIMESTAMP_DEFAULT_FREQUENCY ((NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY == 0) ? \ + (NRF_LOG_LFCLK_FREQ/(APP_TIMER_CONFIG_RTC_FREQUENCY + 1)) : \ + NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY) +#else +#define LOG_TIMESTAMP_DEFAULT_FREQUENCY NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY +#endif + +#define NRF_LOG_INTERNAL_INIT(...) \ + nrf_log_init(GET_VA_ARG_1(__VA_ARGS__), \ + GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__, LOG_TIMESTAMP_DEFAULT_FREQUENCY))) + +#define NRF_LOG_INTERNAL_PROCESS() nrf_log_frontend_dequeue() +#define NRF_LOG_INTERNAL_FLUSH() \ + do { \ + while (NRF_LOG_INTERNAL_PROCESS()); \ + } while (0) + +#define NRF_LOG_INTERNAL_FINAL_FLUSH() \ + do { \ + nrf_log_panic(); \ + NRF_LOG_INTERNAL_FLUSH(); \ + } while (0) + + +#else // NRF_MODULE_ENABLED(NRF_LOG) +#define NRF_LOG_INTERNAL_PROCESS() false +#define NRF_LOG_INTERNAL_FLUSH() +#define NRF_LOG_INTERNAL_INIT(...) NRF_SUCCESS +#define NRF_LOG_INTERNAL_HANDLERS_SET(default_handler, bytes_handler) \ + UNUSED_PARAMETER(default_handler); UNUSED_PARAMETER(bytes_handler) +#define NRF_LOG_INTERNAL_FINAL_FLUSH() +#endif // NRF_MODULE_ENABLED(NRF_LOG) + +/** @} + * @endcond + */ +#endif // NRF_LOG_CTRL_INTERNAL_H diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_default_backends.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_default_backends.c new file mode 100644 index 0000000..b237db7 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_default_backends.c @@ -0,0 +1,76 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "nrf_log_default_backends.h" +#include "nrf_log_ctrl.h" +#include "nrf_log_internal.h" +#include "nrf_assert.h" + +#if defined(NRF_LOG_BACKEND_RTT_ENABLED) && NRF_LOG_BACKEND_RTT_ENABLED +#include "nrf_log_backend_rtt.h" +NRF_LOG_BACKEND_RTT_DEF(rtt_log_backend); +#endif + +#if defined(NRF_LOG_BACKEND_UART_ENABLED) && NRF_LOG_BACKEND_UART_ENABLED +#include "nrf_log_backend_uart.h" +NRF_LOG_BACKEND_UART_DEF(uart_log_backend); +#endif + +void nrf_log_default_backends_init(void) +{ + int32_t backend_id = -1; + (void)backend_id; +#if defined(NRF_LOG_BACKEND_RTT_ENABLED) && NRF_LOG_BACKEND_RTT_ENABLED + nrf_log_backend_rtt_init(); + backend_id = nrf_log_backend_add(&rtt_log_backend, NRF_LOG_SEVERITY_DEBUG); + ASSERT(backend_id >= 0); + nrf_log_backend_enable(&rtt_log_backend); +#endif + +#if defined(NRF_LOG_BACKEND_UART_ENABLED) && NRF_LOG_BACKEND_UART_ENABLED + nrf_log_backend_uart_init(); + backend_id = nrf_log_backend_add(&uart_log_backend, NRF_LOG_SEVERITY_DEBUG); + ASSERT(backend_id >= 0); + nrf_log_backend_enable(&uart_log_backend); +#endif +} +#endif diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_frontend.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_frontend.c new file mode 100644 index 0000000..ea962ac --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_frontend.c @@ -0,0 +1,1561 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "app_util.h" +#include "app_util_platform.h" +#include "nrf_log.h" +#include "nrf_log_internal.h" +#include "nrf_log_ctrl.h" +#include "nrf_log_backend_interface.h" +#include "nrf_log_str_formatter.h" +#include "nrf_section.h" +#include "nrf_ringbuf.h" +#include "nrf_memobj.h" +#include "nrf_atomic.h" +#include + +STATIC_ASSERT((NRF_LOG_BUFSIZE % 4) == 0); +STATIC_ASSERT(IS_POWER_OF_TWO(NRF_LOG_BUFSIZE)); + +#define NRF_LOG_BUF_WORDS (NRF_LOG_BUFSIZE/4) + +#if NRF_MODULE_ENABLED(FDS) && NRF_LOG_FILTERS_ENABLED +#define LOG_CONFIG_LOAD_STORE_ENABLED 1 +#else +#define LOG_CONFIG_LOAD_STORE_ENABLED 0 +#endif + +#if NRF_LOG_BUF_WORDS < 32 +#warning "NRF_LOG_BUFSIZE too small, significant number of logs may be lost." +#endif + +NRF_MEMOBJ_POOL_DEF(log_mempool, NRF_LOG_MSGPOOL_ELEMENT_SIZE, NRF_LOG_MSGPOOL_ELEMENT_COUNT); +NRF_RINGBUF_DEF(m_log_push_ringbuf, NRF_LOG_STR_PUSH_BUFFER_SIZE); + +#define NRF_LOG_BACKENDS_FULL 0xFF +#define NRF_LOG_FILTER_BITS_PER_BACKEND 3 +#define NRF_LOG_MAX_BACKENDS (32/NRF_LOG_FILTER_BITS_PER_BACKEND) +#define NRF_LOG_MAX_HEXDUMP (NRF_LOG_MSGPOOL_ELEMENT_SIZE*NRF_LOG_MSGPOOL_ELEMENT_COUNT/2) +#define NRF_LOG_INVALID_BACKEND_U32 0xFFFFFFFF +/** + * brief An internal control block of the logger + * + * @note Circular buffer is using never cleared indexes and a mask. It means + * that logger may break when indexes overflows. However, it is quite unlikely. + * With rate of 1000 log entries with 2 parameters per second such situation + * would happen after 12 days. + */ +typedef struct +{ + uint32_t wr_idx; // Current write index (never reset) + uint32_t rd_idx; // Current read index (never_reset) + uint32_t mask; // Size of buffer (must be power of 2) presented as mask + uint32_t buffer[NRF_LOG_BUF_WORDS]; + nrf_log_timestamp_func_t timestamp_func; // A pointer to function that returns timestamp + nrf_log_backend_t const * p_backend_head; + nrf_atomic_flag_t log_skipping; + nrf_atomic_flag_t log_skipped; + nrf_atomic_u32_t log_dropped_cnt; + bool autoflush; +} log_data_t; + +static log_data_t m_log_data; + + +NRF_LOG_MODULE_REGISTER(); + +// Helper macros for section variables. +#define NRF_LOG_DYNAMIC_SECTION_VARS_GET(i) NRF_SECTION_ITEM_GET(log_dynamic_data, nrf_log_module_dynamic_data_t, (i)) +#define NRF_LOG_FILTER_SECTION_VARS_GET(i) NRF_SECTION_ITEM_GET(log_filter_data, nrf_log_module_filter_data_t, (i)) + +#define NRF_LOG_CONST_SECTION_VARS_GET(i) NRF_SECTION_ITEM_GET(log_const_data, nrf_log_module_const_data_t, (i)) +#define NRF_LOG_CONST_SECTION_VARS_COUNT NRF_SECTION_ITEM_COUNT(log_const_data, nrf_log_module_const_data_t) + +ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func, uint32_t timestamp_freq) +{ + (void)NRF_LOG_ITEM_DATA_CONST(app); + + if (NRF_LOG_USES_TIMESTAMP && (timestamp_func == NULL)) + { + return NRF_ERROR_INVALID_PARAM; + } + + m_log_data.mask = NRF_LOG_BUF_WORDS - 1; + m_log_data.wr_idx = 0; + m_log_data.rd_idx = 0; + m_log_data.log_skipped = 0; + m_log_data.log_skipping = 0; + m_log_data.autoflush = NRF_LOG_DEFERRED ? false : true; + if (NRF_LOG_USES_TIMESTAMP) + { + nrf_log_str_formatter_timestamp_freq_set(timestamp_freq); + m_log_data.timestamp_func = timestamp_func; + } + + ret_code_t err_code = nrf_memobj_pool_init(&log_mempool); + if (err_code != NRF_SUCCESS) + { + return err_code; + } + + nrf_ringbuf_init(&m_log_push_ringbuf); + + uint32_t modules_cnt = NRF_LOG_CONST_SECTION_VARS_COUNT; + uint32_t i; + if (NRF_LOG_FILTERS_ENABLED) + { + uint32_t j; + //sort modules by name + for (i = 0; i < modules_cnt; i++) + { + uint32_t idx = 0; + + for (j = 0; j < modules_cnt; j++) + { + if (i != j) + { + char const * p_name0 = NRF_LOG_CONST_SECTION_VARS_GET(i)->p_module_name; + char const * p_name1 = NRF_LOG_CONST_SECTION_VARS_GET(j)->p_module_name; + if (strncmp(p_name0, p_name1, 20) > 0) + { + idx++; + } + } + + } + nrf_log_module_dynamic_data_t * p_module_ddata = NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); + p_module_ddata->order_idx = idx; + } + + /* Initialize filters */ + for (i = 0; i < modules_cnt; i++) + { + nrf_log_module_dynamic_data_t * p_module_ddata = NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); + nrf_log_module_filter_data_t * p_module_filter = NRF_LOG_FILTER_SECTION_VARS_GET(i); + p_module_ddata->filter = 0; + p_module_filter->filter_lvls = 0; + } + } + + return NRF_SUCCESS; +} + +uint32_t nrf_log_module_cnt_get(void) +{ + return NRF_LOG_CONST_SECTION_VARS_COUNT; +} + +static ret_code_t module_idx_get(uint32_t * p_idx, bool ordered_idx) +{ + if (ordered_idx) + { + uint32_t module_cnt = nrf_log_module_cnt_get(); + uint32_t i; + for (i = 0; i < module_cnt; i++) + { + nrf_log_module_dynamic_data_t * p_module_data = NRF_LOG_DYNAMIC_SECTION_VARS_GET(i); + if (p_module_data->order_idx == *p_idx) + { + *p_idx = i; + return NRF_SUCCESS; + } + } + return NRF_ERROR_NOT_FOUND; + } + else + { + return NRF_SUCCESS; + } +} +const char * nrf_log_module_name_get(uint32_t module_id, bool ordered_idx) +{ + if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) + { + nrf_log_module_const_data_t * p_module_data = NRF_LOG_CONST_SECTION_VARS_GET(module_id); + return p_module_data->p_module_name; + } + else + { + return NULL; + } +} + +uint8_t nrf_log_color_id_get(uint32_t module_id, nrf_log_severity_t severity) +{ + nrf_log_module_const_data_t * p_module_data = NRF_LOG_CONST_SECTION_VARS_GET(module_id); + uint8_t color_id; + switch (severity) + { + case NRF_LOG_SEVERITY_ERROR: + color_id = NRF_LOG_ERROR_COLOR; + break; + case NRF_LOG_SEVERITY_WARNING: + color_id = NRF_LOG_WARNING_COLOR; + break; + case NRF_LOG_SEVERITY_INFO: + color_id = p_module_data->info_color_id; + break; + case NRF_LOG_SEVERITY_DEBUG: + color_id = p_module_data->debug_color_id; + break; + default: + color_id = 0; + break; + } + return color_id; +} + +static uint16_t higher_lvl_get(uint32_t lvls) +{ + uint16_t top_lvl = 0; + uint16_t tmp_lvl; + uint32_t i; + + //Find highest level enabled by backends + for (i = 0; i < (32/NRF_LOG_LEVEL_BITS); i+=NRF_LOG_LEVEL_BITS) + { + tmp_lvl = (uint16_t)BF_GET(lvls,NRF_LOG_LEVEL_BITS, i); + if (tmp_lvl > top_lvl) + { + top_lvl = tmp_lvl; + } + } + return top_lvl; +} + +void nrf_log_module_filter_set(uint32_t backend_id, uint32_t module_id, nrf_log_severity_t severity) +{ + if (NRF_LOG_FILTERS_ENABLED) + { + nrf_log_module_dynamic_data_t * p_module_data = NRF_LOG_DYNAMIC_SECTION_VARS_GET(module_id); + nrf_log_module_filter_data_t * p_filter = NRF_LOG_FILTER_SECTION_VARS_GET(module_id); + + p_filter->filter_lvls &= ~BF_MASK(NRF_LOG_LEVEL_BITS, (NRF_LOG_LEVEL_BITS * backend_id)); + p_filter->filter_lvls |= BF_VAL(severity, NRF_LOG_LEVEL_BITS, (NRF_LOG_LEVEL_BITS * backend_id)); + + p_module_data->filter = higher_lvl_get(p_filter->filter_lvls); + } +} + +static nrf_log_severity_t nrf_log_module_init_filter_get(uint32_t module_id) +{ + nrf_log_module_const_data_t * p_module_data = + NRF_LOG_CONST_SECTION_VARS_GET(module_id); + return NRF_LOG_FILTERS_ENABLED ? p_module_data->initial_lvl : p_module_data->compiled_lvl; +} + +nrf_log_severity_t nrf_log_module_filter_get(uint32_t backend_id, + uint32_t module_id, + bool ordered_idx, + bool dynamic) +{ + nrf_log_severity_t severity = NRF_LOG_SEVERITY_NONE; + if (NRF_LOG_FILTERS_ENABLED && dynamic) + { + if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) + { + nrf_log_module_filter_data_t * p_filter = NRF_LOG_FILTER_SECTION_VARS_GET(module_id); + severity = (nrf_log_severity_t)BF_GET(p_filter->filter_lvls, + NRF_LOG_LEVEL_BITS, + (backend_id*NRF_LOG_LEVEL_BITS)); + } + } + else if (!dynamic) + { + if (module_idx_get(&module_id, ordered_idx) == NRF_SUCCESS) + { + nrf_log_module_const_data_t * p_module_data = + NRF_LOG_CONST_SECTION_VARS_GET(module_id); + severity = (nrf_log_severity_t)p_module_data->compiled_lvl; + } + } + return severity; +} +/** + * Function examines current header and omits packets which are in progress. + */ +static bool invalid_packets_omit(nrf_log_header_t const * p_header, uint32_t * p_rd_idx) +{ + bool ret = false; + if (p_header->base.generic.in_progress == 1) + { + switch (p_header->base.generic.type) + { + case HEADER_TYPE_STD: + *p_rd_idx += (HEADER_SIZE + p_header->base.std.nargs); + break; + case HEADER_TYPE_HEXDUMP: + *p_rd_idx += (HEADER_SIZE + p_header->base.hexdump.len); + break; + default: + break; + } + ret = true; + } + return ret; +} +/** + * @brief Skips the oldest, not processed logs to make space for new logs. + * @details This function moves forward read index to prepare space for new logs. + */ + +static uint32_t log_skip(void) +{ + uint16_t dropped = 0; + + (void)nrf_atomic_flag_set(&m_log_data.log_skipped); + (void)nrf_atomic_flag_set(&m_log_data.log_skipping); + + uint32_t rd_idx = m_log_data.rd_idx; + uint32_t mask = m_log_data.mask; + nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; + nrf_log_header_t header; + + // Skip packets that may be invalid (interrupted while being in progress) + do { + if (invalid_packets_omit(p_header, &rd_idx)) + { + //something was omitted. Point to new header and try again. + p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; + } + else + { + break; + } + } while (true); + + uint32_t i; + for (i = 0; i < HEADER_SIZE; i++) + { + ((uint32_t*)&header)[i] = m_log_data.buffer[rd_idx++ & mask]; + } + + switch (header.base.generic.type) + { + case HEADER_TYPE_HEXDUMP: + dropped = header.dropped; + rd_idx += CEIL_DIV(header.base.hexdump.len, sizeof(uint32_t)); + break; + case HEADER_TYPE_STD: + dropped = header.dropped; + rd_idx += header.base.std.nargs; + break; + default: + ASSERT(false); + break; + } + + uint32_t log_skipping_tmp = nrf_atomic_flag_clear_fetch(&m_log_data.log_skipping); + //update read index only if log_skip was not interrupted by another log skip + if (log_skipping_tmp) + { + m_log_data.rd_idx = rd_idx; + } + + return (uint32_t)dropped; +} + +/** + * @brief Function for getting number of dropped logs. Dropped counter is reset after reading. + * + * @return Number of dropped logs saturated to 16 bits. + */ +static inline uint32_t dropped_sat16_get(void) +{ + uint32_t dropped = nrf_atomic_u32_fetch_store(&m_log_data.log_dropped_cnt, 0); + return __USAT(dropped, 16); //Saturate to 16 bits +} + + +static inline void std_header_set(uint32_t severity_mid, + char const * const p_str, + uint32_t nargs, + uint32_t wr_idx, + uint32_t mask) +{ + + + //Prepare header - in reverse order to ensure that packet type is validated (set to STD as last action) + uint32_t module_id = severity_mid >> NRF_LOG_MODULE_ID_POS; + uint32_t dropped = dropped_sat16_get(); + ASSERT(module_id < nrf_log_module_cnt_get()); + m_log_data.buffer[(wr_idx + 1) & mask] = module_id | (dropped << 16); + + if (NRF_LOG_USES_TIMESTAMP) + { + m_log_data.buffer[(wr_idx + 2) & mask] = m_log_data.timestamp_func(); + } + + nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[wr_idx & mask]; + p_header->base.std.severity = severity_mid & NRF_LOG_LEVEL_MASK; + p_header->base.std.nargs = nargs; + p_header->base.std.addr = ((uint32_t)(p_str) & STD_ADDR_MASK); + p_header->base.std.type = HEADER_TYPE_STD; + p_header->base.std.in_progress = 0; +} + +/** + * @brief Allocates chunk in a buffer for one entry and injects overflow if + * there is no room for requested entry. + * + * @param content_len Number of 32bit arguments. In case of allocating for hex dump it + * is the size of the buffer in 32bit words (ceiled). + * @param p_wr_idx Pointer to write index. + * + * @return True if successful allocation, false otherwise. + * + */ +static inline bool buf_prealloc(uint32_t content_len, uint32_t * p_wr_idx, bool std) +{ + uint32_t req_len = content_len + HEADER_SIZE; + bool ret = true; + CRITICAL_REGION_ENTER(); + *p_wr_idx = m_log_data.wr_idx; + uint32_t available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx); + while (req_len > available_words) + { + UNUSED_RETURN_VALUE(nrf_atomic_u32_add(&m_log_data.log_dropped_cnt, 1)); + if (NRF_LOG_ALLOW_OVERFLOW) + { + uint32_t dropped_in_skip = log_skip(); + UNUSED_RETURN_VALUE(nrf_atomic_u32_add(&m_log_data.log_dropped_cnt, dropped_in_skip)); + available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx); + } + else + { + ret = false; + break; + } + } + + if (ret) + { + nrf_log_main_header_t invalid_header; + invalid_header.raw = 0; + + if (std) + { + invalid_header.std.type = HEADER_TYPE_STD; + invalid_header.std.in_progress = 1; + invalid_header.std.nargs = content_len; + } + else + { + invalid_header.hexdump.type = HEADER_TYPE_HEXDUMP; + invalid_header.hexdump.in_progress = 1; + invalid_header.hexdump.len = content_len; + } + + nrf_log_main_header_t * p_header = + (nrf_log_main_header_t *)&m_log_data.buffer[m_log_data.wr_idx & m_log_data.mask]; + + p_header->raw = invalid_header.raw; + + m_log_data.wr_idx += req_len; + } + + CRITICAL_REGION_EXIT(); + return ret; +} + +char const * nrf_log_push(char * const p_str) +{ + if ((m_log_data.autoflush) || (p_str == NULL)) + { + return p_str; + } + + size_t ssize = strlen(p_str) + 1; // + 1 for null termination + uint8_t * p_dst; + // Allocate space in the ring buffer. It may be smaller than the requested string in case of buffer wrapping or when the ring buffer size is too small. + // Once the string is copied into the buffer, the space is immediately freed. The string is kept in the buffer but can be overwritten. + // It is done that way because there is no other place where space could be freed since string processing happens in + // the logger backends, often by modules which are generic and not aware of internals of the logger. + if (nrf_ringbuf_alloc(&m_log_push_ringbuf, &p_dst, &ssize, true) == NRF_SUCCESS) + { + ret_code_t err; + + memcpy(p_dst, p_str, ssize); + + //Terminate in case string was partial. + p_dst[ssize - 1] = '\0'; + + err = nrf_ringbuf_put(&m_log_push_ringbuf, ssize); + ASSERT(err == NRF_SUCCESS); + + //Immediately free the space where string was put. + err = nrf_ringbuf_free(&m_log_push_ringbuf, ssize); + ASSERT(err == NRF_SUCCESS); + + return (char const *)p_dst; + } + else + { + return NULL; + } +} + +static inline void std_n(uint32_t severity_mid, + char const * const p_str, + uint32_t const * args, + uint32_t nargs) +{ + uint32_t mask = m_log_data.mask; + uint32_t wr_idx; + + if (buf_prealloc(nargs, &wr_idx, true)) + { + // Proceed only if buffer was successfully preallocated. + + uint32_t data_idx = wr_idx + HEADER_SIZE; + uint32_t i; + for (i = 0; i < nargs; i++) + { + m_log_data.buffer[data_idx++ & mask] =args[i]; + } + std_header_set(severity_mid, p_str, nargs, wr_idx, mask); + } + if (m_log_data.autoflush) + { + NRF_LOG_FLUSH(); + } + +} + +void nrf_log_frontend_std_0(uint32_t severity_mid, char const * const p_str) +{ + std_n(severity_mid, p_str, NULL, 0); +} + + +void nrf_log_frontend_std_1(uint32_t severity_mid, + char const * const p_str, + uint32_t val0) +{ + uint32_t args[] = {val0}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_std_2(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1) +{ + uint32_t args[] = {val0, val1}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_std_3(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2) +{ + uint32_t args[] = {val0, val1, val2}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_std_4(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3) +{ + uint32_t args[] = {val0, val1, val2, val3}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_std_5(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3, + uint32_t val4) +{ + uint32_t args[] = {val0, val1, val2, val3, val4}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_std_6(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3, + uint32_t val4, + uint32_t val5) +{ + uint32_t args[] = {val0, val1, val2, val3, val4, val5}; + std_n(severity_mid, p_str, args, ARRAY_SIZE(args)); +} + + +void nrf_log_frontend_hexdump(uint32_t severity_mid, + const void * const p_data, + uint16_t length) +{ + uint32_t mask = m_log_data.mask; + + uint32_t wr_idx; + if (buf_prealloc(CEIL_DIV(length, sizeof(uint32_t)), &wr_idx, false)) + { + uint32_t header_wr_idx = wr_idx; + wr_idx += HEADER_SIZE; + + uint32_t space0 = sizeof(uint32_t) * (m_log_data.mask + 1 - (wr_idx & mask)); + if (length <= space0) + { + memcpy(&m_log_data.buffer[wr_idx & mask], p_data, length); + } + else + { + memcpy(&m_log_data.buffer[wr_idx & mask], p_data, space0); + memcpy(&m_log_data.buffer[0], &((uint8_t *)p_data)[space0], length - space0); + } + + //Prepare header - in reverse order to ensure that packet type is validated (set to HEXDUMP as last action) + if (NRF_LOG_USES_TIMESTAMP) + { + m_log_data.buffer[(header_wr_idx + 2) & mask] = m_log_data.timestamp_func(); + } + + uint32_t module_id = severity_mid >> NRF_LOG_MODULE_ID_POS; + uint32_t dropped = dropped_sat16_get(); + m_log_data.buffer[(header_wr_idx + 1) & mask] = module_id | (dropped << 16); + //Header prepare + nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[header_wr_idx & mask]; + p_header->base.hexdump.severity = severity_mid & NRF_LOG_LEVEL_MASK; + p_header->base.hexdump.offset = 0; + p_header->base.hexdump.len = length; + p_header->base.hexdump.type = HEADER_TYPE_HEXDUMP; + p_header->base.hexdump.in_progress = 0; + + + + } + + if (m_log_data.autoflush) + { + NRF_LOG_FLUSH(); + } +} + + +bool buffer_is_empty(void) +{ + return (m_log_data.rd_idx == m_log_data.wr_idx); +} + +bool nrf_log_frontend_dequeue(void) +{ + + if (buffer_is_empty()) + { + return false; + } + m_log_data.log_skipped = 0; + //It has to be ensured that reading rd_idx occurs after skipped flag is cleared. + __DSB(); + uint32_t rd_idx = m_log_data.rd_idx; + uint32_t mask = m_log_data.mask; + nrf_log_header_t * p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; + nrf_log_header_t header; + nrf_memobj_t * p_msg_buf = NULL; + size_t memobj_offset = 0; + uint32_t severity = 0; + + // Skip any in progress packets. + do { + if (invalid_packets_omit(p_header, &rd_idx) && (m_log_data.log_skipped == 0)) + { + //Check if end of data is not reached. + if (rd_idx >= m_log_data.wr_idx) + { + m_log_data.rd_idx = m_log_data.wr_idx; + return false; + } + //something was omitted. Point to new header and try again. + p_header = (nrf_log_header_t *)&m_log_data.buffer[rd_idx & mask]; + } + else + { + break; + } + } while (true); + + uint32_t i; + for (i = 0; i < HEADER_SIZE; i++) + { + ((uint32_t*)&header)[i] = m_log_data.buffer[rd_idx++ & mask]; + } + + if (header.base.generic.type == HEADER_TYPE_HEXDUMP) + { + uint32_t orig_data_len = header.base.hexdump.len; + uint32_t data_len = MIN(header.base.hexdump.len, NRF_LOG_MAX_HEXDUMP); //limit the data + header.base.hexdump.len = data_len; + uint32_t msg_buf_size8 = sizeof(uint32_t)*HEADER_SIZE + data_len; + severity = header.base.hexdump.severity; + p_msg_buf = nrf_memobj_alloc(&log_mempool, msg_buf_size8); + + if (p_msg_buf) + { + nrf_memobj_get(p_msg_buf); + nrf_memobj_write(p_msg_buf, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); + memobj_offset += HEADER_SIZE*sizeof(uint32_t); + + uint32_t space0 = sizeof(uint32_t) * (mask + 1 - (rd_idx & mask)); + if (data_len > space0) + { + uint8_t * ptr0 = space0 ? + (uint8_t *)&m_log_data.buffer[rd_idx & mask] : + (uint8_t *)&m_log_data.buffer[0]; + uint8_t len0 = space0 ? space0 : data_len; + uint8_t * ptr1 = space0 ? + (uint8_t *)&m_log_data.buffer[0] : NULL; + uint8_t len1 = space0 ? data_len - space0 : 0; + + nrf_memobj_write(p_msg_buf, ptr0, len0, memobj_offset); + memobj_offset += len0; + if (ptr1) + { + nrf_memobj_write(p_msg_buf, ptr1, len1, memobj_offset); + } + } + else + { + uint8_t * p_data = (uint8_t *)&m_log_data.buffer[rd_idx & mask]; + nrf_memobj_write(p_msg_buf, p_data, data_len, memobj_offset); + } + rd_idx += CEIL_DIV(orig_data_len, 4); + } + } + else if (header.base.generic.type == HEADER_TYPE_STD) // standard entry + { + header.base.std.nargs = MIN(header.base.std.nargs, NRF_LOG_MAX_NUM_OF_ARGS); + uint32_t msg_buf_size32 = HEADER_SIZE + header.base.std.nargs; + severity = header.base.std.severity; + + p_msg_buf = nrf_memobj_alloc(&log_mempool, msg_buf_size32*sizeof(uint32_t)); + + if (p_msg_buf) + { + nrf_memobj_get(p_msg_buf); + nrf_memobj_write(p_msg_buf, &header, HEADER_SIZE*sizeof(uint32_t), memobj_offset); + memobj_offset += HEADER_SIZE*sizeof(uint32_t); + + for (i = 0; i < header.base.std.nargs; i++) + { + nrf_memobj_write(p_msg_buf, &m_log_data.buffer[rd_idx++ & mask], + sizeof(uint32_t), memobj_offset); + memobj_offset += sizeof(uint32_t); + } + } + } + else + { + //Do nothing. In case of log overflow buffer can contain corrupted data. + } + + if (p_msg_buf) + { + nrf_log_backend_t const * p_backend = m_log_data.p_backend_head; + if (NRF_LOG_ALLOW_OVERFLOW && m_log_data.log_skipped) + { + // Check if any log was skipped during log processing. Do not forward log if skipping + // occured because data may be invalid. + nrf_memobj_put(p_msg_buf); + } + else + { + while (p_backend) + { + bool entry_accepted = false; + if (nrf_log_backend_is_enabled(p_backend) == true) + { + if (NRF_LOG_FILTERS_ENABLED) + { + uint8_t backend_id = nrf_log_backend_id_get(p_backend); + nrf_log_module_filter_data_t * p_module_filter = + NRF_LOG_FILTER_SECTION_VARS_GET(header.module_id); + uint32_t backend_lvl = BF_GET(p_module_filter->filter_lvls, + NRF_LOG_LEVEL_BITS, + (backend_id*NRF_LOG_LEVEL_BITS)); + + //Degrade INFO_RAW level to INFO. + severity = (severity == NRF_LOG_SEVERITY_INFO_RAW) ? + NRF_LOG_SEVERITY_INFO : severity; + if (backend_lvl >= severity) + { + entry_accepted = true; + } + } + else + { + (void)severity; + entry_accepted = true; + } + } + if (entry_accepted) + { + nrf_log_backend_put(p_backend, p_msg_buf); + } + p_backend = p_backend->p_cb->p_next; + } + + nrf_memobj_put(p_msg_buf); + + if (NRF_LOG_ALLOW_OVERFLOW) + { + // Read index can be moved forward only if dequeueing process was not interrupt by + // skipping procedure. If NRF_LOG_ALLOW_OVERFLOW is set then in case of buffer gets full + // and new logger entry occurs, oldest entry is removed. In that case read index is + // changed and updating it here would corrupt the internal circular buffer. + CRITICAL_REGION_ENTER(); + if (m_log_data.log_skipped == 0) + { + m_log_data.rd_idx = rd_idx; + } + CRITICAL_REGION_EXIT(); + } + else + { + m_log_data.rd_idx = rd_idx; + } + } + } + else + { + //Could not allocate memobj - backends are not freeing them on time. + nrf_log_backend_t const * p_backend = m_log_data.p_backend_head; + //Flush all backends + while (p_backend) + { + nrf_log_backend_flush(p_backend); + p_backend = p_backend->p_cb->p_next; + } + NRF_LOG_WARNING("Backends flushed"); + } + + return buffer_is_empty() ? false : true; +} + +static int32_t backend_id_assign(void) +{ + int32_t candidate_id; + nrf_log_backend_t const * p_backend; + bool id_available; + for (candidate_id = 0; candidate_id < NRF_LOG_MAX_BACKENDS; candidate_id++) + { + p_backend = m_log_data.p_backend_head; + id_available = true; + while (p_backend) + { + if (nrf_log_backend_id_get(p_backend) == candidate_id) + { + id_available = false; + break; + } + p_backend = p_backend->p_cb->p_next; + } + if (id_available) + { + return candidate_id; + } + } + return -1; +} + +int32_t nrf_log_backend_add(nrf_log_backend_t const * p_backend, nrf_log_severity_t severity) +{ + int32_t id = backend_id_assign(); + if (id == -1) + { + return id; + } + + nrf_log_backend_id_set(p_backend, id); + //add to list + if (m_log_data.p_backend_head == NULL) + { + m_log_data.p_backend_head = p_backend; + p_backend->p_cb->p_next = NULL; + } + else + { + p_backend->p_cb->p_next = m_log_data.p_backend_head->p_cb->p_next; + m_log_data.p_backend_head->p_cb->p_next = p_backend; + } + + if (NRF_LOG_FILTERS_ENABLED) + { + uint32_t i; + for (i = 0; i < nrf_log_module_cnt_get(); i++) + { + nrf_log_severity_t buildin_lvl = nrf_log_module_init_filter_get(i); + nrf_log_severity_t actual_severity = MIN(buildin_lvl, severity); + nrf_log_module_filter_set(nrf_log_backend_id_get(p_backend), i, actual_severity); + } + } + + return id; +} + +void nrf_log_backend_remove(nrf_log_backend_t const * p_backend) +{ + nrf_log_backend_t const * p_curr = m_log_data.p_backend_head; + nrf_log_backend_t const * p_prev = NULL; + while (p_curr != p_backend) + { + p_prev = p_curr; + p_curr = p_curr->p_cb->p_next; + } + + if (p_prev) + { + p_prev->p_cb->p_next = p_backend->p_cb->p_next; + } + else + { + m_log_data.p_backend_head = NULL; + } + + p_backend->p_cb->id = NRF_LOG_BACKEND_INVALID_ID; +} + +void nrf_log_panic(void) +{ + nrf_log_backend_t const * p_backend = m_log_data.p_backend_head; + m_log_data.autoflush = true; + while (p_backend) + { + nrf_log_backend_enable(p_backend); + nrf_log_backend_panic_set(p_backend); + p_backend = p_backend->p_cb->p_next; + } +} + +#if NRF_MODULE_ENABLED(LOG_CONFIG_LOAD_STORE) +#include "fds.h" +#define LOG_CONFIG_FILE_ID 0x106E +#define LOG_CONFIG_RECORD_ID 0x3427 + +ret_code_t nrf_log_config_store(void) +{ + fds_record_desc_t desc = {0}; + fds_find_token_t token = {0}; + fds_record_t record = { + .file_id = LOG_CONFIG_FILE_ID, + .key = LOG_CONFIG_RECORD_ID, + .data = { + .p_data = NRF_LOG_FILTER_SECTION_VARS_GET(0), + .length_words = NRF_SECTION_LENGTH(log_filter_data)/sizeof(uint32_t) + } + }; + ret_code_t ret = fds_record_find(LOG_CONFIG_FILE_ID, LOG_CONFIG_RECORD_ID, &desc, &token); + if (ret == FDS_SUCCESS) + { + ret = fds_record_update(&desc, &record); + NRF_LOG_INFO("Logger configuration file updated with result:%d", ret); + } + else if (ret == FDS_ERR_NOT_FOUND) + { + ret = fds_record_write(&desc, &record); + NRF_LOG_INFO("Logger configuration file written with result:%d", ret); + } + else + { + ret = NRF_ERROR_INTERNAL; + } + return ret; +} + +ret_code_t nrf_log_config_load(void) +{ + fds_record_desc_t desc = {0}; + fds_find_token_t token = {0}; + + ret_code_t ret = fds_record_find(LOG_CONFIG_FILE_ID, LOG_CONFIG_RECORD_ID, &desc, &token); + if (ret == FDS_SUCCESS) + { + fds_flash_record_t record = {0}; + ret = fds_record_open(&desc, &record); + if (ret == NRF_SUCCESS) + { + void * p_dest = (void *)NRF_LOG_FILTER_SECTION_VARS_GET(0); + uint32_t length = NRF_SECTION_LENGTH(log_filter_data); + memcpy(p_dest, record.p_data, length); + ret = fds_record_close(&desc); + } + } + else if (ret == FDS_ERR_NOT_FOUND) + { + NRF_LOG_WARNING("Logger configuration file not found."); + ret = NRF_ERROR_NOT_FOUND; + } + else + { + ret = NRF_ERROR_INTERNAL; + } + + return ret; +} +#endif //LOG_CONFIG_LOAD_STORE_ENABLED + +#if NRF_LOG_CLI_CMDS +#include "nrf_cli.h" + +typedef void (*nrf_log_cli_backend_cmd_t)(nrf_cli_t const * p_cli, + nrf_log_backend_t const * p_backend, + size_t argc, + char * * argv); + +static const char * m_severity_lvls[] = { + "none", + "error", + "warning", + "info", + "debug", +}; + +static const char * m_severity_lvls_sorted[] = { + "debug", + "error", + "info", + "none", + "warning", +}; + +/** + * @brief Function for finding backend instance with given name. + * + * @param p_name Name of the backend instance. + * + * @return Pointer to the instance or NULL. + * + */ +static nrf_log_backend_t const * backend_find(char const * p_name) +{ + size_t num_of_backends; + nrf_log_backend_t const * p_backend; + + num_of_backends = NRF_SECTION_ITEM_COUNT(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t); + for (size_t i = 0; i < num_of_backends; i++) + { + p_backend = NRF_SECTION_ITEM_GET(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t, i); + if (strcmp(p_name, p_backend->p_name) == 0) + { + return p_backend; + } + } + return NULL; +} + +/** + * @brief Function for executing command on given backend. + */ +static void nrf_cli_backend_cmd_execute(nrf_cli_t const * p_cli, + size_t argc, + char * * argv, + nrf_log_cli_backend_cmd_t func) +{ + //Based on the structure of backend commands, name of the backend can be found at -1 (log backend command). + char const * p_backend_name = argv[-1]; + + nrf_log_backend_t const * p_backend = backend_find(p_backend_name); + + if (p_backend) + { + func(p_cli, p_backend, argc, argv); + } + else + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Invalid backend: %s\r\n", p_backend_name); + } +} + + +static void log_status(nrf_cli_t const * p_cli, + nrf_log_backend_t const * p_backend, + size_t argc, + char * * argv) +{ + UNUSED_PARAMETER(argc); + UNUSED_PARAMETER(argv); + + uint32_t modules_cnt = nrf_log_module_cnt_get(); + uint32_t i; + + + if (!nrf_log_backend_is_enabled(p_backend)) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Logs are halted!\r\n"); + } + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "%-40s | current | built-in \r\n", "module_name"); + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "----------------------------------------------------------\r\n"); + for (i = 0; i < modules_cnt; i++) + { + uint32_t backend_id = p_backend->p_cb->id; + nrf_log_severity_t module_dynamic_lvl = + nrf_log_module_filter_get(backend_id, i, true, true); + nrf_log_severity_t module_compiled_lvl = + nrf_log_module_filter_get(backend_id, i, true, false); + nrf_log_severity_t actual_compiled_lvl = + MIN(module_compiled_lvl, (nrf_log_severity_t)NRF_LOG_DEFAULT_LEVEL); + + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "%-40s | %-7s | %s%s\r\n", + nrf_log_module_name_get(i, true), + m_severity_lvls[module_dynamic_lvl], + m_severity_lvls[actual_compiled_lvl], + actual_compiled_lvl < module_compiled_lvl ? "*" : ""); + } +} + + +static void log_self_status(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + log_status(p_cli, p_cli->p_log_backend, argc, argv); +} + + +static void log_backend_status(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + nrf_cli_backend_cmd_execute(p_cli, argc, argv, log_status); +} + + +static bool module_id_get(const char * p_name, uint32_t * p_id) +{ + uint32_t modules_cnt = nrf_log_module_cnt_get(); + const char * p_tmp_name; + uint32_t j; + for (j = 0; j < modules_cnt; j++) + { + p_tmp_name = nrf_log_module_name_get(j, false); + if (strncmp(p_tmp_name, p_name, 32) == 0) + { + *p_id = j; + break; + } + } + return (j != modules_cnt); +} + + +static bool module_id_filter_set(uint32_t backend_id, + uint32_t module_id, + nrf_log_severity_t lvl) +{ + nrf_log_severity_t buildin_lvl = nrf_log_module_filter_get(backend_id, module_id, false, false); + if (lvl > buildin_lvl) + { + return false; + } + else + { + nrf_log_module_filter_set(backend_id, module_id, lvl); + return true; + } +} + + +static void log_ctrl(nrf_cli_t const * p_cli, + nrf_log_backend_t const * p_backend, + size_t argc, + char * * argv) +{ + nrf_log_severity_t lvl; + uint32_t first_m_name_idx; + uint32_t i; + bool all_modules = false; + uint32_t backend_id = p_backend->p_cb->id; + + if (argc > 0) + { + if (strncmp(argv[0], "enable", 7) == 0) + { + if (argc == 1) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Bad parameter count.\r\n"); + return; + } + + if (argc == 2) + { + all_modules = true; + } + + for (i = 0; i < ARRAY_SIZE(m_severity_lvls); i++) + { + if (strncmp(argv[1], m_severity_lvls[i], 10) == 0) + { + break; + } + } + + if (i == ARRAY_SIZE(m_severity_lvls)) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown severity level: %s\r\n", argv[1]); + return; + } + + lvl = (nrf_log_severity_t)i; + first_m_name_idx = 2; + + } + else if (strncmp(argv[0], "disable", 8) == 0) + { + if (argc == 1) + { + all_modules = true; + } + lvl = NRF_LOG_SEVERITY_NONE; + first_m_name_idx = 1; + } + else + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown option: %s\r\n", argv[0]); + return; + } + + if (all_modules) + { + for (i = 0; i < nrf_log_module_cnt_get(); i++) + { + if (module_id_filter_set(backend_id, i, lvl) == false) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, + "Level unavailable for module: %s\r\n", + nrf_log_module_name_get(i, false)); + } + } + } + else + { + for (i = first_m_name_idx; i < argc; i++) + { + uint32_t module_id = 0; + if (module_id_get(argv[i], &module_id) == false) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Unknown module:%s\r\n", argv[i]); + } + else if (module_id_filter_set(backend_id, module_id, lvl) == false) + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, + "Level unavailable for module: %s\r\n", + nrf_log_module_name_get(module_id, false)); + } + else + { + /* empty */ + } + } + } + } +} + + +static void log_self_ctrl(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + log_ctrl(p_cli, p_cli->p_log_backend, argc, argv); +} + + +static void log_backend_ctrl(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + nrf_cli_backend_cmd_execute(p_cli, argc, argv, log_ctrl); +} + +static void module_name_get(size_t idx, nrf_cli_static_entry_t * p_static); + +NRF_CLI_CREATE_DYNAMIC_CMD(m_module_name, module_name_get); + +static void module_name_get(size_t idx, nrf_cli_static_entry_t * p_static) +{ + p_static->handler = NULL; + p_static->p_help = NULL; + p_static->p_subcmd = &m_module_name; + p_static->p_syntax = nrf_log_module_name_get(idx, true); +} + + +static void severity_lvl_get(size_t idx, nrf_cli_static_entry_t * p_static) +{ + p_static->handler = NULL; + p_static->p_help = NULL; + p_static->p_subcmd = &m_module_name; + p_static->p_syntax = (idx < ARRAY_SIZE(m_severity_lvls_sorted)) ? + m_severity_lvls_sorted[idx] : NULL; +} + +NRF_CLI_CREATE_DYNAMIC_CMD(m_severity_lvl, severity_lvl_get); + + +static void log_halt(nrf_cli_t const * p_cli, + nrf_log_backend_t const * p_backend, + size_t argc, + char * * argv) +{ + UNUSED_PARAMETER(argc); + UNUSED_PARAMETER(argv); + + nrf_log_backend_disable(p_backend); +} + + +static void log_backend_halt(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + nrf_cli_backend_cmd_execute(p_cli, argc, argv, log_halt); +} + + +static void log_self_halt(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + log_halt(p_cli, p_cli->p_log_backend, argc, argv); +} + + +static void log_go(nrf_cli_t const * p_cli, + nrf_log_backend_t const * p_backend, + size_t argc, + char * * argv) +{ + UNUSED_PARAMETER(argc); + UNUSED_PARAMETER(argv); + + nrf_log_backend_enable(p_backend); +} + + +static void log_backend_go(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + nrf_cli_backend_cmd_execute(p_cli, argc, argv, log_go); +} + + +static void log_self_go(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + log_go(p_cli, p_cli->p_log_backend, argc, argv); +} + + +static void log_cmd_backends_list(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + if (nrf_cli_help_requested(p_cli)) + { + nrf_cli_help_print(p_cli, NULL, 0); + return; + } + size_t num_of_backends; + + num_of_backends = NRF_SECTION_ITEM_COUNT(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t); + for (size_t i = 0; i < num_of_backends; i++) + { + nrf_log_backend_t const * p_backend = + NRF_SECTION_ITEM_GET(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t, i); + + if (p_backend->p_cb->id == NRF_LOG_BACKEND_INVALID_ID) + { + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, + "%s\r\n" + "\t- Status: deactivated\r\n\r\n", + p_backend->p_name); + } + else + { + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, + "%s\r\n" + "\t- Status: %s\r\n" + "\t- ID: %d\r\n\r\n", + p_backend->p_name, + p_backend->p_cb->enabled ? "enabled" : "disabled", + p_backend->p_cb->id); + } + } +} + + +NRF_CLI_CREATE_STATIC_SUBCMD_SET(m_sub_log_backend) +{ + NRF_CLI_CMD(disable, &m_module_name, + "'log disable .. ' disables logs in specified " + "modules (all if no modules specified).", + log_backend_ctrl), + NRF_CLI_CMD(enable, &m_severity_lvl, + "'log enable ... ' enables logs up to given level in " + "specified modules (all if no modules specified).", + log_backend_ctrl), + NRF_CLI_CMD(go, NULL, "Resume logging", log_backend_go), + NRF_CLI_CMD(halt, NULL, "Halt logging", log_backend_halt), + NRF_CLI_CMD(status, NULL, "Logger status", log_backend_status), + NRF_CLI_SUBCMD_SET_END +}; + +static void backend_name_get(size_t idx, nrf_cli_static_entry_t * p_static) +{ + p_static->handler = NULL; + p_static->p_help = NULL; + p_static->p_subcmd = &m_sub_log_backend; + p_static->p_syntax = NULL; + + nrf_log_backend_t const * p_backend; + size_t active_idx = 0; + uint32_t i; + + for (i = 0; i < NRF_SECTION_ITEM_COUNT(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t); i++) + { + p_backend = NRF_SECTION_ITEM_GET(NRF_LOG_BACKEND_SECTION_NAME, nrf_log_backend_t, i); + if (p_backend->p_cb->id != NRF_LOG_BACKEND_INVALID_ID) + { + if (idx == active_idx) + { + p_static->p_syntax = p_backend->p_name; + break; + } + else + { + active_idx++; + } + } + } +} + +NRF_CLI_CREATE_DYNAMIC_CMD(m_backend_name_dynamic, backend_name_get); + +static void log_config_load_cmd(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + UNUSED_PARAMETER(argc); + UNUSED_PARAMETER(argv); + + if (nrf_cli_help_requested(p_cli)) + { + nrf_cli_help_print(p_cli, NULL, 0); + return; + } + +#if LOG_CONFIG_LOAD_STORE_ENABLED + if (nrf_log_config_load() == NRF_SUCCESS) + { + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "Configuration loaded.\r\n"); + } + else + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Failed to load the configuration.\r\n"); + } +#else + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Not supported.\r\n"); +#endif +} + +static void log_config_store_cmd(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + UNUSED_PARAMETER(argc); + UNUSED_PARAMETER(argv); + + if (nrf_cli_help_requested(p_cli)) + { + nrf_cli_help_print(p_cli, NULL, 0); + return; + } + +#if LOG_CONFIG_LOAD_STORE_ENABLED + if (nrf_log_config_store() == NRF_SUCCESS) + { + nrf_cli_fprintf(p_cli, NRF_CLI_NORMAL, "Configuration stored.\r\n"); + } + else + { + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Failed to store the configuration.\r\n"); + } +#else + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "Not supported.\r\n"); +#endif +} + +NRF_CLI_CREATE_STATIC_SUBCMD_SET(m_sub_log_config) +{ + NRF_CLI_CMD(load, NULL, "Load configuration stored in non-volatile memory.", log_config_load_cmd), + NRF_CLI_CMD(store, NULL, "Store current configuration in non-volatile memory.", log_config_store_cmd), + NRF_CLI_SUBCMD_SET_END +}; + +NRF_CLI_CREATE_STATIC_SUBCMD_SET(m_sub_log_stat) +{ + NRF_CLI_CMD(backend, &m_backend_name_dynamic, "Logger backends commands.", NULL), + NRF_CLI_CMD(config, &m_sub_log_config, "Manage logger configuration", NULL), + NRF_CLI_CMD(disable, &m_module_name, + "'log disable .. ' disables logs in specified " + "modules (all if no modules specified).", + log_self_ctrl), + NRF_CLI_CMD(enable, &m_severity_lvl, + "'log enable ... ' enables logs up to given level in " + "specified modules (all if no modules specified).", + log_self_ctrl), + NRF_CLI_CMD(go, NULL, "Resume logging", log_self_go), + NRF_CLI_CMD(halt, NULL, "Halt logging", log_self_halt), + NRF_CLI_CMD(list_backends, NULL, "Lists logger backends.", log_cmd_backends_list), + NRF_CLI_CMD(status, NULL, "Logger status", log_self_status), + NRF_CLI_SUBCMD_SET_END +}; + +static void log_cmd(nrf_cli_t const * p_cli, size_t argc, char **argv) +{ + if ((argc == 1) || nrf_cli_help_requested(p_cli)) + { + nrf_cli_help_print(p_cli, NULL, 0); + return; + } + + nrf_cli_fprintf(p_cli, NRF_CLI_ERROR, "%s:%s%s\r\n", argv[0], " unknown parameter: ", argv[1]); +} + +NRF_CLI_CMD_REGISTER(log, &m_sub_log_stat, "Commands for controlling logger", log_cmd); + +#endif //NRF_LOG_CLI_CMDS + +#endif // NRF_MODULE_ENABLED(NRF_LOG) diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_internal.h b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_internal.h new file mode 100644 index 0000000..d71680b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_internal.h @@ -0,0 +1,516 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_LOG_INTERNAL_H__ +#define NRF_LOG_INTERNAL_H__ +#include "sdk_common.h" +#include "nrf.h" +#include "nrf_error.h" +#include "app_util.h" +#include +#include +#include "nrf_log_instance.h" +#include "nrf_log_types.h" + +#ifndef NRF_LOG_ERROR_COLOR + #define NRF_LOG_ERROR_COLOR NRF_LOG_COLOR_DEFAULT +#endif + +#ifndef NRF_LOG_WARNING_COLOR + #define NRF_LOG_WARNING_COLOR NRF_LOG_COLOR_DEFAULT +#endif + +#ifndef NRF_LOG_INFO_COLOR + #define NRF_LOG_INFO_COLOR NRF_LOG_COLOR_DEFAULT +#endif + +#ifndef NRF_LOG_DEBUG_COLOR + #define NRF_LOG_DEBUG_COLOR NRF_LOG_COLOR_DEFAULT +#endif + + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 0 +#endif + +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif + +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif + +#ifndef NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_FILTERS_ENABLED 0 +#endif + +#ifndef NRF_LOG_MODULE_NAME + #define NRF_LOG_MODULE_NAME app +#endif + +#define NRF_LOG_LEVEL_BITS 3 +#define NRF_LOG_LEVEL_MASK ((1UL << NRF_LOG_LEVEL_BITS) - 1) +#define NRF_LOG_MODULE_ID_BITS 16 +#define NRF_LOG_MODULE_ID_POS 16 + + +#define NRF_LOG_MAX_NUM_OF_ARGS 6 + + +#if NRF_LOG_FILTERS_ENABLED && NRF_LOG_ENABLED + #define NRF_LOG_FILTER NRF_LOG_ITEM_DATA_DYNAMIC(NRF_LOG_MODULE_NAME).filter + #define NRF_LOG_INST_FILTER(p_inst) (p_inst)->filter +#else + #undef NRF_LOG_FILTER + #define NRF_LOG_FILTER NRF_LOG_SEVERITY_DEBUG + #define NRF_LOG_INST_FILTER(p_inst) NRF_LOG_SEVERITY_DEBUG +#endif + +/** + * @brief Macro for calculating module id based on address and section start address + */ +#define NRF_LOG_MODULE_ID_GET_CONST(addr) (((uint32_t)(addr) - \ + (uint32_t)NRF_SECTION_START_ADDR(log_const_data)) / \ + sizeof(nrf_log_module_const_data_t)) +/** + * @brief Macro for calculating module id based on address and section start address + */ +#define NRF_LOG_MODULE_ID_GET_DYNAMIC(addr) (((uint32_t)(addr) - \ + (uint32_t)NRF_SECTION_START_ADDR(log_dynamic_data)) / \ + sizeof(nrf_log_module_dynamic_data_t)) + + +#if NRF_LOG_ENABLED +#define NRF_LOG_MODULE_ID NRF_LOG_MODULE_ID_GET_CONST(&NRF_LOG_ITEM_DATA_CONST(NRF_LOG_MODULE_NAME)) +#if NRF_LOG_FILTERS_ENABLED +#define NRF_LOG_INST_ID(p_inst) NRF_LOG_MODULE_ID_GET_DYNAMIC(p_inst) +#else +#define NRF_LOG_INST_ID(p_inst) NRF_LOG_MODULE_ID +#endif +#else +#define NRF_LOG_MODULE_ID 0 +#define NRF_LOG_INST_ID(p_inst) 0 +#endif + + +#define LOG_INTERNAL_X(N, ...) CONCAT_2(LOG_INTERNAL_, N) (__VA_ARGS__) +#define LOG_INTERNAL(type, ...) LOG_INTERNAL_X(NUM_VA_ARGS_LESS_1( \ + __VA_ARGS__), type, __VA_ARGS__) +#if NRF_LOG_ENABLED +#define NRF_LOG_INTERNAL_LOG_PUSH(_str) nrf_log_push(_str) +#define LOG_INTERNAL_0(type, str) \ + nrf_log_frontend_std_0(type, str) +#define LOG_INTERNAL_1(type, str, arg0) \ + /*lint -save -e571*/nrf_log_frontend_std_1(type, str, (uint32_t)(arg0))/*lint -restore*/ +#define LOG_INTERNAL_2(type, str, arg0, arg1) \ + /*lint -save -e571*/nrf_log_frontend_std_2(type, str, (uint32_t)(arg0), \ + (uint32_t)(arg1))/*lint -restore*/ +#define LOG_INTERNAL_3(type, str, arg0, arg1, arg2) \ + /*lint -save -e571*/nrf_log_frontend_std_3(type, str, (uint32_t)(arg0), \ + (uint32_t)(arg1), (uint32_t)(arg2))/*lint -restore*/ +#define LOG_INTERNAL_4(type, str, arg0, arg1, arg2, arg3) \ + /*lint -save -e571*/nrf_log_frontend_std_4(type, str, (uint32_t)(arg0), \ + (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3))/*lint -restore*/ +#define LOG_INTERNAL_5(type, str, arg0, arg1, arg2, arg3, arg4) \ + /*lint -save -e571*/nrf_log_frontend_std_5(type, str, (uint32_t)(arg0), \ + (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3), (uint32_t)(arg4))/*lint -restore*/ +#define LOG_INTERNAL_6(type, str, arg0, arg1, arg2, arg3, arg4, arg5) \ + /*lint -save -e571*/nrf_log_frontend_std_6(type, str, (uint32_t)(arg0), \ + (uint32_t)(arg1), (uint32_t)(arg2), (uint32_t)(arg3), (uint32_t)(arg4), (uint32_t)(arg5))/*lint -restore*/ + + +#else //NRF_LOG_ENABLED +#define NRF_LOG_INTERNAL_LOG_PUSH(_str) (void)(_str) +#define LOG_INTERNAL_0(_type, _str) \ + (void)(_type); (void)(_str) +#define LOG_INTERNAL_1(_type, _str, _arg0) \ + (void)(_type); (void)(_str); (void)(_arg0) +#define LOG_INTERNAL_2(_type, _str, _arg0, _arg1) \ + (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1) +#define LOG_INTERNAL_3(_type, _str, _arg0, _arg1, _arg2) \ + (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2) +#define LOG_INTERNAL_4(_type, _str, _arg0, _arg1, _arg2, _arg3) \ + (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3) +#define LOG_INTERNAL_5(_type, _str, _arg0, _arg1, _arg2, _arg3, _arg4) \ + (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3); (void)(_arg4) +#define LOG_INTERNAL_6(_type, _str, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5) \ + (void)(_type); (void)(_str); (void)(_arg0); (void)(_arg1); (void)(_arg2); (void)(_arg3); (void)(_arg4); (void)(_arg5) +#endif //NRF_LOG_ENABLED + +#define LOG_SEVERITY_MOD_ID(severity) ((severity) | NRF_LOG_MODULE_ID << NRF_LOG_MODULE_ID_POS) +#define LOG_SEVERITY_INST_ID(severity,p_inst) ((severity) | NRF_LOG_INST_ID(p_inst) << NRF_LOG_MODULE_ID_POS) + +#if NRF_LOG_ENABLED +#define LOG_HEXDUMP(_severity, _p_data, _length) \ + nrf_log_frontend_hexdump((_severity), (_p_data), (_length)) +#else +#define LOG_HEXDUMP(_severity, _p_data, _length) \ + (void)(_severity); (void)(_p_data); (void)_length +#endif + +#define NRF_LOG_INTERNAL_INST(level, level_id, p_inst, ...) \ + if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ + (level <= NRF_LOG_DEFAULT_LEVEL)) \ + { \ + if (NRF_LOG_INST_FILTER(p_inst) >= level) \ + { \ + LOG_INTERNAL(LOG_SEVERITY_INST_ID(level_id, p_inst), __VA_ARGS__); \ + } \ + } + +#define NRF_LOG_INTERNAL_MODULE(level, level_id, ...) \ + if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ + (level <= NRF_LOG_DEFAULT_LEVEL)) \ + { \ + if (NRF_LOG_FILTER >= level) \ + { \ + LOG_INTERNAL(LOG_SEVERITY_MOD_ID(level_id), __VA_ARGS__); \ + } \ + } + +#define NRF_LOG_INTERNAL_HEXDUMP_INST(level, level_id, p_inst, p_data, len) \ + if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ + (level <= NRF_LOG_DEFAULT_LEVEL)) \ + { \ + if (NRF_LOG_INST_FILTER(p_inst) >= level) \ + { \ + LOG_HEXDUMP(LOG_SEVERITY_INST_ID(level_id, p_inst), \ + (p_data), (len)); \ + } \ + } + +#define NRF_LOG_INTERNAL_HEXDUMP_MODULE(level, level_id, p_data, len) \ + if (NRF_LOG_ENABLED && (NRF_LOG_LEVEL >= level) && \ + (level <= NRF_LOG_DEFAULT_LEVEL)) \ + { \ + if (NRF_LOG_FILTER >= level) \ + { \ + LOG_HEXDUMP(LOG_SEVERITY_MOD_ID(level_id), \ + (p_data), (len)); \ + } \ + } + +#define NRF_LOG_INTERNAL_INST_ERROR(p_inst, ...) \ + NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_inst, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_ERROR(...) \ + NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR,__VA_ARGS__) + +#define NRF_LOG_INTERNAL_HEXDUMP_INST_ERROR(p_inst, p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_inst, p_data, len) + +#define NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_ERROR, NRF_LOG_SEVERITY_ERROR, p_data, len) + +#define NRF_LOG_INTERNAL_INST_WARNING(p_inst, ...) \ + NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_inst, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_WARNING(...) \ + NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING,__VA_ARGS__) + +#define NRF_LOG_INTERNAL_HEXDUMP_INST_WARNING(p_inst, p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_inst, p_data, len) + +#define NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_WARNING, NRF_LOG_SEVERITY_WARNING, p_data, len) + +#define NRF_LOG_INTERNAL_INST_INFO(p_inst, ...) \ + NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_inst, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_INFO(...) \ + NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_HEXDUMP_INST_INFO(p_inst, p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_inst, p_data, len) + +#define NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO, p_data, len) + +#define NRF_LOG_INTERNAL_RAW_INFO(...) \ + NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO_RAW, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_INFO, NRF_LOG_SEVERITY_INFO_RAW, p_data, len) + +#define NRF_LOG_INTERNAL_INST_DEBUG(p_inst, ...) \ + NRF_LOG_INTERNAL_INST(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_inst, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_DEBUG(...) \ + NRF_LOG_INTERNAL_MODULE(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, __VA_ARGS__) + +#define NRF_LOG_INTERNAL_HEXDUMP_INST_DEBUG(p_inst, p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_INST(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_inst, p_data, len) + +#define NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len) \ + NRF_LOG_INTERNAL_HEXDUMP_MODULE(NRF_LOG_SEVERITY_DEBUG, NRF_LOG_SEVERITY_DEBUG, p_data, len) + + +#if NRF_LOG_ENABLED + +#ifdef UNIT_TEST +#define COMPILED_LOG_LEVEL 4 +#else +#define COMPILED_LOG_LEVEL NRF_LOG_LEVEL +#endif + + +#define NRF_LOG_INTERNAL_MODULE_REGISTER() \ + NRF_LOG_INTERNAL_ITEM_REGISTER(NRF_LOG_MODULE_NAME, \ + STRINGIFY(NRF_LOG_MODULE_NAME), \ + NRF_LOG_INFO_COLOR, \ + NRF_LOG_DEBUG_COLOR, \ + NRF_LOG_INITIAL_LEVEL, \ + COMPILED_LOG_LEVEL) + +#else +#define NRF_LOG_INTERNAL_MODULE_REGISTER() /*lint -save -e19*/ /*lint -restore*/ +#endif + +extern nrf_log_module_dynamic_data_t NRF_LOG_ITEM_DATA_DYNAMIC(NRF_LOG_MODULE_NAME); +extern _CONST nrf_log_module_const_data_t NRF_LOG_ITEM_DATA_CONST(NRF_LOG_MODULE_NAME); + +/** + * Set of macros for encoding and decoding header for log entries. + * There are 2 types of entries: + * 1. Standard entry (STD) + * An entry consists of header, pointer to string and values. Header contains + * severity leveland determines number of arguments and thus size of the entry. + * Since flash address space starts from 0x00000000 and is limited to kB rather + * than MB 22 bits are used to store the address (4MB). It is used that way to + * save one RAM memory. + * + * -------------------------------- + * |TYPE|SEVERITY|NARGS| P_STR | + * |------------------------------| + * | Module_ID (optional) | + * |------------------------------| + * | TIMESTAMP (optional) | + * |------------------------------| + * | ARG0 | + * |------------------------------| + * | .... | + * |------------------------------| + * | ARG(nargs-1) | + * -------------------------------- + * + * 2. Hexdump entry (HEXDUMP) is used for dumping raw data. An entry consists of + * header, optional timestamp, pointer to string and data. A header contains + * length (10bit) and offset which is updated after backend processes part of + * data. + * + * -------------------------------- + * |TYPE|SEVERITY|NARGS|OFFSET|LEN| + * |------------------------------| + * | Module_ID (optional) | + * |------------------------------| + * | TIMESTAMP (optional) | + * |------------------------------| + * | P_STR | + * |------------------------------| + * | data | + * |------------------------------| + * | data | dummy | + * -------------------------------- + * + */ + +#define STD_ADDR_MASK ((uint32_t)(1U << 22) - 1U) +#define HEADER_TYPE_STD 1U +#define HEADER_TYPE_HEXDUMP 2U +#define HEADER_TYPE_INVALID 3U + +typedef struct +{ + uint32_t type : 2; + uint32_t in_progress: 1; + uint32_t data : 29; +} nrf_log_generic_header_t; + +typedef struct +{ + uint32_t type : 2; + uint32_t in_progress: 1; + uint32_t severity : 3; + uint32_t nargs : 4; + uint32_t addr : 22; +} nrf_log_std_header_t; + +typedef struct +{ + uint32_t type : 2; + uint32_t in_progress: 1; + uint32_t severity : 3; + uint32_t offset : 10; + uint32_t reserved : 6; + uint32_t len : 10; +} nrf_log_hexdump_header_t; + +typedef union +{ + nrf_log_generic_header_t generic; + nrf_log_std_header_t std; + nrf_log_hexdump_header_t hexdump; + uint32_t raw; +} nrf_log_main_header_t; + +typedef struct +{ + nrf_log_main_header_t base; + uint16_t module_id; + uint16_t dropped; + uint32_t timestamp; +} nrf_log_header_t; + +#define HEADER_SIZE (sizeof(nrf_log_header_t)/sizeof(uint32_t) - \ + (NRF_LOG_USES_TIMESTAMP ? 0 : 1)) + +/** + * @brief A function for logging raw string. + * + * @param severity_mid Severity. + * @param p_str A pointer to a string. + */ +void nrf_log_frontend_std_0(uint32_t severity_mid, char const * const p_str); + +/** + * @brief A function for logging a formatted string with one argument. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0 An argument. + */ +void nrf_log_frontend_std_1(uint32_t severity_mid, + char const * const p_str, + uint32_t val0); + +/** + * @brief A function for logging a formatted string with 2 arguments. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0, val1 Arguments for formatting string. + */ +void nrf_log_frontend_std_2(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1); + +/** + * @brief A function for logging a formatted string with 3 arguments. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0, val1, val2 Arguments for formatting string. + */ +void nrf_log_frontend_std_3(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2); + +/** + * @brief A function for logging a formatted string with 4 arguments. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0, val1, val2, val3 Arguments for formatting string. + */ +void nrf_log_frontend_std_4(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3); + +/** + * @brief A function for logging a formatted string with 5 arguments. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0, val1, val2, val3, val4 Arguments for formatting string. + */ +void nrf_log_frontend_std_5(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3, + uint32_t val4); + +/** + * @brief A function for logging a formatted string with 6 arguments. + * + * @param severity_mid Severity. + * @param p_str A pointer to a formatted string. + * @param val0, val1, val2, val3, val4, val5 Arguments for formatting string. + */ +void nrf_log_frontend_std_6(uint32_t severity_mid, + char const * const p_str, + uint32_t val0, + uint32_t val1, + uint32_t val2, + uint32_t val3, + uint32_t val4, + uint32_t val5); + +/** + * @brief A function for logging raw data. + * + * @param severity_mid Severity. + * @param p_str A pointer to a string which is prefixing the data. + * @param p_data A pointer to data to be dumped. + * @param length Length of data (in bytes). + * + */ +void nrf_log_frontend_hexdump(uint32_t severity_mid, + const void * const p_data, + uint16_t length); + +/** + * @brief A function for reading a byte from log backend. + * + * @return Byte. + */ +uint8_t nrf_log_getchar(void); +#endif // NRF_LOG_INTERNAL_H__ diff --git a/HAL_Driver/sdk/components/libraries/log/src/nrf_log_str_formatter.c b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_str_formatter.c new file mode 100644 index 0000000..5d903b8 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/log/src/nrf_log_str_formatter.c @@ -0,0 +1,258 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_LOG) +#include "nrf_log_str_formatter.h" +#include "nrf_log_internal.h" +#include "nrf_log_ctrl.h" +#include "nrf_fprintf.h" +#include + +#define NRF_LOG_COLOR_CODE_DEFAULT "\x1B[0m" +#define NRF_LOG_COLOR_CODE_BLACK "\x1B[1;30m" +#define NRF_LOG_COLOR_CODE_RED "\x1B[1;31m" +#define NRF_LOG_COLOR_CODE_GREEN "\x1B[1;32m" +#define NRF_LOG_COLOR_CODE_YELLOW "\x1B[1;33m" +#define NRF_LOG_COLOR_CODE_BLUE "\x1B[1;34m" +#define NRF_LOG_COLOR_CODE_MAGENTA "\x1B[1;35m" +#define NRF_LOG_COLOR_CODE_CYAN "\x1B[1;36m" +#define NRF_LOG_COLOR_CODE_WHITE "\x1B[1;37m" + +#define NRF_LOG_CHAR_CODE_MAX 0x7E + +static const char * severity_names[] = { + NULL, + "error", + "warning", + "info", + "debug" +}; + +static const char * m_colors[] = { + NRF_LOG_COLOR_CODE_DEFAULT, + NRF_LOG_COLOR_CODE_BLACK, + NRF_LOG_COLOR_CODE_RED, + NRF_LOG_COLOR_CODE_GREEN, + NRF_LOG_COLOR_CODE_YELLOW, + NRF_LOG_COLOR_CODE_BLUE, + NRF_LOG_COLOR_CODE_MAGENTA, + NRF_LOG_COLOR_CODE_CYAN, + NRF_LOG_COLOR_CODE_WHITE, +}; + +static uint32_t m_freq; +static uint32_t m_timestamp_div; + +static void timestamp_print(nrf_fprintf_ctx_t * p_ctx, uint32_t timestamp) +{ + if (NRF_LOG_USES_TIMESTAMP) + { + if (NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED) + { + timestamp /= m_timestamp_div; + uint32_t seconds = timestamp/m_freq; + uint32_t hours = seconds/3600; + seconds -= hours * 3600; + uint32_t mins = seconds/60; + seconds -= mins * 60; + + uint32_t reminder = timestamp % m_freq; + uint32_t ms = (reminder * 1000)/m_freq; + uint32_t us = (1000*(1000*reminder - (ms * m_freq)))/m_freq; + + nrf_fprintf(p_ctx, "[%02d:%02d:%02d.%03d,%03d] ", hours, mins, seconds, ms, us); + } + else + { + nrf_fprintf(p_ctx, "[%08lu] ", timestamp); + } + } +} +static void prefix_process(nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx) +{ + if (p_params->dropped) + { + nrf_fprintf(p_ctx, + "%sLogs dropped (%d)%s\r\n", + NRF_LOG_COLOR_CODE_RED, + p_params->dropped, + NRF_LOG_COLOR_CODE_DEFAULT); + } + + if (!(p_params->severity == NRF_LOG_SEVERITY_INFO_RAW)) + { + if (p_params->use_colors) + { + nrf_fprintf(p_ctx, "%s", + m_colors[nrf_log_color_id_get( p_params->module_id, p_params->severity)]); + } + timestamp_print(p_ctx, p_params->timestamp); + + nrf_fprintf(p_ctx, "<%s> %s: ", + severity_names[p_params->severity], nrf_log_module_name_get(p_params->module_id, false)); + } +} + +static void postfix_process(nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx, + bool newline) +{ + if (!(p_params->severity == NRF_LOG_SEVERITY_INFO_RAW)) + { + if (p_params->use_colors) + { + nrf_fprintf(p_ctx, "%s", m_colors[0]); + } + nrf_fprintf(p_ctx, "\r\n"); + } + else if (newline) + { + nrf_fprintf(p_ctx, "\r\n"); + } + nrf_fprintf_buffer_flush(p_ctx); +} + +void nrf_log_std_entry_process(char const * p_str, + uint32_t const * p_args, + uint32_t nargs, + nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx) +{ + bool auto_flush = p_ctx->auto_flush; + p_ctx->auto_flush = false; + + prefix_process(p_params, p_ctx); + + switch (nargs) + { + case 0: + nrf_fprintf(p_ctx, p_str); + break; + case 1: + nrf_fprintf(p_ctx, p_str, p_args[0]); + break; + case 2: + nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1]); + break; + case 3: + nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2]); + break; + case 4: + nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3]); + break; + case 5: + nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3], p_args[4]); + break; + case 6: + nrf_fprintf(p_ctx, p_str, p_args[0], p_args[1], p_args[2], p_args[3], p_args[4], p_args[5]); + break; + + default: + break; + } + + postfix_process(p_params, p_ctx, false); + p_ctx->auto_flush = auto_flush; +} + +#define HEXDUMP_BYTES_IN_LINE 8 + +void nrf_log_hexdump_entry_process(uint8_t * p_data, + uint32_t data_len, + nrf_log_str_formatter_entry_params_t * p_params, + nrf_fprintf_ctx_t * p_ctx) +{ + if (data_len > HEXDUMP_BYTES_IN_LINE) + { + return; + } + bool auto_flush = p_ctx->auto_flush; + p_ctx->auto_flush = false; + + prefix_process(p_params, p_ctx); + + uint32_t i; + + for (i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) + { + if (i < data_len) + { + nrf_fprintf(p_ctx, " %02x", p_data[i]); + } + else + { + nrf_fprintf(p_ctx, " "); + } + } + nrf_fprintf(p_ctx, "|"); + + for (i = 0; i < HEXDUMP_BYTES_IN_LINE; i++) + { + if (i < data_len) + { + char c = (char)p_data[i]; + nrf_fprintf(p_ctx, "%c", ((c <= NRF_LOG_CHAR_CODE_MAX) && isprint((int)c)) ? c :'.'); + } + else + { + nrf_fprintf(p_ctx, " "); + } + } + + postfix_process(p_params, p_ctx, true); + + p_ctx->auto_flush = auto_flush; +} + +void nrf_log_str_formatter_timestamp_freq_set(uint32_t freq) +{ + m_timestamp_div = 1; + /* There is no point to have frequency higher than 1MHz (ns are not printed) and too high + * frequency leads to overflows in calculations. + */ + while (freq > 1000000) + { + freq /= 2; + m_timestamp_div *= 2; + } + m_freq = freq; +} +#endif //NRF_LOG_ENABLED diff --git a/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.c b/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.c new file mode 100644 index 0000000..161f1ab --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.c @@ -0,0 +1,258 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nrf_memobj.h" +#include "nrf_atomic.h" +#include "nrf_assert.h" + +typedef struct memobj_elem_s memobj_elem_t; + +/** @brief Standard chunk header. */ +typedef struct +{ + memobj_elem_t * p_next; ///< Pointer to the next element. +} memobj_header_t; + +/** @brief Head header extension fields. */ +typedef struct +{ + uint8_t user_cnt; ///< User counter (see @ref nrf_memobj_get and @ref nrf_memobj_put). + uint8_t chunk_cnt; ///< Number of chunks in the object. + uint16_t chunk_size; ///< Single chunk size +} memobj_head_header_fields_t; + +/** @brief Head header extension. */ +typedef struct +{ + union + { + nrf_atomic_u32_t atomic_user_cnt; + memobj_head_header_fields_t fields; + } data; +} memobj_head_header_t; + +/** @brief Head chunk structure. */ +typedef struct +{ + memobj_header_t header; ///< Standard header. + memobj_head_header_t head_header; ///< Head-specific header part. + uint8_t data[1]; ///< Data. +} memobj_head_t; + +STATIC_ASSERT(sizeof(memobj_header_t) == NRF_MEMOBJ_STD_HEADER_SIZE); + +/** @brief Standard chunk structure. */ +struct memobj_elem_s +{ + memobj_header_t header; ///< Standard header. + uint8_t data[1]; ///< Data. +}; + +ret_code_t nrf_memobj_pool_init(nrf_memobj_pool_t const * p_pool) +{ + return nrf_balloc_init((nrf_balloc_t const *)p_pool); +} + +nrf_memobj_t * nrf_memobj_alloc(nrf_memobj_pool_t const * p_pool, + size_t size) +{ + uint32_t bsize = (uint32_t)NRF_BALLOC_ELEMENT_SIZE((nrf_balloc_t const *)p_pool) - sizeof(memobj_header_t); + uint8_t num_of_chunks = (uint8_t)CEIL_DIV(size + sizeof(memobj_head_header_t), bsize); + + memobj_head_t * p_head = nrf_balloc_alloc((nrf_balloc_t const *)p_pool); + if (p_head == NULL) + { + return NULL; + } + p_head->head_header.data.fields.user_cnt = 0; + p_head->head_header.data.fields.chunk_cnt = 1; + p_head->head_header.data.fields.chunk_size = bsize; + + memobj_header_t * p_prev = (memobj_header_t *)p_head; + memobj_header_t * p_curr; + uint32_t i; + uint32_t chunk_less1 = (uint32_t)num_of_chunks - 1; + + p_prev->p_next = (memobj_elem_t *)p_pool; + for (i = 0; i < chunk_less1; i++) + { + p_curr = (memobj_header_t *)nrf_balloc_alloc((nrf_balloc_t const *)p_pool); + if (p_curr) + { + (p_head->head_header.data.fields.chunk_cnt)++; + p_prev->p_next = (memobj_elem_t *)p_curr; + p_curr->p_next = (memobj_elem_t *)p_pool; + p_prev = p_curr; + } + else + { + //Could not allocate all requested buffers + nrf_memobj_free((nrf_memobj_t *)p_head); + return NULL; + } + } + return (nrf_memobj_t *)p_head; +} + +void nrf_memobj_free(nrf_memobj_t * p_obj) +{ + memobj_head_t * p_head = (memobj_head_t *)p_obj; + uint8_t chunk_cnt = p_head->head_header.data.fields.chunk_cnt; + uint32_t i; + memobj_header_t * p_curr = (memobj_header_t *)p_obj; + memobj_header_t * p_next; + uint32_t chunk_less1 = (uint32_t)chunk_cnt - 1; + + for (i = 0; i < chunk_less1; i++) + { + p_curr = (memobj_header_t *)p_curr->p_next; + } + nrf_balloc_t const * p_pool2 = (nrf_balloc_t const *)p_curr->p_next; + + p_curr = (memobj_header_t *)p_obj; + for (i = 0; i < chunk_cnt; i++) + { + p_next = (memobj_header_t *)p_curr->p_next; + nrf_balloc_free(p_pool2, p_curr); + p_curr = p_next; + } +} + +void nrf_memobj_get(nrf_memobj_t const * p_obj) +{ + memobj_head_t * p_head = (memobj_head_t *)p_obj; + (void)nrf_atomic_u32_add(&p_head->head_header.data.atomic_user_cnt, 1); +} + +void nrf_memobj_put(nrf_memobj_t * p_obj) +{ + memobj_head_t * p_head = (memobj_head_t *)p_obj; + uint32_t user_cnt = nrf_atomic_u32_sub(&p_head->head_header.data.atomic_user_cnt, 1); + memobj_head_header_fields_t * p_fields = (memobj_head_header_fields_t *)&user_cnt; + if (p_fields->user_cnt == 0) + { + nrf_memobj_free(p_obj); + } +} + +static void memobj_op(nrf_memobj_t * p_obj, + void * p_data, + size_t * p_len, + size_t offset, + bool read) +{ + + ASSERT(p_obj); + + memobj_head_t * p_head = (memobj_head_t *)p_obj; + memobj_elem_t * p_curr_chunk = (memobj_elem_t *)p_obj; + size_t obj_capacity; + size_t chunk_size; + size_t chunk_idx; + size_t chunk_offset; + size_t len; + + obj_capacity = (p_head->head_header.data.fields.chunk_size * + p_head->head_header.data.fields.chunk_cnt) - + sizeof(memobj_head_header_fields_t); + + ASSERT(offset < obj_capacity); + + chunk_size = p_head->head_header.data.fields.chunk_size; + chunk_idx = (offset + sizeof(memobj_head_header_fields_t)) / chunk_size; + chunk_offset = (offset + sizeof(memobj_head_header_fields_t)) % chunk_size; + len = ((*p_len + offset) > obj_capacity) ? obj_capacity - offset : *p_len; + + //Return number of available bytes + *p_len = len; + + //Move to the first chunk to be used + while (chunk_idx > 0) + { + p_curr_chunk = p_curr_chunk->header.p_next; + chunk_idx--; + } + + size_t user_mem_offset = 0; + size_t curr_cpy_size = chunk_size - chunk_offset; + curr_cpy_size = curr_cpy_size > len ? len : curr_cpy_size; + + while (len) + { + void * p_user_mem = &((uint8_t *)p_data)[user_mem_offset]; + void * p_obj_mem = &p_curr_chunk->data[chunk_offset]; + if (read) + { + memcpy(p_user_mem, p_obj_mem, curr_cpy_size); + } + else + { + memcpy(p_obj_mem, p_user_mem, curr_cpy_size); + } + + chunk_offset = 0; + p_curr_chunk = p_curr_chunk->header.p_next; + len -= curr_cpy_size; + user_mem_offset += curr_cpy_size; + curr_cpy_size = (chunk_size > len) ? len : chunk_size; + } +} + +void nrf_memobj_write(nrf_memobj_t * p_obj, + void * p_data, + size_t len, + size_t offset) +{ + + size_t op_len = len; + memobj_op(p_obj, p_data, &op_len, offset, false); + ASSERT(op_len == len); +} + +void nrf_memobj_read(nrf_memobj_t * p_obj, + void * p_data, + size_t len, + size_t offset) +{ + size_t op_len = len; + memobj_op(p_obj, p_data, &op_len, offset, true); + ASSERT(op_len == len); + +} diff --git a/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.h b/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.h new file mode 100644 index 0000000..22cb3be --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/memobj/nrf_memobj.h @@ -0,0 +1,203 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_MEMOBJ_H +#define NRF_MEMOBJ_H + +/** +* @defgroup nrf_memobj Memory Object module +* @{ +* @ingroup app_common +* @brief Functions for controlling a memory object. +*/ +#include +#include +#include "sdk_errors.h" +#include "nrf_balloc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * A memory object can consist of multiple chunks with the same size. Each object has a header part + * and a data part. The first element in a memory object is memory object head which has a special header. + * The remaining objects have a header of the same size. + * +@verbatim + _____________________ _____________________ _____________________ +| | | | | | +|4 B head header | --> |4 B p_next |------->|4 B p_memobj_pool | +|_____________________| | |_____________________| |_____________________| +| | | | | | | +|4 B p_next |--| | | | | +|_____________________| | | .... | | +| | | data | | data | +| | | | | | +| data | | | | | +| | | | | | +|_____________________| |_____________________| |_____________________| + head mid_element last_element +@endverbatim + * + */ +#define NRF_MEMOBJ_STD_HEADER_SIZE sizeof(uint32_t) + +/** + * @brief Macro for creating an nrf_memobj pool. + * + * This macro declares an nrf_balloc object. The element in the pool contains a user-defined data part and + * a memory object header. + * + * @param _name Name of the instance. + * @param _chunk_size Size of a single chunk. + * @param _pool_size Number of chunks in the pool. + */ +#define NRF_MEMOBJ_POOL_DEF(_name, _chunk_size, _pool_size) \ + STATIC_ASSERT((_chunk_size) > sizeof(uint32_t)); \ + NRF_BALLOC_DEF(_name, ((_chunk_size)+NRF_MEMOBJ_STD_HEADER_SIZE), (_pool_size)) + +/** + * @brief Pool of memory objects. + */ +typedef nrf_balloc_t nrf_memobj_pool_t; + +/** + * @brief Memory object handle. + */ +typedef void * nrf_memobj_t; + +/** + * @brief Function for initializing the memobj pool instance. + * + * This function initializes the pool. + * + * @param[in] p_pool Pointer to the memobj pool instance structure. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +ret_code_t nrf_memobj_pool_init(nrf_memobj_pool_t const * p_pool); + +/** + * @brief Function for allocating a memobj with a requested size. + * + * Fixed length elements in the pool are linked together to provide the amount of memory requested by + * the user. If a memory object is successfully allocated, then the users can use the memory. + * However, it is fragmented into multiple objects so it must be accessed through the API: + * @ref nrf_memobj_write and @ref nrf_memobj_read. + * + * @param[in] p_pool Pointer to the memobj pool instance structure. + * @param[in] size Data size of requested object. + * + * @return Pointer to a memory object or NULL if the requested size cannot be allocated. + */ +nrf_memobj_t * nrf_memobj_alloc(nrf_memobj_pool_t const * p_pool, + size_t size); + +/** + * @brief Function for indicating that a memory object is used and cannot be freed. + * + * Memory object can be shared and reused between multiple modules and this mechanism ensures that + * object is freed when no longer used by any module. Memory object has a counter which is incremented + * whenever this function is called. @ref nrf_memobj_put function decrements the counter. + * + * @param[in] p_obj Pointer to memory object. + */ +void nrf_memobj_get(nrf_memobj_t const * p_obj); + + +/** + * @brief Function for indicated that memory object is no longer used by the module and can be freed + * if no other module is using it. + * + * Memory object is returned to the pool if internal counter reaches 0 after decrementing. It means + * that no other module is needing it anymore. + * + * @note Memory object holds pointer to the pool which was used to allocate it so it does not have + * to be provided explicitly to this function. + * + * @param[in] p_obj Pointer to memory object. + */ +void nrf_memobj_put(nrf_memobj_t * p_obj); + + +/** + * @brief Function for forcing freeing of the memory object. + * + * @note This function should be use with caution because it can lead to undefined behavior of the + * modules since modules using the memory object are not aware that it has been freed. + * + * @param[in] p_obj Pointer to memory object. + */ +void nrf_memobj_free(nrf_memobj_t * p_obj); + +/** + * @brief Function for writing data to the memory object. + * + * @param[in] p_obj Pointer to memory object. + * @param[in] p_data Pointer to data to be written to the memory object. + * @param[in] len Amount of data to be written to the memory object. + * @param[in] offset Offset. + */ +void nrf_memobj_write(nrf_memobj_t * p_obj, + void * p_data, + size_t len, + size_t offset); + +/** + * @brief Function for reading data from the memory object. + * + * @param[in] p_obj Pointer to memory object. + * @param[in] p_data Pointer to the destination buffer. + * @param[in] len Amount of data to be read from the memory object. + * @param[in] offset Offset. + */ +void nrf_memobj_read(nrf_memobj_t * p_obj, + void * p_data, + size_t len, + size_t offset); + +#ifdef __cplusplus +} +#endif + +#endif //NRF_MEMOBJ_H + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.c b/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.c new file mode 100644 index 0000000..d9a2e8c --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.c @@ -0,0 +1,237 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "nrf_ringbuf.h" +#include "app_util_platform.h" +#include "nrf_assert.h" + +#define WR_OFFSET 0 +#define RD_OFFSET 1 + +void nrf_ringbuf_init(nrf_ringbuf_t const * p_ringbuf) +{ + p_ringbuf->p_cb->wr_idx = 0; + p_ringbuf->p_cb->rd_idx = 0; + p_ringbuf->p_cb->tmp_rd_idx = 0; + p_ringbuf->p_cb->tmp_wr_idx = 0; + p_ringbuf->p_cb->rd_flag = 0; + p_ringbuf->p_cb->wr_flag = 0; +} + +ret_code_t nrf_ringbuf_alloc(nrf_ringbuf_t const * p_ringbuf, uint8_t * * pp_data, size_t * p_length, bool start) +{ + ASSERT(pp_data); + ASSERT(p_length); + + if (start) + { + if (nrf_atomic_flag_set_fetch(&p_ringbuf->p_cb->wr_flag)) + { + return NRF_ERROR_BUSY; + } + } + + if (p_ringbuf->p_cb->tmp_wr_idx - p_ringbuf->p_cb->rd_idx == p_ringbuf->bufsize_mask + 1) + { + *p_length = 0; + if (start) + { + UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&p_ringbuf->p_cb->wr_flag)); + } + return NRF_SUCCESS; + } + + uint32_t wr_idx = p_ringbuf->p_cb->tmp_wr_idx & p_ringbuf->bufsize_mask; + uint32_t rd_idx = p_ringbuf->p_cb->rd_idx & p_ringbuf->bufsize_mask; + uint32_t available = (wr_idx >= rd_idx) ? p_ringbuf->bufsize_mask + 1 - wr_idx : + p_ringbuf->p_cb->rd_idx - (p_ringbuf->p_cb->tmp_wr_idx - (p_ringbuf->bufsize_mask + 1)); + *p_length = *p_length < available ? *p_length : available; + *pp_data = &p_ringbuf->p_buffer[wr_idx]; + p_ringbuf->p_cb->tmp_wr_idx += *p_length; + + return NRF_SUCCESS; +} + +ret_code_t nrf_ringbuf_put(nrf_ringbuf_t const * p_ringbuf, size_t length) +{ + uint32_t available = p_ringbuf->bufsize_mask + 1 - + (p_ringbuf->p_cb->wr_idx - p_ringbuf->p_cb->rd_idx); + if (length > available) + { + return NRF_ERROR_NO_MEM; + } + + p_ringbuf->p_cb->wr_idx += length; + p_ringbuf->p_cb->tmp_wr_idx = p_ringbuf->p_cb->wr_idx; + if (nrf_atomic_flag_clear_fetch(&p_ringbuf->p_cb->wr_flag) == 0) + { + /* Flag was already cleared. Suggests misuse. */ + return NRF_ERROR_INVALID_STATE; + } + return NRF_SUCCESS; +} + +ret_code_t nrf_ringbuf_cpy_put(nrf_ringbuf_t const * p_ringbuf, + uint8_t const * p_data, + size_t * p_length) +{ + ASSERT(p_data); + ASSERT(p_length); + + if (nrf_atomic_flag_set_fetch(&p_ringbuf->p_cb->wr_flag)) + { + return NRF_ERROR_BUSY; + } + + uint32_t available = p_ringbuf->bufsize_mask + 1 - + (p_ringbuf->p_cb->wr_idx - p_ringbuf->p_cb->rd_idx); + *p_length = available > *p_length ? *p_length : available; + size_t length = *p_length; + uint32_t masked_wr_idx = (p_ringbuf->p_cb->wr_idx & p_ringbuf->bufsize_mask); + uint32_t trail = p_ringbuf->bufsize_mask + 1 - masked_wr_idx; + + if (length > trail) + { + memcpy(&p_ringbuf->p_buffer[masked_wr_idx], p_data, trail); + length -= trail; + masked_wr_idx = 0; + p_data += trail; + } + memcpy(&p_ringbuf->p_buffer[masked_wr_idx], p_data, length); + p_ringbuf->p_cb->wr_idx += *p_length; + + UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&p_ringbuf->p_cb->wr_flag)); + + return NRF_SUCCESS; +} + +ret_code_t nrf_ringbuf_get(nrf_ringbuf_t const * p_ringbuf, uint8_t * * pp_data, size_t * p_length, bool start) +{ + ASSERT(pp_data); + ASSERT(p_length); + + if (start) + { + if (nrf_atomic_flag_set_fetch(&p_ringbuf->p_cb->rd_flag)) + { + return NRF_ERROR_BUSY; + } + } + + uint32_t available = p_ringbuf->p_cb->wr_idx - p_ringbuf->p_cb->tmp_rd_idx; + if (available == 0) + { + *p_length = 0; + if (start) + { + UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&p_ringbuf->p_cb->rd_flag)); + } + return NRF_SUCCESS; + } + + uint32_t masked_tmp_rd_idx = p_ringbuf->p_cb->tmp_rd_idx & p_ringbuf->bufsize_mask; + uint32_t masked_wr_idx = p_ringbuf->p_cb->wr_idx & p_ringbuf->bufsize_mask; + + if ((masked_wr_idx > masked_tmp_rd_idx) && (available < *p_length)) + { + *p_length = available; + } + else if (masked_wr_idx <= masked_tmp_rd_idx) + { + uint32_t trail = p_ringbuf->bufsize_mask + 1 - masked_tmp_rd_idx; + if (*p_length > trail) + { + *p_length = trail; + } + } + *pp_data = &p_ringbuf->p_buffer[masked_tmp_rd_idx]; + p_ringbuf->p_cb->tmp_rd_idx += *p_length; + + return NRF_SUCCESS; +} + +ret_code_t nrf_ringbuf_cpy_get(nrf_ringbuf_t const * p_ringbuf, + uint8_t * p_data, + size_t * p_length) +{ + ASSERT(p_data); + ASSERT(p_length); + + if (nrf_atomic_flag_set_fetch(&p_ringbuf->p_cb->rd_flag)) + { + return NRF_ERROR_BUSY; + } + + uint32_t available = p_ringbuf->p_cb->wr_idx - p_ringbuf->p_cb->rd_idx; + *p_length = available > *p_length ? *p_length : available; + size_t length = *p_length; + uint32_t masked_rd_idx = (p_ringbuf->p_cb->rd_idx & p_ringbuf->bufsize_mask); + uint32_t masked_wr_idx = (p_ringbuf->p_cb->wr_idx & p_ringbuf->bufsize_mask); + uint32_t trail = (masked_wr_idx > masked_rd_idx) ? masked_wr_idx - masked_rd_idx : + p_ringbuf->bufsize_mask + 1 - masked_rd_idx; + + if (length > trail) + { + memcpy(p_data, &p_ringbuf->p_buffer[masked_rd_idx], trail); + length -= trail; + masked_rd_idx = 0; + p_data += trail; + } + memcpy(p_data, &p_ringbuf->p_buffer[masked_rd_idx], length); + p_ringbuf->p_cb->rd_idx += *p_length; + + UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&p_ringbuf->p_cb->rd_flag)); + + return NRF_SUCCESS; +} + +ret_code_t nrf_ringbuf_free(nrf_ringbuf_t const * p_ringbuf, size_t length) +{ + uint32_t available = (p_ringbuf->p_cb->wr_idx - p_ringbuf->p_cb->rd_idx); + if (length > available) + { + return NRF_ERROR_NO_MEM; + } + + p_ringbuf->p_cb->rd_idx += length; + p_ringbuf->p_cb->tmp_rd_idx = p_ringbuf->p_cb->rd_idx; + UNUSED_RETURN_VALUE(nrf_atomic_flag_clear(&p_ringbuf->p_cb->rd_flag)); + + return NRF_SUCCESS; +} diff --git a/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.h b/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.h new file mode 100644 index 0000000..2a5c814 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/ringbuf/nrf_ringbuf.h @@ -0,0 +1,206 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_RINGBUF_H +#define NRF_RINGBUF_H + +/** +* @defgroup nrf_ringbuf Ring buffer +* @{ +* @ingroup app_common +* @brief Functions for controlling the ring buffer. +*/ + +#include +#include "nrf_atomic.h" +#include "sdk_errors.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @brief Ring buffer instance control block. + * */ +typedef struct +{ + nrf_atomic_flag_t wr_flag; //!< Protection flag. + nrf_atomic_flag_t rd_flag; //!< Protection flag. + uint32_t wr_idx; //!< Write index (updated when putting). + uint32_t tmp_wr_idx; //!< Temporary write index (updated when allocating). + uint32_t rd_idx; //!< Read index (updated when freeing). + uint32_t tmp_rd_idx; //!< Temporary read index (updated when getting). +} nrf_ringbuf_cb_t; + +/** + * @brief Ring buffer instance structure. + * */ +typedef struct +{ + uint8_t * p_buffer; //!< Pointer to the memory used by the ring buffer. + uint32_t bufsize_mask; //!< Buffer size mask (buffer size must be a power of 2). + nrf_ringbuf_cb_t * p_cb; //!< Pointer to the instance control block. +} nrf_ringbuf_t; + +/** + * @brief Macro for defining a ring buffer instance. + * + * @param _name Instance name. + * @param _size Size of the ring buffer (must be a power of 2). + * */ +#define NRF_RINGBUF_DEF(_name, _size) \ + STATIC_ASSERT(IS_POWER_OF_TWO(_size)); \ + static uint8_t CONCAT_2(_name,_buf)[_size]; \ + static nrf_ringbuf_cb_t CONCAT_2(_name,_cb); \ + static const nrf_ringbuf_t _name = { \ + .p_buffer = CONCAT_2(_name,_buf), \ + .bufsize_mask = _size - 1, \ + .p_cb = &CONCAT_2(_name,_cb), \ + } + +/** + * @brief Function for initializing a ring buffer instance. + * + * @param p_ringbuf Pointer to the ring buffer instance. + * + * */ +void nrf_ringbuf_init(nrf_ringbuf_t const * p_ringbuf); + +/** + * @brief Function for allocating memory from a ring buffer. + * + * This function attempts to allocate the amount of memory requested by the user, or a smaller amount if + * the requested amount is not available. If a start flag is set, then exclusive access to allocation + * is established. @ref nrf_ringbuf_put frees access to allocation. If a start flag is not set, then + * exclusive access check is omitted. + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] pp_data Pointer to the pointer to the allocated buffer. + * @param[in, out] p_length Pointer to length. Length is set to the requested amount and filled + * by the function with actually allocated amount. + * @param[in] start Set to true if exclusive access should be controlled. + * + * @retval NRF_SUCCESS Successful allocation (can be smaller amount than requested). + * NRF_ERROR_BUSY Ring buffer allocation process (alloc-put) is ongoing. + * + * */ +ret_code_t nrf_ringbuf_alloc(nrf_ringbuf_t const * p_ringbuf, uint8_t * * pp_data, size_t * p_length, bool start); + +/** + * @brief Function for commiting data to a ring buffer. + * + * When an allocated buffer (see @ref nrf_ringbuf_alloc) has been filled with data, it must be committed + * to make it available for @ref nrf_ringbuf_get and @ref nrf_ringbuf_cpy_get. This function commits + * the data (can be smaller amount than allocated). + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] length Amount of bytes to put. + + * @return NRF_SUCCESS on successful put or error. + * */ +ret_code_t nrf_ringbuf_put(nrf_ringbuf_t const * p_ringbuf, size_t length); + +/** + * @brief Function for copying data directly into the ring buffer. + * + * This function copies a user buffer to the ring buffer. + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] p_data Pointer to the input buffer. + * @param[in, out] p_length Amount of bytes to copy. Amount of bytes copied. + + * @return NRF_SUCCESS on successful put or error. + * */ +ret_code_t nrf_ringbuf_cpy_put(nrf_ringbuf_t const * p_ringbuf, + uint8_t const* p_data, + size_t * p_length); + + +/** + * Function for getting data from the ring buffer. + * + * This function attempts to get the requested amount of data from the ring buffer. If a start flag is set, then + * exclusive access to getting data from the ring buffer is established. @ref nrf_ringbuf_free frees + * access to getting data from the ring buffer. If a start flag is not set, then + * exclusive access check is omitted. + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] pp_data Pointer to the pointer to the buffer with data. + * @param[in, out] p_length Pointer to length. Length is set to the requested amount and filled + * by the function with the actual amount. + * @param[in] start Set to true if exclusive access should be controlled. + * + * @retval NRF_SUCCESS Successful getting (can be smaller amount than requested). + * NRF_ERROR_BUSY Ring buffer getting process (get-free) is ongoing. + */ +ret_code_t nrf_ringbuf_get(nrf_ringbuf_t const * p_ringbuf, uint8_t * * pp_data, size_t * p_length, bool start); + +/** + * @brief Function for freeing a buffer back to the ring buffer. + * + * When a buffer with data taken from the ring buffer (see @ref nrf_ringbuf_get) has been processed, it + * must be freed to make it available for further use. This function frees the buffer (can be smaller + * amount than get). + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] length Amount of bytes to free. + + * @return NRF_SUCCESS on successful put or error. + * */ +ret_code_t nrf_ringbuf_free(nrf_ringbuf_t const * p_ringbuf, size_t length); + +/** + * @brief Function for copying data directly out of the ring buffer. + * + * This function copies available data from the ring buffer to a user buffer. + * + * @param[in] p_ringbuf Pointer to the ring buffer instance. + * @param[in] p_data Pointer to the input buffer. + * @param[in, out] p_length Amount of bytes to copy. Amount of bytes copied. + + * @return NRF_SUCCESS on successful put or error. + * */ +ret_code_t nrf_ringbuf_cpy_get(nrf_ringbuf_t const * p_ringbuf, + uint8_t * p_data, + size_t * p_length); +#ifdef __cplusplus +} +#endif + +#endif //NRF_RINGBUF_H +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.c b/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.c new file mode 100644 index 0000000..f7f4336 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.c @@ -0,0 +1,288 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(APP_SCHEDULER) +#include "app_scheduler.h" +#include +#include +#include +#include "nrf_soc.h" +#include "nrf_assert.h" +#include "app_util_platform.h" + +/**@brief Structure for holding a scheduled event header. */ +typedef struct +{ + app_sched_event_handler_t handler; /**< Pointer to event handler to receive the event. */ + uint16_t event_data_size; /**< Size of event data. */ +} event_header_t; + +STATIC_ASSERT(sizeof(event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE); + +static event_header_t * m_queue_event_headers; /**< Array for holding the queue event headers. */ +static uint8_t * m_queue_event_data; /**< Array for holding the queue event data. */ +static volatile uint8_t m_queue_start_index; /**< Index of queue entry at the start of the queue. */ +static volatile uint8_t m_queue_end_index; /**< Index of queue entry at the end of the queue. */ +static uint16_t m_queue_event_size; /**< Maximum event size in queue. */ +static uint16_t m_queue_size; /**< Number of queue entries. */ + +#if APP_SCHEDULER_WITH_PROFILER +static uint16_t m_max_queue_utilization; /**< Maximum observed queue utilization. */ +#endif + +#if APP_SCHEDULER_WITH_PAUSE +static uint32_t m_scheduler_paused_counter = 0; /**< Counter storing the difference between pausing + and resuming the scheduler. */ +#endif + +/**@brief Function for incrementing a queue index, and handle wrap-around. + * + * @param[in] index Old index. + * + * @return New (incremented) index. + */ +static __INLINE uint8_t next_index(uint8_t index) +{ + return (index < m_queue_size) ? (index + 1) : 0; +} + + +static __INLINE uint8_t app_sched_queue_full() +{ + uint8_t tmp = m_queue_start_index; + return next_index(m_queue_end_index) == tmp; +} + +/**@brief Macro for checking if a queue is full. */ +#define APP_SCHED_QUEUE_FULL() app_sched_queue_full() + + +static __INLINE uint8_t app_sched_queue_empty() +{ + uint8_t tmp = m_queue_start_index; + return m_queue_end_index == tmp; +} + +/**@brief Macro for checking if a queue is empty. */ +#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty() + + +uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer) +{ + uint16_t data_start_index = (queue_size + 1) * sizeof(event_header_t); + + // Check that buffer is correctly aligned + if (!is_word_aligned(p_event_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Initialize event scheduler + m_queue_event_headers = p_event_buffer; + m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index]; + m_queue_end_index = 0; + m_queue_start_index = 0; + m_queue_event_size = event_size; + m_queue_size = queue_size; + +#if APP_SCHEDULER_WITH_PROFILER + m_max_queue_utilization = 0; +#endif + + return NRF_SUCCESS; +} + + +uint16_t app_sched_queue_space_get() +{ + uint16_t start = m_queue_start_index; + uint16_t end = m_queue_end_index; + uint16_t free_space = m_queue_size - ((end >= start) ? + (end - start) : (m_queue_size + 1 - start + end)); + return free_space; +} + + +#if APP_SCHEDULER_WITH_PROFILER +static void queue_utilization_check(void) +{ + uint16_t start = m_queue_start_index; + uint16_t end = m_queue_end_index; + uint16_t queue_utilization = (end >= start) ? (end - start) : + (m_queue_size + 1 - start + end); + + if (queue_utilization > m_max_queue_utilization) + { + m_max_queue_utilization = queue_utilization; + } +} + +uint16_t app_sched_queue_utilization_get(void) +{ + return m_max_queue_utilization; +} +#endif // APP_SCHEDULER_WITH_PROFILER + + +uint32_t app_sched_event_put(void const * p_event_data, + uint16_t event_data_size, + app_sched_event_handler_t handler) +{ + uint32_t err_code; + + if (event_data_size <= m_queue_event_size) + { + uint16_t event_index = 0xFFFF; + + CRITICAL_REGION_ENTER(); + + if (!APP_SCHED_QUEUE_FULL()) + { + event_index = m_queue_end_index; + m_queue_end_index = next_index(m_queue_end_index); + + #if APP_SCHEDULER_WITH_PROFILER + // This function call must be protected with critical region because + // it modifies 'm_max_queue_utilization'. + queue_utilization_check(); + #endif + } + + CRITICAL_REGION_EXIT(); + + if (event_index != 0xFFFF) + { + // NOTE: This can be done outside the critical region since the event consumer will + // always be called from the main loop, and will thus never interrupt this code. + m_queue_event_headers[event_index].handler = handler; + if ((p_event_data != NULL) && (event_data_size > 0)) + { + memcpy(&m_queue_event_data[event_index * m_queue_event_size], + p_event_data, + event_data_size); + m_queue_event_headers[event_index].event_data_size = event_data_size; + } + else + { + m_queue_event_headers[event_index].event_data_size = 0; + } + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + err_code = NRF_ERROR_INVALID_LENGTH; + } + + return err_code; +} + + +#if APP_SCHEDULER_WITH_PAUSE +void app_sched_pause(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter < UINT32_MAX) + { + m_scheduler_paused_counter++; + } + CRITICAL_REGION_EXIT(); +} + +void app_sched_resume(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter > 0) + { + m_scheduler_paused_counter--; + } + CRITICAL_REGION_EXIT(); +} +#endif //APP_SCHEDULER_WITH_PAUSE + + +/**@brief Function for checking if scheduler is paused which means that should break processing + * events. + * + * @return Boolean value - true if scheduler is paused, false otherwise. + */ +static __INLINE bool is_app_sched_paused(void) +{ +#if APP_SCHEDULER_WITH_PAUSE + return (m_scheduler_paused_counter > 0); +#else + return false; +#endif +} + + +void app_sched_execute(void) +{ + while (!is_app_sched_paused() && !APP_SCHED_QUEUE_EMPTY()) + { + // Since this function is only called from the main loop, there is no + // need for a critical region here, however a special care must be taken + // regarding update of the queue start index (see the end of the loop). + uint16_t event_index = m_queue_start_index; + + void * p_event_data; + uint16_t event_data_size; + app_sched_event_handler_t event_handler; + + p_event_data = &m_queue_event_data[event_index * m_queue_event_size]; + event_data_size = m_queue_event_headers[event_index].event_data_size; + event_handler = m_queue_event_headers[event_index].handler; + + event_handler(p_event_data, event_data_size); + + // Event processed, now it is safe to move the queue start index, + // so the queue entry occupied by this event can be used to store + // a next one. + m_queue_start_index = next_index(m_queue_start_index); + } +} +#endif //NRF_MODULE_ENABLED(APP_SCHEDULER) diff --git a/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.h b/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.h new file mode 100644 index 0000000..123d6f6 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/scheduler/app_scheduler.h @@ -0,0 +1,211 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_scheduler Scheduler + * @{ + * @ingroup app_common + * + * @brief The scheduler is used for transferring execution from the interrupt context to the main + * context. + * + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events + * when using the Scheduler. + * + * @section app_scheduler_req Requirements: + * + * @subsection main_context_logic Logic in main context: + * + * - Define an event handler for each type of event expected. + * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the + * application main loop. + * - Call app_sched_execute() from the main loop each time the application wakes up because of an + * event (typically when sd_app_evt_wait() returns). + * + * @subsection int_context_logic Logic in interrupt context: + * + * - In the interrupt handler, call app_sched_event_put() + * with the appropriate data and event handler. This will insert an event into the + * scheduler's queue. The app_sched_execute() function will pull this event and call its + * handler in the main context. + * + * @if (PERIPHERAL) + * For an example usage of the scheduler, see the implementations of + * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif + * + * @image html scheduler_working.svg The high level design of the scheduler + */ + +#ifndef APP_SCHEDULER_H__ +#define APP_SCHEDULER_H__ + +#include "sdk_config.h" +#include +#include "app_error.h" +#include "app_util.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the scheduler buffer. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @return Required scheduler buffer size (in bytes). + */ +#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ + (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) + +/**@brief Scheduler event handler type. */ +typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); + +/**@brief Macro for initializing the event scheduler. + * + * @details It will also handle dimensioning and allocation of the memory buffer required by the + * scheduler, making sure the buffer is correctly aligned. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ + do \ + { \ + static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +/**@brief Function for initializing the Scheduler. + * + * @details It must be called before entering the main loop. + * + * @param[in] max_event_size Maximum size of events to be passed through the scheduler. + * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of + * events that can be scheduled for execution). + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must + * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer + * must be aligned to a 4 byte boundary. + * + * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both + * allocate the scheduler buffer, and also align the buffer correctly. + * + * @retval NRF_SUCCESS Successful initialization. + * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte + * boundary). + */ +uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); + +/**@brief Function for executing all scheduled events. + * + * @details This function must be called from within the main loop. It will execute all events + * scheduled since the last time it was called. + */ +void app_sched_execute(void); + +/**@brief Function for scheduling an event. + * + * @details Puts an event into the event queue. + * + * @param[in] p_event_data Pointer to event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. + * @param[in] handler Event handler to receive the event. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +uint32_t app_sched_event_put(void const * p_event_data, + uint16_t event_size, + app_sched_event_handler_t handler); + +/**@brief Function for getting the maximum observed queue utilization. + * + * Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage. + * + * @note @ref APP_SCHEDULER_WITH_PROFILER must be enabled to use this functionality. + * + * @return Maximum number of events in queue observed so far. + */ +uint16_t app_sched_queue_utilization_get(void); + +/**@brief Function for getting the current amount of free space in the queue. + * + * @details The real amount of free space may be less if entries are being added from an interrupt. + * To get the sxact value, this function should be called from the critical section. + * + * @return Amount of free space in the queue. + */ +uint16_t app_sched_queue_space_get(void); + +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + * + * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + * + * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality. + */ +void app_sched_resume(void); + +#ifdef __cplusplus +} +#endif + +#endif // APP_SCHEDULER_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.c b/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.c new file mode 100644 index 0000000..a4d31cc --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.c @@ -0,0 +1,161 @@ +/** + * Copyright (c) 2011 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_STRERROR) +#include "nrf_strerror.h" + +/** + * @brief Macro for adding an entity to the description array. + * + * Macro that helps to create a single entity in the description array. + */ +#define NRF_STRERROR_ENTITY(mnemonic) {.code = mnemonic, .name = #mnemonic} + +/** + * @brief Array entity element that describes an error. + */ +typedef struct +{ + ret_code_t code; /**< Error code. */ + char const * name; /**< Descriptive name (the same as the internal error mnemonic). */ +}nrf_strerror_desc_t; + +/** + * @brief Unknown error code. + * + * The constant string used by @ref nrf_strerror_get when the error description was not found. + */ +static char const m_unknown_str[] = "Unknown error code"; + +/** + * @brief Array with error codes. + * + * Array that describes error codes. + * + * @note It is required for this array to have error codes placed in ascending order. + * This condition is checked in automatic unit test before the release. + */ +static nrf_strerror_desc_t const nrf_strerror_array[] = +{ + NRF_STRERROR_ENTITY(NRF_SUCCESS), + NRF_STRERROR_ENTITY(NRF_ERROR_SVC_HANDLER_MISSING), + NRF_STRERROR_ENTITY(NRF_ERROR_SOFTDEVICE_NOT_ENABLED), + NRF_STRERROR_ENTITY(NRF_ERROR_INTERNAL), + NRF_STRERROR_ENTITY(NRF_ERROR_NO_MEM), + NRF_STRERROR_ENTITY(NRF_ERROR_NOT_FOUND), + NRF_STRERROR_ENTITY(NRF_ERROR_NOT_SUPPORTED), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_PARAM), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_STATE), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_LENGTH), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_FLAGS), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_DATA), + NRF_STRERROR_ENTITY(NRF_ERROR_DATA_SIZE), + NRF_STRERROR_ENTITY(NRF_ERROR_TIMEOUT), + NRF_STRERROR_ENTITY(NRF_ERROR_NULL), + NRF_STRERROR_ENTITY(NRF_ERROR_FORBIDDEN), + NRF_STRERROR_ENTITY(NRF_ERROR_INVALID_ADDR), + NRF_STRERROR_ENTITY(NRF_ERROR_BUSY), +#ifdef NRF_ERROR_CONN_COUNT + NRF_STRERROR_ENTITY(NRF_ERROR_CONN_COUNT), +#endif +#ifdef NRF_ERROR_RESOURCES + NRF_STRERROR_ENTITY(NRF_ERROR_RESOURCES), +#endif + + /* SDK Common errors */ + NRF_STRERROR_ENTITY(NRF_ERROR_MODULE_NOT_INITIALIZED), + NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_INIT_FAILED), + NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_LOCK_FAILED), + NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_UNLOCK_FAILED), + NRF_STRERROR_ENTITY(NRF_ERROR_MUTEX_COND_INIT_FAILED), + NRF_STRERROR_ENTITY(NRF_ERROR_MODULE_ALREADY_INITIALIZED), + NRF_STRERROR_ENTITY(NRF_ERROR_STORAGE_FULL), + NRF_STRERROR_ENTITY(NRF_ERROR_API_NOT_IMPLEMENTED), + NRF_STRERROR_ENTITY(NRF_ERROR_FEATURE_NOT_ENABLED), + NRF_STRERROR_ENTITY(NRF_ERROR_IO_PENDING), + + /* TWI error codes */ + NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_OVERRUN), + NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_ANACK), + NRF_STRERROR_ENTITY(NRF_ERROR_DRV_TWI_ERR_DNACK), + + /* IPSP error codes */ + NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_RX_PKT_TRUNCATED), + NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_CHANNEL_ALREADY_EXISTS), + NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_LINK_DISCONNECTED), + NRF_STRERROR_ENTITY(NRF_ERROR_BLE_IPSP_PEER_REJECTED) +}; + + +char const * nrf_strerror_get(ret_code_t code) +{ + char const * p_ret = nrf_strerror_find(code); + return (p_ret == NULL) ? m_unknown_str : p_ret; +} + +char const * nrf_strerror_find(ret_code_t code) +{ + nrf_strerror_desc_t const * p_start; + nrf_strerror_desc_t const * p_end; + p_start = nrf_strerror_array; + p_end = nrf_strerror_array + ARRAY_SIZE(nrf_strerror_array); + + while (p_start < p_end) + { + nrf_strerror_desc_t const * p_mid = p_start + ((p_end - p_start) / 2); + ret_code_t mid_c = p_mid->code; + if (mid_c > code) + { + p_end = p_mid; + } + else if (mid_c < code) + { + p_start = p_mid + 1; + } + else + { + return p_mid->name; + } + } + return NULL; +} + +#endif /* NRF_STRERROR enabled */ diff --git a/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.h b/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.h new file mode 100644 index 0000000..9f302c4 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/strerror/nrf_strerror.h @@ -0,0 +1,89 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @defgroup nrf_strerror Error code to string converter + * @ingroup app_common + * + * @brief Module for converting error code into a printable string. + * @{ + */ +#ifndef NRF_STRERROR_H__ +#define NRF_STRERROR_H__ + +#include "sdk_errors.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Function for getting a printable error string. + * + * @param code Error code to convert. + * + * @note This function cannot fail. + * For the function that may fail with error translation, see @ref nrf_strerror_find. + * + * @return Pointer to the printable string. + * If the string is not found, + * it returns a simple string that says that the error is unknown. + */ +char const * nrf_strerror_get(ret_code_t code); + +/** + * @brief Function for finding a printable error string. + * + * This function gets the error string in the same way as @ref nrf_strerror_get, + * but if the string is not found, it returns NULL. + * + * @param code Error code to convert. + * @return Pointer to the printable string. + * If the string is not found, NULL is returned. + */ +char const * nrf_strerror_find(ret_code_t code); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_STRERROR_H__ */ diff --git a/HAL_Driver/sdk/components/libraries/timer/app_timer.c b/HAL_Driver/sdk/components/libraries/timer/app_timer.c new file mode 100644 index 0000000..26d446b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/timer/app_timer.c @@ -0,0 +1,1075 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(APP_TIMER) +#include "app_timer.h" +#include +#include "nrf.h" +#include "nrf_peripherals.h" +#include "nrf_soc.h" +#include "app_error.h" +#include "nrf_delay.h" +#include "app_util_platform.h" +#if APP_TIMER_CONFIG_USE_SCHEDULER +#include "app_scheduler.h" +#endif + +#define RTC1_IRQ_PRI APP_TIMER_CONFIG_IRQ_PRIORITY /**< Priority of the RTC1 interrupt (used for checking for timeouts and executing timeout handlers). */ +#define SWI_IRQ_PRI APP_TIMER_CONFIG_IRQ_PRIORITY /**< Priority of the SWI interrupt (used for updating the timer list). */ + +// The current design assumes that both interrupt handlers run at the same interrupt level. +// If this is to be changed, protection must be added to prevent them from interrupting each other +// (e.g. by using guard/trigger flags). +STATIC_ASSERT(RTC1_IRQ_PRI == SWI_IRQ_PRI); + +#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ + +#define RTC_COMPARE_OFFSET_MIN 3 /**< Minimum offset between the current RTC counter value and the Capture Compare register. Although the nRF51 Series User Specification recommends this value to be 2, we use 3 to be safer.*/ + +#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */ + +#ifdef EGU_PRESENT +#define SWI_PART(_id) CONCAT_2(SWI,_id) +#define EGU_PART(_id) CONCAT_2(_EGU,_id) +#define SWI_IRQ_n(_id) CONCAT_3(SWI_PART(_id), EGU_PART(_id),_IRQn) +#define SWI_IRQ_Handler_n(_id) CONCAT_3(SWI_PART(_id), EGU_PART(_id),_IRQHandler) +#else //EGU_PRESENT +#define SWI_IRQ_n(_id) CONCAT_3(SWI,_id,_IRQn) +#define SWI_IRQ_Handler_n(_id) CONCAT_3(SWI,_id,_IRQHandler) +#endif + +#define SWI_IRQn SWI_IRQ_n(APP_TIMER_CONFIG_SWI_NUMBER) +#define SWI_IRQHandler SWI_IRQ_Handler_n(APP_TIMER_CONFIG_SWI_NUMBER) + + +#define MODULE_INITIALIZED (m_op_queue.size != 0) /**< Macro designating whether the module has been initialized properly. */ + +/**@brief Timer node type. The nodes will be used form a linked list of running timers. */ +typedef struct +{ + uint32_t ticks_to_expire; /**< Number of ticks from previous timer interrupt to timer expiry. */ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + bool is_running; /**< True if timer is running, False otherwise. */ + app_timer_mode_t mode; /**< Timer mode. */ + app_timer_timeout_handler_t p_timeout_handler; /**< Pointer to function to be executed when the timer expires. */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ + void * next; /**< Pointer to the next node. */ +} timer_node_t; + +STATIC_ASSERT(sizeof(timer_node_t) == APP_TIMER_NODE_SIZE); + +/**@brief Set of available timer operation types. */ +typedef enum +{ + TIMER_USER_OP_TYPE_NONE, /**< Invalid timer operation type. */ + TIMER_USER_OP_TYPE_START, /**< Timer operation type Start. */ + TIMER_USER_OP_TYPE_STOP, /**< Timer operation type Stop. */ + TIMER_USER_OP_TYPE_STOP_ALL /**< Timer operation type Stop All. */ +} timer_user_op_type_t; + +/**@brief Structure describing a timer start operation. */ +typedef struct +{ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ +} timer_user_op_start_t; + +/**@brief Structure describing a timer operation. */ +typedef struct +{ + timer_user_op_type_t op_type; /**< Id of timer on which the operation is to be performed. */ + timer_node_t * p_node; + union + { + timer_user_op_start_t start; /**< Structure describing a timer start operation. */ + } params; +} timer_user_op_t; + +/**@brief Structure describing a timer operations queue. + * + * @details This queue will hold timer operations issued by the application + * until the timer interrupt handler processes these operations. + */ +typedef struct +{ + uint8_t first; /**< Index of first entry to have been inserted in the queue (i.e. the next entry to be executed). */ + uint8_t last; /**< Index of last entry to have been inserted in the queue. */ + uint8_t size; /**< Queue size. */ + timer_user_op_t user_op_queue[APP_TIMER_CONFIG_OP_QUEUE_SIZE+1]; /**< Queue buffer. */ +} timer_op_queue_t; + +STATIC_ASSERT(sizeof(timer_op_queue_t) % 4 == 0); + +#define CONTEXT_QUEUE_SIZE_MAX (2) + +static timer_op_queue_t m_op_queue; /**< Timer operations queue. */ +static timer_node_t * mp_timer_id_head; /**< First timer in list of running timers. */ +static uint32_t m_ticks_latest; /**< Last known RTC counter value. */ +static uint32_t m_ticks_elapsed[CONTEXT_QUEUE_SIZE_MAX]; /**< Timer internal elapsed ticks queue. */ +static uint8_t m_ticks_elapsed_q_read_ind; /**< Timer internal elapsed ticks queue read index. */ +static uint8_t m_ticks_elapsed_q_write_ind; /**< Timer internal elapsed ticks queue write index. */ +static bool m_rtc1_running; /**< Boolean indicating if RTC1 is running. */ +static bool m_rtc1_reset; /**< Boolean indicating if RTC1 counter has been reset due to last timer removed from timer list during the timer list handling. */ + +#if APP_TIMER_WITH_PROFILER +static uint8_t m_max_user_op_queue_utilization; /**< Maximum observed timer user operations queue utilization. */ +#endif + +/**@brief Function for initializing the RTC1 counter. + * + * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. + */ +static void rtc1_init(uint32_t prescaler) +{ + NRF_RTC1->PRESCALER = prescaler; + NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); +} + + +/**@brief Function for starting the RTC1 timer. + */ +static void rtc1_start(void) +{ + NRF_RTC1->EVTENSET = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk; + + NVIC_ClearPendingIRQ(RTC1_IRQn); + NVIC_EnableIRQ(RTC1_IRQn); + + NRF_RTC1->TASKS_START = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = true; +} + + +/**@brief Function for stopping the RTC1 timer. + */ +static void rtc1_stop(void) +{ + NVIC_DisableIRQ(RTC1_IRQn); + + NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk; + + NRF_RTC1->TASKS_STOP = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = false; +} + + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @return Current value of the RTC1 counter. + */ +static __INLINE uint32_t rtc1_counter_get(void) +{ + return NRF_RTC1->COUNTER; +} + + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @return Number of ticks elapsed from ticks_old to ticks_now. + */ +static __INLINE uint32_t ticks_diff_get(uint32_t ticks_now, uint32_t ticks_old) +{ + return ((ticks_now - ticks_old) & MAX_RTC_COUNTER_VAL); +} + + +/**@brief Function for setting the RTC1 Capture Compare register 0, and enabling the corresponding + * event. + * + * @param[in] value New value of Capture Compare register 0. + */ +static __INLINE void rtc1_compare0_set(uint32_t value) +{ + NRF_RTC1->CC[0] = value; +} + + +/**@brief Function for inserting a timer in the timer list. + * + * @param[in] timer_id Id of timer to insert. + */ +static void timer_list_insert(timer_node_t * p_timer) +{ + if (mp_timer_id_head == NULL) + { + mp_timer_id_head = p_timer; + } + else + { + if (p_timer->ticks_to_expire <= mp_timer_id_head->ticks_to_expire) + { + mp_timer_id_head->ticks_to_expire -= p_timer->ticks_to_expire; + + p_timer->next = mp_timer_id_head; + mp_timer_id_head = p_timer; + } + else + { + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t ticks_to_expire; + + ticks_to_expire = p_timer->ticks_to_expire; + p_previous = mp_timer_id_head; + p_current = mp_timer_id_head; + + while ((p_current != NULL) && (ticks_to_expire > p_current->ticks_to_expire)) + { + ticks_to_expire -= p_current->ticks_to_expire; + p_previous = p_current; + p_current = p_current->next; + } + + if (p_current != NULL) + { + p_current->ticks_to_expire -= ticks_to_expire; + } + + p_timer->ticks_to_expire = ticks_to_expire; + p_timer->next = p_current; + p_previous->next = p_timer; + } + } +} + + +/**@brief Function for removing a timer from the timer queue. + * + * @param[in] timer_id Id of timer to remove. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool timer_list_remove(timer_node_t * p_timer) +{ + timer_node_t * p_old_head; + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t timeout; + + // Find the timer's position in timer list. + p_old_head = mp_timer_id_head; + p_previous = mp_timer_id_head; + p_current = p_previous; + + while (p_current != NULL) + { + if (p_current == p_timer) + { + break; + } + p_previous = p_current; + p_current = p_current->next; + } + + // Timer not in active list. + if (p_current == NULL) + { + return false; + } + + // Timer is the first in the list + if (p_previous == p_current) + { + mp_timer_id_head = mp_timer_id_head->next; + + // No more timers in the list. Reset RTC1 in case Start timer operations are present in the queue. + if (mp_timer_id_head == NULL) + { + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + m_rtc1_reset = true; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + } + } + + // Remaining timeout between next timeout. + timeout = p_current->ticks_to_expire; + + // Link previous timer with next of this timer, i.e. removing the timer from list. + p_previous->next = p_current->next; + + // If this is not the last timer, increment the next timer by this timer timeout. + p_current = p_previous->next; + if (p_current != NULL) + { + p_current->ticks_to_expire += timeout; + } + + return (p_old_head != mp_timer_id_head); +} + + +/**@brief Function for scheduling a check for timeouts by generating a RTC1 interrupt. + */ +static void timer_timeouts_check_sched(void) +{ + NVIC_SetPendingIRQ(RTC1_IRQn); +} + + +/**@brief Function for scheduling a timer list update by generating a SWI interrupt. + */ +static void timer_list_handler_sched(void) +{ + NVIC_SetPendingIRQ(SWI_IRQn); +} + +#if APP_TIMER_CONFIG_USE_SCHEDULER +static void timeout_handler_scheduled_exec(void * p_event_data, uint16_t event_size) +{ + APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); + app_timer_event_t const * p_timer_event = (app_timer_event_t *)p_event_data; + + p_timer_event->timeout_handler(p_timer_event->p_context); +} +#endif + +/**@brief Function for executing an application timeout handler, either by calling it directly, or + * by passing an event to the @ref app_scheduler. + * + * @param[in] p_timer Pointer to expired timer. + */ +static void timeout_handler_exec(timer_node_t * p_timer) +{ +#if APP_TIMER_CONFIG_USE_SCHEDULER + app_timer_event_t timer_event; + + timer_event.timeout_handler = p_timer->p_timeout_handler; + timer_event.p_context = p_timer->p_context; + uint32_t err_code = app_sched_event_put(&timer_event, sizeof(timer_event), timeout_handler_scheduled_exec); + APP_ERROR_CHECK(err_code); +#else + p_timer->p_timeout_handler(p_timer->p_context); +#endif +} + + +/**@brief Function for checking for expired timers. + */ +static void timer_timeouts_check(void) +{ + // Handle expired of timer + if (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_previous_timer; + uint32_t ticks_elapsed; + uint32_t ticks_expired; + + // Initialize actual elapsed ticks being consumed to 0. + ticks_expired = 0; + + // ticks_elapsed is collected here, job will use it. + ticks_elapsed = ticks_diff_get(rtc1_counter_get(), m_ticks_latest); + + // Auto variable containing the head of timers expiring. + p_timer = mp_timer_id_head; + + // Expire all timers within ticks_elapsed and collect ticks_expired. + while (p_timer != NULL) + { + // Do nothing if timer did not expire. + if (ticks_elapsed < p_timer->ticks_to_expire) + { + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Move to next timer. + p_previous_timer = p_timer; + p_timer = p_timer->next; + + // Execute Task. + if (p_previous_timer->is_running) + { + p_previous_timer->is_running = false; + timeout_handler_exec(p_previous_timer); + } + } + + // Prepare to queue the ticks expired in the m_ticks_elapsed queue. + if (m_ticks_elapsed_q_read_ind == m_ticks_elapsed_q_write_ind) + { + // The read index of the queue is equal to the write index. This means the new + // value of ticks_expired should be stored at a new location in the m_ticks_elapsed + // queue (which is implemented as a double buffer). + + // Check if there will be a queue overflow. + if (++m_ticks_elapsed_q_write_ind == CONTEXT_QUEUE_SIZE_MAX) + { + // There will be a queue overflow. Hence the write index should point to the start + // of the queue. + m_ticks_elapsed_q_write_ind = 0; + } + } + + // Queue the ticks expired. + m_ticks_elapsed[m_ticks_elapsed_q_write_ind] = ticks_expired; + + timer_list_handler_sched(); + } +} + + +/**@brief Function for acquiring the number of ticks elapsed. + * + * @param[out] p_ticks_elapsed Number of ticks elapsed. + * + * @return TRUE if elapsed ticks was read from queue, FALSE otherwise. + */ +static bool elapsed_ticks_acquire(uint32_t * p_ticks_elapsed) +{ + // Pick the elapsed value from queue. + if (m_ticks_elapsed_q_read_ind != m_ticks_elapsed_q_write_ind) + { + // Dequeue elapsed value. + m_ticks_elapsed_q_read_ind++; + if (m_ticks_elapsed_q_read_ind == CONTEXT_QUEUE_SIZE_MAX) + { + m_ticks_elapsed_q_read_ind = 0; + } + + *p_ticks_elapsed = m_ticks_elapsed[m_ticks_elapsed_q_read_ind]; + + m_ticks_latest += *p_ticks_elapsed; + m_ticks_latest &= MAX_RTC_COUNTER_VAL; + + return true; + } + else + { + // No elapsed value in queue. + *p_ticks_elapsed = 0; + return false; + } +} + + +/**@brief Function for updating the timer list for expired timers. + * + * @param[in] ticks_elapsed Number of elapsed ticks. + * @param[in] ticks_previous Previous known value of the RTC counter. + * @param[out] p_restart_list_head List of repeating timers to be restarted. + */ +static void expired_timers_handler(uint32_t ticks_elapsed, + uint32_t ticks_previous, + timer_node_t ** p_restart_list_head) +{ + uint32_t ticks_expired = 0; + + while (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_timer_expired; + + // Auto variable for current timer node. + p_timer = mp_timer_id_head; + + // Do nothing if timer did not expire + if (ticks_elapsed < p_timer->ticks_to_expire) + { + p_timer->ticks_to_expire -= ticks_elapsed; + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Timer expired, set ticks_to_expire zero. + p_timer->ticks_to_expire = 0; + + // Remove the expired timer from head. + p_timer_expired = mp_timer_id_head; + mp_timer_id_head = p_timer->next; + + // Timer will be restarted if periodic. + if (p_timer->ticks_periodic_interval != 0) + { + p_timer->ticks_at_start = (ticks_previous + ticks_expired) & MAX_RTC_COUNTER_VAL; + p_timer->ticks_first_interval = p_timer->ticks_periodic_interval; + p_timer->next = *p_restart_list_head; + *p_restart_list_head = p_timer_expired; + } + } +} + + +/**@brief Function for handling timer list insertions. + * + * @param[in] p_restart_list_head List of repeating timers to be restarted. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool list_insertions_handler(timer_node_t * p_restart_list_head) +{ + bool compare_update = false; + + timer_node_t * p_timer_id_old_head; + + // Remember the old head, so as to decide if new compare needs to be set. + p_timer_id_old_head = mp_timer_id_head; + + // Handle insertions of timers. + while ((p_restart_list_head != NULL) || (m_op_queue.first != m_op_queue.last)) + { + timer_node_t * p_timer; + + if (p_restart_list_head != NULL) + { + p_timer = p_restart_list_head; + p_restart_list_head = p_timer->next; + } + else + { + timer_user_op_t * p_user_op = &m_op_queue.user_op_queue[m_op_queue.first]; + + m_op_queue.first++; + if (m_op_queue.first == m_op_queue.size) + { + m_op_queue.first = 0; + } + + p_timer = p_user_op->p_node; + + switch (p_user_op->op_type) + { + case TIMER_USER_OP_TYPE_STOP: + // Delete node if timer is running. + if (timer_list_remove(p_user_op->p_node)) + { + compare_update = true; + } + + p_timer->is_running = false; + continue; + + case TIMER_USER_OP_TYPE_STOP_ALL: + // Delete list of running timers, and mark all timers as not running. + while (mp_timer_id_head != NULL) + { + timer_node_t * p_head = mp_timer_id_head; + + p_head->is_running = false; + mp_timer_id_head = p_head->next; + } + continue; + case TIMER_USER_OP_TYPE_START: + break; + default: + // No implementation needed. + continue; + } + + if (p_timer->is_running) + { + continue; + } + + p_timer->ticks_at_start = p_user_op->params.start.ticks_at_start; + p_timer->ticks_first_interval = p_user_op->params.start.ticks_first_interval; + p_timer->ticks_periodic_interval = p_user_op->params.start.ticks_periodic_interval; + p_timer->p_context = p_user_op->params.start.p_context; + + if (m_rtc1_reset) + { + p_timer->ticks_at_start = 0; + } + } + + // Prepare the node to be inserted. + if ( + ((p_timer->ticks_at_start - m_ticks_latest) & MAX_RTC_COUNTER_VAL) + < + (MAX_RTC_COUNTER_VAL / 2) + ) + { + p_timer->ticks_to_expire = ticks_diff_get(p_timer->ticks_at_start, m_ticks_latest) + + p_timer->ticks_first_interval; + } + else + { + uint32_t delta_current_start; + + delta_current_start = ticks_diff_get(m_ticks_latest, p_timer->ticks_at_start); + if (p_timer->ticks_first_interval > delta_current_start) + { + p_timer->ticks_to_expire = p_timer->ticks_first_interval - delta_current_start; + } + else + { + p_timer->ticks_to_expire = 0; + } + } + + p_timer->ticks_at_start = 0; + p_timer->ticks_first_interval = 0; + p_timer->is_running = true; + p_timer->next = NULL; + + // Insert into list + timer_list_insert(p_timer); + } + + return (compare_update || (mp_timer_id_head != p_timer_id_old_head)); +} + + +/**@brief Function for updating the Capture Compare register. + */ +static void compare_reg_update(timer_node_t * p_timer_id_head_old) +{ + // Setup the timeout for timers on the head of the list + if (mp_timer_id_head != NULL) + { + uint32_t ticks_to_expire = mp_timer_id_head->ticks_to_expire; + uint32_t pre_counter_val = rtc1_counter_get(); + uint32_t cc = m_ticks_latest; + uint32_t ticks_elapsed = ticks_diff_get(pre_counter_val, cc) + RTC_COMPARE_OFFSET_MIN; + + if (!m_rtc1_running) + { + // No timers were already running, start RTC + rtc1_start(); + } + + cc += (ticks_elapsed < ticks_to_expire) ? ticks_to_expire : ticks_elapsed; + cc &= MAX_RTC_COUNTER_VAL; + + rtc1_compare0_set(cc); + + uint32_t post_counter_val = rtc1_counter_get(); + + if ( + (ticks_diff_get(post_counter_val, pre_counter_val) + RTC_COMPARE_OFFSET_MIN) + > + ticks_diff_get(cc, pre_counter_val) + ) + { + // When this happens the COMPARE event may not be triggered by the RTC. + // The nRF51 Series User Specification states that if the COUNTER value is N + // (i.e post_counter_val = N), writing N or N + 1 to a CC register may not trigger a + // COMPARE event. Hence the RTC interrupt is forcefully pended by calling the following + // function. + rtc1_compare0_set(rtc1_counter_get()); // this should prevent CC to fire again in the background while the code is in RTC-ISR + nrf_delay_us(MAX_RTC_TASKS_DELAY); + timer_timeouts_check_sched(); + } + } + else + { +#if (APP_TIMER_KEEPS_RTC_ACTIVE == 0) + // No timers are running, stop RTC + rtc1_stop(); +#endif //(APP_TIMER_KEEPS_RTC_ACTIVE == 0) + } +} + + +/**@brief Function for handling changes to the timer list. + */ +static void timer_list_handler(void) +{ + timer_node_t * p_restart_list_head = NULL; + + uint32_t ticks_elapsed; + uint32_t ticks_previous; + bool ticks_have_elapsed; + bool compare_update = false; + timer_node_t * p_timer_id_head_old; + +#if APP_TIMER_WITH_PROFILER + { + uint8_t size = m_op_queue.size; + uint8_t first = m_op_queue.first; + uint8_t last = m_op_queue.last; + uint8_t utilization = (first <= last) ? (last - first) : (size + 1 - first + last); + + if (utilization > m_max_user_op_queue_utilization) + { + m_max_user_op_queue_utilization = utilization; + } + } +#endif + + // Back up the previous known tick and previous list head + ticks_previous = m_ticks_latest; + p_timer_id_head_old = mp_timer_id_head; + + // Get number of elapsed ticks + ticks_have_elapsed = elapsed_ticks_acquire(&ticks_elapsed); + + // Handle expired timers + if (ticks_have_elapsed) + { + expired_timers_handler(ticks_elapsed, ticks_previous, &p_restart_list_head); + compare_update = true; + } + + + // Handle list insertions + if (list_insertions_handler(p_restart_list_head)) + { + compare_update = true; + } + + // Update compare register if necessary + if (compare_update) + { + compare_reg_update(p_timer_id_head_old); + } + m_rtc1_reset = false; +} + + +/**@brief Function for enqueueing a new operations queue entry. + * + * @param[in] last_index Index of the next last index to be enqueued. + */ +static void user_op_enque(uint8_t last_index) +{ + m_op_queue.last = last_index; +} + + +/**@brief Function for allocating a new operations queue entry. + * + * @param[out] p_last_index Index of the next last index to be enqueued. + * + * @return Pointer to allocated queue entry, or NULL if queue is full. + */ +static timer_user_op_t * user_op_alloc( uint8_t * p_last_index) +{ + uint8_t last; + timer_user_op_t * p_user_op; + + last = m_op_queue.last + 1; + if (last == m_op_queue.size) + { + // Overflow case. + last = 0; + } + if (last == m_op_queue.first) + { + // Queue is full. + return NULL; + } + + *p_last_index = last; + p_user_op = &m_op_queue.user_op_queue[m_op_queue.last]; + + return p_user_op; +} + + +/**@brief Function for scheduling a Timer Start operation. + * + * @param[in] timer_id Id of timer to start. + * @param[in] timeout_initial Time (in ticks) to first timer expiry. + * @param[in] timeout_periodic Time (in ticks) between periodic expiries. + * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when + * the timer expires. + * @return NRF_SUCCESS on success, otherwise an error code. + */ + +static uint32_t timer_start_op_schedule(timer_node_t * p_node, + uint32_t timeout_initial, + uint32_t timeout_periodic, + void * p_context) +{ + uint8_t last_index; + uint32_t err_code = NRF_SUCCESS; + + CRITICAL_REGION_ENTER(); + timer_user_op_t * p_user_op = user_op_alloc(&last_index); + if (p_user_op == NULL) + { + err_code = NRF_ERROR_NO_MEM; + } + else + { + p_user_op->op_type = TIMER_USER_OP_TYPE_START; + p_user_op->p_node = p_node; + p_user_op->params.start.ticks_at_start = rtc1_counter_get(); + p_user_op->params.start.ticks_first_interval = timeout_initial; + p_user_op->params.start.ticks_periodic_interval = timeout_periodic; + p_user_op->params.start.p_context = p_context; + + user_op_enque(last_index); + } + CRITICAL_REGION_EXIT(); + + if (err_code == NRF_SUCCESS) + { + timer_list_handler_sched(); + } + + return err_code; +} + + +/**@brief Function for scheduling a Timer Stop operation. + * + * @param[in] timer_id Id of timer to stop. + * @param[in] op_type Type of stop operation + * + * @return NRF_SUCCESS on successful scheduling a timer stop operation. NRF_ERROR_NO_MEM when there + * is no memory left to schedule the timer stop operation. + */ +static uint32_t timer_stop_op_schedule(timer_node_t * p_node, + timer_user_op_type_t op_type) +{ + uint8_t last_index; + uint32_t err_code = NRF_SUCCESS; + + CRITICAL_REGION_ENTER(); + timer_user_op_t * p_user_op = user_op_alloc(&last_index); + if (p_user_op == NULL) + { + err_code = NRF_ERROR_NO_MEM; + } + else + { + p_user_op->op_type = op_type; + p_user_op->p_node = p_node; + + user_op_enque(last_index); + } + CRITICAL_REGION_EXIT(); + + if (err_code == NRF_SUCCESS) + { + timer_list_handler_sched(); + } + + return err_code; +} + +/**@brief Function for handling the RTC1 interrupt. + * + * @details Checks for timeouts, and executes timeout handlers for expired timers. + */ +void RTC1_IRQHandler(void) +{ + // Clear all events (also unexpected ones) + NRF_RTC1->EVENTS_COMPARE[0] = 0; + NRF_RTC1->EVENTS_COMPARE[1] = 0; + NRF_RTC1->EVENTS_COMPARE[2] = 0; + NRF_RTC1->EVENTS_COMPARE[3] = 0; + NRF_RTC1->EVENTS_TICK = 0; + NRF_RTC1->EVENTS_OVRFLW = 0; + + // Check for expired timers + timer_timeouts_check(); +} + + +/**@brief Function for handling the SWI interrupt. + * + * @details Performs all updates to the timer list. + */ +void SWI_IRQHandler(void) +{ + timer_list_handler(); +} + + +ret_code_t app_timer_init(void) +{ + // Stop RTC to prevent any running timers from expiring (in case of reinitialization) + rtc1_stop(); + + // Initialize operation queue + m_op_queue.first = 0; + m_op_queue.last = 0; + m_op_queue.size = APP_TIMER_CONFIG_OP_QUEUE_SIZE+1; + + mp_timer_id_head = NULL; + m_ticks_elapsed_q_read_ind = 0; + m_ticks_elapsed_q_write_ind = 0; + +#if APP_TIMER_WITH_PROFILER + m_max_user_op_queue_utilization = 0; +#endif + + NVIC_ClearPendingIRQ(SWI_IRQn); + NVIC_SetPriority(SWI_IRQn, SWI_IRQ_PRI); + NVIC_EnableIRQ(SWI_IRQn); + + rtc1_init(APP_TIMER_CONFIG_RTC_FREQUENCY); + + m_ticks_latest = rtc1_counter_get(); + + return NRF_SUCCESS; +} + + +ret_code_t app_timer_create(app_timer_id_t const * p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler) +{ + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timeout_handler == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_timer_id == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (((timer_node_t*)*p_timer_id)->is_running) + { + return NRF_ERROR_INVALID_STATE; + } + + timer_node_t * p_node = (timer_node_t *)*p_timer_id; + p_node->is_running = false; + p_node->mode = mode; + p_node->p_timeout_handler = timeout_handler; + return NRF_SUCCESS; +} + +ret_code_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context) +{ + uint32_t timeout_periodic; + timer_node_t * p_node = (timer_node_t*)timer_id; + + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timer_id == 0) + { + return NRF_ERROR_INVALID_STATE; + } + if (timeout_ticks < APP_TIMER_MIN_TIMEOUT_TICKS) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_node->p_timeout_handler == NULL) + { + return NRF_ERROR_INVALID_STATE; + } + + // Schedule timer start operation + timeout_periodic = (p_node->mode == APP_TIMER_MODE_REPEATED) ? timeout_ticks : 0; + + return timer_start_op_schedule(p_node, + timeout_ticks, + timeout_periodic, + p_context); +} + + +ret_code_t app_timer_stop(app_timer_id_t timer_id) +{ + timer_node_t * p_node = (timer_node_t*)timer_id; + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if ((timer_id == NULL) || (p_node->p_timeout_handler == NULL)) + { + return NRF_ERROR_INVALID_STATE; + } + + p_node->is_running = false; + + // Schedule timer stop operation + return timer_stop_op_schedule(p_node, TIMER_USER_OP_TYPE_STOP); +} + + +ret_code_t app_timer_stop_all(void) +{ + // Check state + VERIFY_MODULE_INITIALIZED(); + + return timer_stop_op_schedule(NULL, TIMER_USER_OP_TYPE_STOP_ALL); +} + + +uint32_t app_timer_cnt_get(void) +{ + return rtc1_counter_get(); +} + + +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from) +{ + return ticks_diff_get(ticks_to, ticks_from); +} + +#if APP_TIMER_WITH_PROFILER +uint8_t app_timer_op_queue_utilization_get(void) +{ + return m_max_user_op_queue_utilization; +} +#endif + +void app_timer_pause(void) +{ + NRF_RTC1->TASKS_STOP = 1; +} + +void app_timer_resume(void) +{ + NRF_RTC1->TASKS_START = 1; +} + +#endif //NRF_MODULE_ENABLED(APP_TIMER) diff --git a/HAL_Driver/sdk/components/libraries/timer/app_timer.h b/HAL_Driver/sdk/components/libraries/timer/app_timer.h new file mode 100644 index 0000000..067b23b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/timer/app_timer.h @@ -0,0 +1,313 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_timer Application Timer + * @{ + * @ingroup app_common + * + * @brief Application timer functionality. + * + * @details This module enables the application to create multiple timer instances based on the RTC1 + * peripheral. Checking for time-outs and invocation of user time-out handlers is performed + * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). + * Both interrupt handlers are running in APP_LOW priority level. + * + * @details When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, + * and the software interrupt is triggered. The actual timer start/stop operation is + * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, + * if the application code calling the timer function is running in APP_LOW or APP_HIGH, + * the timer operation will not be performed until the application handler has returned. + * This will be the case, for example, when stopping a timer from a time-out handler when not using + * the scheduler. + * + * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the + * @ref app_scheduler should be used or not. Even if the scheduler is + * not used, app_timer.h will include app_scheduler.h, so when + * compiling, app_scheduler.h must be available in one of the compiler include paths. + */ + +#ifndef APP_TIMER_H__ +#define APP_TIMER_H__ +#include "sdk_config.h" +#include "app_error.h" +#include "app_util.h" +#include "compiler_abstraction.h" +#include "nordic_common.h" +#ifdef APP_TIMER_V2 +#include "nrf_log_instance.h" +#include "nrf_sortlist.h" +#endif +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Name of the module used for logger messaging. + */ +#define APP_TIMER_LOG_NAME app_timer + +#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ +#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ + +#ifdef RTX +#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (used to allocate data). */ +#else +#define APP_TIMER_NODE_SIZE 32 /**< Size of app_timer.timer_node_t (used to allocate data). */ +#endif // RTX + +#define APP_TIMER_SCHED_EVENT_DATA_SIZE sizeof(app_timer_event_t) /**< Size of event data when scheduler is used. */ + +#define APP_TIMER_MAX_CNT_VAL RTC_COUNTER_COUNTER_Msk /**< Maximum counter value that can be returned by @ref app_timer_cnt_get. */ + +/**@brief Convert milliseconds to timer ticks. + * + * This macro uses 64-bit integer arithmetic, but as long as the macro parameters are + * constants (i.e. defines), the computation will be done by the preprocessor. + * + * @param[in] MS Milliseconds. + * + * @return Number of timer ticks. + */ +#ifndef FREERTOS +#define APP_TIMER_TICKS(MS) \ + ((uint32_t)ROUNDED_DIV( \ + (MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, \ + 1000 * (APP_TIMER_CONFIG_RTC_FREQUENCY + 1))) +#else +#include "FreeRTOSConfig.h" +#define APP_TIMER_TICKS(MS) (uint32_t)ROUNDED_DIV((MS)*configTICK_RATE_HZ,1000) +#endif + + +/** + * @brief Create a timer identifier and statically allocate memory for the timer. + * + * @param timer_id Name of the timer identifier variable that will be used to control the timer. + */ +#define APP_TIMER_DEF(timer_id) _APP_TIMER_DEF(timer_id) + +/**@brief Application time-out handler type. */ +typedef void (*app_timer_timeout_handler_t)(void * p_context); + +#ifdef APP_TIMER_V2 +/** + * @brief app_timer control block + */ +typedef struct +{ + nrf_sortlist_item_t list_item; /**< Token used by sortlist. */ + volatile uint32_t end_val; /**< RTC counter value when timer expires. */ + uint32_t repeat_period; /**< Repeat period (0 if single shot mode). */ + app_timer_timeout_handler_t handler; /**< User handler. */ + void * p_context; /**< User context. */ + NRF_LOG_INSTANCE_PTR_DECLARE(p_log) /**< Pointer to instance of the logger object (Conditionally compiled). */ + volatile bool active; /**< Flag indicating that timer is active. */ +} app_timer_t; + +/**@brief Timer ID type. + * Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/ +typedef app_timer_t * app_timer_id_t; + +#define _APP_TIMER_DEF(timer_id) \ + NRF_LOG_INSTANCE_REGISTER(APP_TIMER_LOG_NAME, timer_id, \ + APP_TIMER_CONFIG_INFO_COLOR, \ + APP_TIMER_CONFIG_DEBUG_COLOR, \ + APP_TIMER_CONFIG_INITIAL_LOG_LEVEL, \ + APP_TIMER_CONFIG_LOG_ENABLED ? \ + APP_TIMER_CONFIG_LOG_LEVEL : NRF_LOG_SEVERITY_NONE); \ + static app_timer_t CONCAT_2(timer_id,_data) = { \ + .active = false, \ + NRF_LOG_INSTANCE_PTR_INIT(p_log, APP_TIMER_LOG_NAME, timer_id) \ + }; \ + static const app_timer_id_t timer_id = &CONCAT_2(timer_id,_data) + +#else //APP_TIMER_V2 +typedef struct app_timer_t { uint32_t data[CEIL_DIV(APP_TIMER_NODE_SIZE, sizeof(uint32_t))]; } app_timer_t; + +/**@brief Timer ID type. + * Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/ +typedef app_timer_t * app_timer_id_t; + +#define _APP_TIMER_DEF(timer_id) \ + static app_timer_t CONCAT_2(timer_id,_data) = { {0} }; \ + static const app_timer_id_t timer_id = &CONCAT_2(timer_id,_data) + +#endif + + +/**@brief Structure passed to app_scheduler. */ +typedef struct +{ + app_timer_timeout_handler_t timeout_handler; + void * p_context; +} app_timer_event_t; + +/**@brief Timer modes. */ +typedef enum +{ + APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ + APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ +} app_timer_mode_t; + +/**@brief Function for initializing the timer module. + * + * @retval NRF_SUCCESS If the module was initialized successfully. + */ +ret_code_t app_timer_init(void); + +/**@brief Function for creating a timer instance. + * + * @param[in] p_timer_id Pointer to timer identifier. + * @param[in] mode Timer mode. + * @param[in] timeout_handler Function to be executed when the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully created. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or + * the timer is running. + * + * @note This function does the timer allocation in the caller's context. It is also not protected + * by a critical region. Therefore care must be taken not to call it from several interrupt + * levels simultaneously. + * @note The function can be called again on the timer instance and will re-initialize the instance if + * the timer is not running. + * @attention The FreeRTOS and RTX app_timer implementation does not allow app_timer_create to + * be called on the previously initialized instance. + */ +ret_code_t app_timer_create(app_timer_id_t const * p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler); + +/**@brief Function for starting a timer. + * + * @param[in] timer_id Timer identifier. + * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to time-out event + * (minimum 5 ticks). + * @param[in] p_context General purpose pointer. Will be passed to the time-out handler when + * the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully started. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + * + * @note The minimum timeout_ticks value is 5. + * @note For multiple active timers, time-outs occurring in close proximity to each other (in the + * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. + * @note When calling this method on a timer that is already running, the second start operation + * is ignored. + */ +ret_code_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); + +/**@brief Function for stopping the specified timer. + * + * @param[in] timer_id Timer identifier. + * + * @retval NRF_SUCCESS If the timer was successfully stopped. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +ret_code_t app_timer_stop(app_timer_id_t timer_id); + +/**@brief Function for stopping all running timers. + * + * @retval NRF_SUCCESS If all timers were successfully stopped. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +ret_code_t app_timer_stop_all(void); + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @return Current value of the RTC1 counter. + */ +uint32_t app_timer_cnt_get(void); + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @param[in] ticks_to Value returned by app_timer_cnt_get(). + * @param[in] ticks_from Value returned by app_timer_cnt_get(). + * + * @return Number of ticks from ticks_from to ticks_to. + */ +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from); + + +/**@brief Function for getting the maximum observed operation queue utilization. + * + * Function for tuning the module and determining OP_QUEUE_SIZE value and thus module RAM usage. + * + * @note APP_TIMER_WITH_PROFILER must be enabled to use this functionality. + * + * @return Maximum number of events in queue observed so far. + */ +uint8_t app_timer_op_queue_utilization_get(void); + +/** + * @brief Function for pausing RTC activity which drives app_timer. + * + * @note This function can be used for debugging purposes to ensure + * that application is halted when entering a breakpoint. + */ +void app_timer_pause(void); + +/** + * @brief Function for resuming RTC activity which drives app_timer. + * + * @note This function can be used for debugging purposes to resume + * application activity. + */ +void app_timer_resume(void); + +#ifdef __cplusplus +} +#endif + +#endif // APP_TIMER_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/uart/app_uart.h b/HAL_Driver/sdk/components/libraries/uart/app_uart.h new file mode 100644 index 0000000..ce773a2 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/uart/app_uart.h @@ -0,0 +1,262 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup app_uart UART module + * @{ + * @ingroup app_common + * + * @brief UART module interface. + */ + +#ifndef APP_UART_H__ +#define APP_UART_H__ + +#include +#include +#include "app_util_platform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UART_PIN_DISCONNECTED 0xFFFFFFFF /**< Value indicating that no pin is connected to this UART register. */ + +/**@brief UART Flow Control modes for the peripheral. + */ +typedef enum +{ + APP_UART_FLOW_CONTROL_DISABLED, /**< UART Hw Flow Control is disabled. */ + APP_UART_FLOW_CONTROL_ENABLED, /**< Standard UART Hw Flow Control is enabled. */ +} app_uart_flow_control_t; + +/**@brief UART communication structure holding configuration settings for the peripheral. + */ +typedef struct +{ + uint32_t rx_pin_no; /**< RX pin number. */ + uint32_t tx_pin_no; /**< TX pin number. */ + uint32_t rts_pin_no; /**< RTS pin number, only used if flow control is enabled. */ + uint32_t cts_pin_no; /**< CTS pin number, only used if flow control is enabled. */ + app_uart_flow_control_t flow_control; /**< Flow control setting, if flow control is used, the system will use low power UART mode, based on CTS signal. */ + bool use_parity; /**< Even parity if TRUE, no parity if FALSE. */ + uint32_t baud_rate; /**< Baud rate configuration. */ +} app_uart_comm_params_t; + +/**@brief UART buffer for transmitting/receiving data. + */ +typedef struct +{ + uint8_t * rx_buf; /**< Pointer to the RX buffer. */ + uint32_t rx_buf_size; /**< Size of the RX buffer. */ + uint8_t * tx_buf; /**< Pointer to the TX buffer. */ + uint32_t tx_buf_size; /**< Size of the TX buffer. */ +} app_uart_buffers_t; + +/**@brief Enumeration which defines events used by the UART module upon data reception or error. + * + * @details The event type is used to indicate the type of additional information in the event + * @ref app_uart_evt_t. + */ +typedef enum +{ + APP_UART_DATA_READY, /**< An event indicating that UART data has been received. The data is available in the FIFO and can be fetched using @ref app_uart_get. */ + APP_UART_FIFO_ERROR, /**< An error in the FIFO module used by the app_uart module has occured. The FIFO error code is stored in app_uart_evt_t.data.error_code field. */ + APP_UART_COMMUNICATION_ERROR, /**< An communication error has occured during reception. The error is stored in app_uart_evt_t.data.error_communication field. */ + APP_UART_TX_EMPTY, /**< An event indicating that UART has completed transmission of all available data in the TX FIFO. */ + APP_UART_DATA, /**< An event indicating that UART data has been received, and data is present in data field. This event is only used when no FIFO is configured. */ +} app_uart_evt_type_t; + +/**@brief Struct containing events from the UART module. + * + * @details The app_uart_evt_t is used to notify the application of asynchronous events when data + * are received on the UART peripheral or in case an error occured during data reception. + */ +typedef struct +{ + app_uart_evt_type_t evt_type; /**< Type of event. */ + union + { + uint32_t error_communication; /**< Field used if evt_type is: APP_UART_COMMUNICATION_ERROR. This field contains the value in the ERRORSRC register for the UART peripheral. The UART_ERRORSRC_x defines from nrf5x_bitfields.h can be used to parse the error code. See also the \nRFXX Series Reference Manual for specification. */ + uint32_t error_code; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ + uint8_t value; /**< Field used if evt_type is: NRF_ERROR_x. Additional status/error code if the error event type is APP_UART_FIFO_ERROR. This error code refer to errors defined in nrf_error.h. */ + } data; +} app_uart_evt_t; + +/**@brief Function for handling app_uart event callback. + * + * @details Upon an event in the app_uart module this callback function will be called to notify + * the application about the event. + * + * @param[in] p_app_uart_event Pointer to UART event. + */ +typedef void (* app_uart_event_handler_t) (app_uart_evt_t * p_app_uart_event); + +/**@brief Macro for safe initialization of the UART module in a single user instance when using + * a FIFO together with UART. + * + * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t + * @param[in] RX_BUF_SIZE Size of desired RX buffer, must be a power of 2 or ZERO (No FIFO). + * @param[in] TX_BUF_SIZE Size of desired TX buffer, must be a power of 2 or ZERO (No FIFO). + * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the + * UART module. + * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. + * @param[out] ERR_CODE The return value of the UART initialization function will be + * written to this parameter. + * + * @note Since this macro allocates a buffer and registers the module as a GPIOTE user when flow + * control is enabled, it must only be called once. + */ +#define APP_UART_FIFO_INIT(P_COMM_PARAMS, RX_BUF_SIZE, TX_BUF_SIZE, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ + do \ + { \ + app_uart_buffers_t buffers; \ + static uint8_t rx_buf[RX_BUF_SIZE]; \ + static uint8_t tx_buf[TX_BUF_SIZE]; \ + \ + buffers.rx_buf = rx_buf; \ + buffers.rx_buf_size = sizeof (rx_buf); \ + buffers.tx_buf = tx_buf; \ + buffers.tx_buf_size = sizeof (tx_buf); \ + ERR_CODE = app_uart_init(P_COMM_PARAMS, &buffers, EVT_HANDLER, IRQ_PRIO); \ + } while (0) + +/**@brief Macro for safe initialization of the UART module in a single user instance. + * + * @param[in] P_COMM_PARAMS Pointer to a UART communication structure: app_uart_comm_params_t + * @param[in] EVT_HANDLER Event handler function to be called when an event occurs in the + * UART module. + * @param[in] IRQ_PRIO IRQ priority, app_irq_priority_t, for the UART module irq handler. + * @param[out] ERR_CODE The return value of the UART initialization function will be + * written to this parameter. + * + * @note Since this macro allocates registers the module as a GPIOTE user when flow control is + * enabled, it must only be called once. + */ +#define APP_UART_INIT(P_COMM_PARAMS, EVT_HANDLER, IRQ_PRIO, ERR_CODE) \ + do \ + { \ + ERR_CODE = app_uart_init(P_COMM_PARAMS, NULL, EVT_HANDLER, IRQ_PRIO); \ + } while (0) + +/**@brief Function for initializing the UART module. Use this initialization when several instances of the UART + * module are needed. + * + * + * @note Normally single initialization should be done using the APP_UART_INIT() or + * APP_UART_INIT_FIFO() macro depending on whether the FIFO should be used by the UART, as + * that will allocate the buffers needed by the UART module (including aligning the buffer + * correctly). + + * @param[in] p_comm_params Pin and communication parameters. + * @param[in] p_buffers RX and TX buffers, NULL is FIFO is not used. + * @param[in] error_handler Function to be called in case of an error. + * @param[in] irq_priority Interrupt priority level. + * + * @retval NRF_SUCCESS If successful initialization. + * @retval NRF_ERROR_INVALID_LENGTH If a provided buffer is not a power of two. + * @retval NRF_ERROR_NULL If one of the provided buffers is a NULL pointer. + * + * The below errors are propagated by the UART module to the caller upon registration when Hardware + * Flow Control is enabled. When Hardware Flow Control is not used, these errors cannot occur. + * @retval NRF_ERROR_INVALID_STATE The GPIOTE module is not in a valid state when registering + * the UART module as a user. + * @retval NRF_ERROR_INVALID_PARAM The UART module provides an invalid callback function when + * registering the UART module as a user. + * Or the value pointed to by *p_uart_uid is not a valid + * GPIOTE number. + * @retval NRF_ERROR_NO_MEM GPIOTE module has reached the maximum number of users. + */ +uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, + app_uart_buffers_t * p_buffers, + app_uart_event_handler_t error_handler, + app_irq_priority_t irq_priority); + +/**@brief Function for getting a byte from the UART. + * + * @details This function will get the next byte from the RX buffer. If the RX buffer is empty + * an error code will be returned and the app_uart module will generate an event upon + * reception of the first byte which is added to the RX buffer. + * + * @param[out] p_byte Pointer to an address where next byte received on the UART will be copied. + * + * @retval NRF_SUCCESS If a byte has been received and pushed to the pointer provided. + * @retval NRF_ERROR_NOT_FOUND If no byte is available in the RX buffer of the app_uart module. + */ +uint32_t app_uart_get(uint8_t * p_byte); + +/**@brief Function for putting a byte on the UART. + * + * @details This call is non-blocking. + * + * @param[in] byte Byte to be transmitted on the UART. + * + * @retval NRF_SUCCESS If the byte was successfully put on the TX buffer for transmission. + * @retval NRF_ERROR_NO_MEM If no more space is available in the TX buffer. + * NRF_ERROR_NO_MEM may occur if flow control is enabled and CTS signal + * is high for a long period and the buffer fills up. + * @retval NRF_ERROR_INTERNAL If UART driver reported error. + */ +uint32_t app_uart_put(uint8_t byte); + +/**@brief Function for flushing the RX and TX buffers (Only valid if FIFO is used). + * This function does nothing if FIFO is not used. + * + * @retval NRF_SUCCESS Flushing completed (Current implementation will always succeed). + */ +uint32_t app_uart_flush(void); + +/**@brief Function for closing the UART module. + * + * @retval NRF_SUCCESS If successfully closed. + * @retval NRF_ERROR_INVALID_PARAM If an invalid user id is provided or the user id differs from + * the current active user. + */ +uint32_t app_uart_close(void); + + + +#ifdef __cplusplus +} +#endif + +#endif //APP_UART_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/uart/app_uart_fifo.c b/HAL_Driver/sdk/components/libraries/uart/app_uart_fifo.c new file mode 100644 index 0000000..23b1df2 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/uart/app_uart_fifo.c @@ -0,0 +1,244 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(APP_UART) +#include "app_uart.h" +#include "app_fifo.h" +#include "nrf_drv_uart.h" +#include "nrf_assert.h" + +static nrf_drv_uart_t app_uart_inst = NRF_DRV_UART_INSTANCE(APP_UART_DRIVER_INSTANCE); + +static __INLINE uint32_t fifo_length(app_fifo_t * const fifo) +{ + uint32_t tmp = fifo->read_pos; + return fifo->write_pos - tmp; +} + +#define FIFO_LENGTH(F) fifo_length(&F) /**< Macro to calculate length of a FIFO. */ + + +static app_uart_event_handler_t m_event_handler; /**< Event handler function. */ +static uint8_t tx_buffer[1]; +static uint8_t rx_buffer[1]; +static bool m_rx_ovf; + +static app_fifo_t m_rx_fifo; /**< RX FIFO buffer for storing data received on the UART until the application fetches them using app_uart_get(). */ +static app_fifo_t m_tx_fifo; /**< TX FIFO buffer for storing data to be transmitted on the UART when TXD is ready. Data is put to the buffer on using app_uart_put(). */ + +static void uart_event_handler(nrf_drv_uart_event_t * p_event, void* p_context) +{ + app_uart_evt_t app_uart_event; + uint32_t err_code; + + switch (p_event->type) + { + case NRF_DRV_UART_EVT_RX_DONE: + // Write received byte to FIFO. + err_code = app_fifo_put(&m_rx_fifo, p_event->data.rxtx.p_data[0]); + if (err_code != NRF_SUCCESS) + { + app_uart_event.evt_type = APP_UART_FIFO_ERROR; + app_uart_event.data.error_code = err_code; + m_event_handler(&app_uart_event); + } + // Notify that there are data available. + else if (FIFO_LENGTH(m_rx_fifo) != 0) + { + app_uart_event.evt_type = APP_UART_DATA_READY; + m_event_handler(&app_uart_event); + } + + // Start new RX if size in buffer. + if (FIFO_LENGTH(m_rx_fifo) <= m_rx_fifo.buf_size_mask) + { + (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); + } + else + { + // Overflow in RX FIFO. + m_rx_ovf = true; + } + + break; + + case NRF_DRV_UART_EVT_ERROR: + app_uart_event.evt_type = APP_UART_COMMUNICATION_ERROR; + app_uart_event.data.error_communication = p_event->data.error.error_mask; + (void)nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); + m_event_handler(&app_uart_event); + break; + + case NRF_DRV_UART_EVT_TX_DONE: + // Get next byte from FIFO. + if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) + { + (void)nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1); + } + else + { + // Last byte from FIFO transmitted, notify the application. + app_uart_event.evt_type = APP_UART_TX_EMPTY; + m_event_handler(&app_uart_event); + } + break; + + default: + break; + } +} + + +uint32_t app_uart_init(const app_uart_comm_params_t * p_comm_params, + app_uart_buffers_t * p_buffers, + app_uart_event_handler_t event_handler, + app_irq_priority_t irq_priority) +{ + uint32_t err_code; + + m_event_handler = event_handler; + + if (p_buffers == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Configure buffer RX buffer. + err_code = app_fifo_init(&m_rx_fifo, p_buffers->rx_buf, p_buffers->rx_buf_size); + VERIFY_SUCCESS(err_code); + + // Configure buffer TX buffer. + err_code = app_fifo_init(&m_tx_fifo, p_buffers->tx_buf, p_buffers->tx_buf_size); + VERIFY_SUCCESS(err_code); + + nrf_drv_uart_config_t config = NRF_DRV_UART_DEFAULT_CONFIG; + config.baudrate = (nrf_uart_baudrate_t)p_comm_params->baud_rate; + config.hwfc = (p_comm_params->flow_control == APP_UART_FLOW_CONTROL_DISABLED) ? + NRF_UART_HWFC_DISABLED : NRF_UART_HWFC_ENABLED; + config.interrupt_priority = irq_priority; + config.parity = p_comm_params->use_parity ? NRF_UART_PARITY_INCLUDED : NRF_UART_PARITY_EXCLUDED; + config.pselcts = p_comm_params->cts_pin_no; + config.pselrts = p_comm_params->rts_pin_no; + config.pselrxd = p_comm_params->rx_pin_no; + config.pseltxd = p_comm_params->tx_pin_no; + + err_code = nrf_drv_uart_init(&app_uart_inst, &config, uart_event_handler); + VERIFY_SUCCESS(err_code); + m_rx_ovf = false; + + // Turn on receiver if RX pin is connected + if (p_comm_params->rx_pin_no != UART_PIN_DISCONNECTED) + { + return nrf_drv_uart_rx(&app_uart_inst, rx_buffer,1); + } + else + { + return NRF_SUCCESS; + } +} + + +uint32_t app_uart_flush(void) +{ + uint32_t err_code; + + err_code = app_fifo_flush(&m_rx_fifo); + VERIFY_SUCCESS(err_code); + + err_code = app_fifo_flush(&m_tx_fifo); + VERIFY_SUCCESS(err_code); + + return NRF_SUCCESS; +} + + +uint32_t app_uart_get(uint8_t * p_byte) +{ + ASSERT(p_byte); + bool rx_ovf = m_rx_ovf; + + ret_code_t err_code = app_fifo_get(&m_rx_fifo, p_byte); + + // If FIFO was full new request to receive one byte was not scheduled. Must be done here. + if (rx_ovf) + { + m_rx_ovf = false; + uint32_t uart_err_code = nrf_drv_uart_rx(&app_uart_inst, rx_buffer, 1); + + // RX resume should never fail. + APP_ERROR_CHECK(uart_err_code); + } + + return err_code; +} + + +uint32_t app_uart_put(uint8_t byte) +{ + uint32_t err_code; + err_code = app_fifo_put(&m_tx_fifo, byte); + if (err_code == NRF_SUCCESS) + { + // The new byte has been added to FIFO. It will be picked up from there + // (in 'uart_event_handler') when all preceding bytes are transmitted. + // But if UART is not transmitting anything at the moment, we must start + // a new transmission here. + if (!nrf_drv_uart_tx_in_progress(&app_uart_inst)) + { + // This operation should be almost always successful, since we've + // just added a byte to FIFO, but if some bigger delay occurred + // (some heavy interrupt handler routine has been executed) since + // that time, FIFO might be empty already. + if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS) + { + err_code = nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1); + } + } + } + return err_code; +} + + +uint32_t app_uart_close(void) +{ + nrf_drv_uart_uninit(&app_uart_inst); + return NRF_SUCCESS; +} +#endif //NRF_MODULE_ENABLED(APP_UART) diff --git a/HAL_Driver/sdk/components/libraries/util/app_error.c b/HAL_Driver/sdk/components/libraries/util/app_error.c new file mode 100644 index 0000000..64e0386 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_error.c @@ -0,0 +1,125 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler. + */ + +#include "nrf.h" +#include +#include "app_error.h" +#include "nordic_common.h" +#include "sdk_errors.h" + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @warning This handler is an example only and does not fit a final product. You need to analyze + * how your product is supposed to react in case of error. + * + * @param[in] error_code Error code supplied to the handler. + * @param[in] line_num Line number where the handler is called. + * @param[in] p_file_name Pointer to the file name. + */ +void app_error_handler_bare(ret_code_t error_code) +{ + error_info_t error_info = + { + .line_num = 0, + .p_file_name = NULL, + .err_code = error_code, + }; + + app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); + + UNUSED_VARIABLE(error_info); +} + +void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info) +{ + /* static error variables - in order to prevent removal by optimizers */ + static volatile struct + { + uint32_t fault_id; + uint32_t pc; + uint32_t error_info; + assert_info_t * p_assert_info; + error_info_t * p_error_info; + ret_code_t err_code; + uint32_t line_num; + const uint8_t * p_file_name; + } m_error_data = {0}; + + // The following variable helps Keil keep the call stack visible, in addition, it can be set to + // 0 in the debugger to continue executing code after the error check. + volatile bool loop = true; + UNUSED_VARIABLE(loop); + + m_error_data.fault_id = id; + m_error_data.pc = pc; + m_error_data.error_info = info; + + switch (id) + { + case NRF_FAULT_ID_SDK_ASSERT: + m_error_data.p_assert_info = (assert_info_t *)info; + m_error_data.line_num = m_error_data.p_assert_info->line_num; + m_error_data.p_file_name = m_error_data.p_assert_info->p_file_name; + break; + + case NRF_FAULT_ID_SDK_ERROR: + m_error_data.p_error_info = (error_info_t *)info; + m_error_data.err_code = m_error_data.p_error_info->err_code; + m_error_data.line_num = m_error_data.p_error_info->line_num; + m_error_data.p_file_name = m_error_data.p_error_info->p_file_name; + break; + } + + UNUSED_VARIABLE(m_error_data); + + // If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger. + __disable_irq(); + while (loop); + + __enable_irq(); +} diff --git a/HAL_Driver/sdk/components/libraries/util/app_error.h b/HAL_Driver/sdk/components/libraries/util/app_error.h new file mode 100644 index 0000000..eab849e --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_error.h @@ -0,0 +1,192 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler and macros for utilizing a common error handler. + */ + +#ifndef APP_ERROR_H__ +#define APP_ERROR_H__ + + +#include +#include +#include +#include "nrf.h" +#include "sdk_errors.h" +#include "nordic_common.h" +#include "app_error_weak.h" +#ifdef ANT_STACK_SUPPORT_REQD +#include "ant_error.h" +#endif // ANT_STACK_SUPPORT_REQD + + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_FAULT_ID_SDK_RANGE_START (0x00004000) /**< The start of the range of error IDs defined in the SDK. */ + +/**@defgroup APP_ERROR_FAULT_IDS Fault ID types + * @{ */ +#define NRF_FAULT_ID_SDK_ERROR (NRF_FAULT_ID_SDK_RANGE_START + 1) /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */ +#define NRF_FAULT_ID_SDK_ASSERT (NRF_FAULT_ID_SDK_RANGE_START + 2) /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */ +/**@} */ + +/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR. + */ +typedef struct +{ + uint32_t line_num; /**< The line number where the error occurred. */ + uint8_t const * p_file_name; /**< The file in which the error occurred. */ + uint32_t err_code; /**< The error code representing the error that occurred. */ +} error_info_t; + +/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT. + */ +typedef struct +{ + uint16_t line_num; /**< The line number where the error occurred. */ + uint8_t const * p_file_name; /**< The file in which the error occurred. */ +} assert_info_t; + +/**@brief Defines required by app_error_handler assembler intructions. + */ +#define APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM (offsetof(error_info_t, line_num)) +#define APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME (offsetof(error_info_t, p_file_name)) +#define APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE (offsetof(error_info_t, err_code)) +#define APP_ERROR_ERROR_INFO_SIZE (sizeof(error_info_t)) +#define APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE \ + ALIGN_NUM(APP_ERROR_ERROR_INFO_SIZE, sizeof(uint64_t)) + + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @param[in] error_code Error code supplied to the handler. + * @param[in] line_num Line number where the handler is called. + * @param[in] p_file_name Pointer to the file name. + */ +void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); + +/**@brief Function for error handling, which is called when an error has occurred. + * + * @param[in] error_code Error code supplied to the handler. + */ +void app_error_handler_bare(ret_code_t error_code); + +/**@brief Function for saving the parameters and entering an eternal loop, for debug purposes. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info); + +/**@brief Function for logging details of error and flushing logs. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. Refer to each fault + * identifier for details. + */ +void app_error_log_handle(uint32_t id, uint32_t pc, uint32_t info); + + +/**@brief Macro for calling error handler function. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#ifdef DEBUG +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ + } while (0) +#else +#define APP_ERROR_HANDLER(ERR_CODE) \ + do \ + { \ + app_error_handler_bare((ERR_CODE)); \ + } while (0) +#endif +/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. + * + * @param[in] ERR_CODE Error code supplied to the error handler. + */ +#define APP_ERROR_CHECK(ERR_CODE) \ + do \ + { \ + const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ + if (LOCAL_ERR_CODE != NRF_SUCCESS) \ + { \ + APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ + } \ + } while (0) + +/**@brief Macro for calling error handler function if supplied boolean value is false. + * + * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. + */ +#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ + do \ + { \ + const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ + if (!LOCAL_BOOLEAN_VALUE) \ + { \ + APP_ERROR_HANDLER(0); \ + } \ + } while (0) + + +#ifdef __cplusplus +} +#endif + +#endif // APP_ERROR_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/util/app_error_handler_gcc.c b/HAL_Driver/sdk/components/libraries/util/app_error_handler_gcc.c new file mode 100644 index 0000000..2b6f18e --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_error_handler_gcc.c @@ -0,0 +1,101 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#include "compiler_abstraction.h" +#include "app_error.h" + +#if defined (__CORTEX_M) && (__CORTEX_M == 0x04) +void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) __attribute__(( naked )); + +void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) +{ + __ASM volatile( + + "push {lr} \n" + + /* reserve space on stack for error_info_t struct - preserve 8byte stack aligment */ + "sub sp, sp, %0 \n" + + /* prepare error_info_t struct */ + "str r0, [sp, %1] \n" + "str r1, [sp, %3] \n" + "str r2, [sp, %2] \n" + + /* prepare arguments and call function: app_error_fault_handler */ + "ldr r0, =%4 \n" + "mov r1, lr \n" + "mov r2, sp \n" + "bl %5 \n" + + /* release stack */ + "add sp, sp, %0 \n" + + "pop {pc} \n" + ".ltorg \n" + + : /* Outputs */ + : /* Inputs */ + "I" (APP_ERROR_ERROR_INFO_SIZE_ALIGNED_8BYTE), + "I" (APP_ERROR_ERROR_INFO_OFFSET_ERR_CODE), + "I" (APP_ERROR_ERROR_INFO_OFFSET_P_FILE_NAME), + "I" (APP_ERROR_ERROR_INFO_OFFSET_LINE_NUM), + "X" (NRF_FAULT_ID_SDK_ERROR), + "X" (app_error_fault_handler) + : /* Clobbers */ + "r0", "r1", "r2" + ); +} +#elif defined(__CORTEX_M) && (__CORTEX_M == 0x00) +/* NRF51 implementation is currently not supporting PC readout */ +void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name) +{ + error_info_t error_info = { + .line_num = line_num, + .p_file_name = p_file_name, + .err_code = error_code, + }; + app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info)); + + UNUSED_VARIABLE(error_info); +} +#else +#error Architecture not supported +#endif + diff --git a/HAL_Driver/sdk/components/libraries/util/app_error_weak.c b/HAL_Driver/sdk/components/libraries/util/app_error_weak.c new file mode 100644 index 0000000..e55bf0f --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_error_weak.c @@ -0,0 +1,110 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "app_error.h" + +#include "nrf_log.h" +#include "nrf_log_ctrl.h" +#include "app_util_platform.h" +#include "nrf_strerror.h" + +#if defined(SOFTDEVICE_PRESENT) && SOFTDEVICE_PRESENT +#include "nrf_sdm.h" +#endif + +/*lint -save -e14 */ +/** + * Function is implemented as weak so that it can be overwritten by custom application error handler + * when needed. + */ +__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info) +{ + __disable_irq(); + NRF_LOG_FINAL_FLUSH(); + +#ifndef DEBUG + NRF_LOG_ERROR("Fatal error"); +#else + switch (id) + { +#if defined(SOFTDEVICE_PRESENT) && SOFTDEVICE_PRESENT + case NRF_FAULT_ID_SD_ASSERT: + NRF_LOG_ERROR("SOFTDEVICE: ASSERTION FAILED"); + break; + case NRF_FAULT_ID_APP_MEMACC: + NRF_LOG_ERROR("SOFTDEVICE: INVALID MEMORY ACCESS"); + break; +#endif + case NRF_FAULT_ID_SDK_ASSERT: + { + assert_info_t * p_info = (assert_info_t *)info; + NRF_LOG_ERROR("ASSERTION FAILED at %s:%u", + p_info->p_file_name, + p_info->line_num); + break; + } + case NRF_FAULT_ID_SDK_ERROR: + { + error_info_t * p_info = (error_info_t *)info; + NRF_LOG_ERROR("ERROR %u [%s] at %s:%u\r\nPC at: 0x%08x", + p_info->err_code, + nrf_strerror_get(p_info->err_code), + p_info->p_file_name, + p_info->line_num, + pc); + NRF_LOG_ERROR("End of error report"); + break; + } + default: + NRF_LOG_ERROR("UNKNOWN FAULT at 0x%08X", pc); + break; + } +#endif + + NRF_BREAKPOINT_COND; + // On assert, the system can only recover with a reset. + +#ifndef DEBUG + NRF_LOG_WARNING("System reset"); + NVIC_SystemReset(); +#else + app_error_save_and_stop(id, pc, info); +#endif // DEBUG +} +/*lint -restore */ diff --git a/HAL_Driver/sdk/components/libraries/util/app_error_weak.h b/HAL_Driver/sdk/components/libraries/util/app_error_weak.h new file mode 100644 index 0000000..05d64f5 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_error_weak.h @@ -0,0 +1,87 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef APP_ERROR_WEAK_H__ +#define APP_ERROR_WEAK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @file + * + * @defgroup app_error Common application error handler + * @{ + * @ingroup app_common + * + * @brief Common application error handler. + */ + +/**@brief Callback function for errors, asserts, and faults. + * + * @details This function is called every time an error is raised in app_error, nrf_assert, or + * in the SoftDevice. Information about the error can be found in the @p info + * parameter. + * + * See also @ref nrf_fault_handler_t for more details. + * + * @note The function is implemented as weak so that it can be redefined by a custom error + * handler when needed. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault, or 0 if + * unavailable. + * @param[in] info Optional additional information regarding the fault. The value of the @p id + * parameter dictates how to interpret this parameter. Refer to the documentation + * for each fault identifier (@ref NRF_FAULT_IDS and @ref APP_ERROR_FAULT_IDS) for + * details about interpreting @p info. + */ +void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info); + + +/** @} */ + + +#ifdef __cplusplus +} +#endif + +#endif // APP_ERROR_WEAK_H__ diff --git a/HAL_Driver/sdk/components/libraries/util/app_util.h b/HAL_Driver/sdk/components/libraries/util/app_util.h new file mode 100644 index 0000000..31ac92b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_util.h @@ -0,0 +1,1321 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * + * @defgroup app_util Utility Functions and Definitions + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications. + */ + +#ifndef APP_UTIL_H__ +#define APP_UTIL_H__ + +#include +#include +#include +#include "compiler_abstraction.h" +#include "nordic_common.h" +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @cond (NODOX) + */ +/*lint -save -e27 -e10 -e19 */ +#if defined (__LINT__) +#define STACK_BASE 0x1F000 // Arbitrary value. +#define STACK_TOP 0x20000 // Arbitrary value. + +#elif defined ( __CC_ARM ) +extern char STACK$$Base; +extern char STACK$$Length; +#define STACK_BASE &STACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length)) + +#elif defined ( __ICCARM__ ) +extern char CSTACK$$Base; +extern char CSTACK$$Length; +#define STACK_BASE &CSTACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length)) + +#elif defined ( __GNUC__ ) +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +#define STACK_BASE &__StackLimit +#define STACK_TOP &__StackTop +#endif + +/* These macros are valid only when absolute placement is used for the application + * image. The macros are not compile time symbols. They cannot be used as a + * constant expression, for example, inside a static assert or linker script + * at-placement. */ +#if defined (__LINT__) +#define CODE_START (0) // Arbitrary value. +#define CODE_END (0x1000) // Arbitrary value. +#define CODE_SIZE (0x1000) // Arbitrary value. + +#elif defined ( __CC_ARM ) +extern char Load$$LR$$LR_IROM1$$Base; +extern char Load$$LR$$LR_IROM1$$Length; +extern char Load$$LR$$LR_IROM1$$Limit; +#define CODE_START ((uint32_t)&Load$$LR$$LR_IROM1$$Base) +#define CODE_END ((uint32_t)&Load$$LR$$LR_IROM1$$Limit) +#define CODE_SIZE ((uint32_t)&Load$$LR$$LR_IROM1$$Length) + +#elif defined ( __ICCARM__ ) +extern void * __vector_table; +extern char RO_END$$Base; +#define CODE_START ((uint32_t)&__vector_table) +#define CODE_END ((uint32_t)&RO_END$$Base) +#define CODE_SIZE (CODE_END - CODE_START) + +#elif defined(__SES_ARM) +extern uint32_t * _vectors; +extern uint32_t __FLASH_segment_used_end__; +#define CODE_START ((uint32_t)&_vectors) +#define CODE_END ((uint32_t)&__FLASH_segment_used_end__) +#define CODE_SIZE (CODE_END - CODE_START) + +#elif defined ( __GNUC__ ) +extern uint32_t __isr_vector; +extern uint32_t __etext; +#define CODE_START ((uint32_t)&__isr_vector) +#define CODE_END ((uint32_t)&__etext) +#define CODE_SIZE (CODE_END - CODE_START) +#endif +/** @} + * @endcond + */ +/* lint -restore */ + +#if defined(MBR_PRESENT) || defined(SOFTDEVICE_PRESENT) +#include "nrf_mbr.h" +#define BOOTLOADER_ADDRESS ((*(uint32_t *)MBR_BOOTLOADER_ADDR) == 0xFFFFFFFF ? *MBR_UICR_BOOTLOADER_ADDR : *(uint32_t *)MBR_BOOTLOADER_ADDR) /**< The currently configured start address of the bootloader. If 0xFFFFFFFF, no bootloader start address is configured. */ +#define MBR_PARAMS_PAGE_ADDRESS ((*(uint32_t *)MBR_PARAM_PAGE_ADDR) == 0xFFFFFFFF ? *MBR_UICR_PARAM_PAGE_ADDR : *(uint32_t *)MBR_PARAM_PAGE_ADDR) /**< The currently configured address of the MBR params page. If 0xFFFFFFFF, no MBR params page address is configured. */ +#else +#define BOOTLOADER_ADDRESS (NRF_UICR->NRFFW[0]) /**< Check UICR, just in case. */ +#define MBR_PARAMS_PAGE_ADDRESS (NRF_UICR->NRFFW[1]) /**< Check UICR, just in case. */ +#endif + +enum +{ + UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ + UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ + UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ +}; + +/** + * @brief Counts number of bits required for the given value + * + * The macro technically searches for the highest bit set. + * For value 0 it returns 0. + * + * @param val Value to be processed + * + * @return Number of bits required for the given value + */ +//lint -emacro(572,VBITS) +#define VBITS(val) VBITS_32(val) + +/** + * @def VBITS_1 + * @brief Internal macro used by @ref VBITS */ +/** + * @def VBITS_2 + * @brief Internal macro used by @ref VBITS */ +/** + * @def VBITS_4 + * @brief Internal macro used by @ref VBITS */ +/** + * @def VBITS_8 + * @brief Internal macro used by @ref VBITS */ +/** + * @def VBITS_16 + * @brief Internal macro used by @ref VBITS */ +/** + * @def VBITS_32 + * @brief Internal macro used by @ref VBITS */ +#define VBITS_1( v) ((((v) & (0x0001U << 0)) != 0) ? 1U : 0U) +#define VBITS_2( v) ((((v) & (0x0001U << 1)) != 0) ? VBITS_1 ((v) >> 1) + 1 : VBITS_1 (v)) +#define VBITS_4( v) ((((v) & (0x0003U << 2)) != 0) ? VBITS_2 ((v) >> 2) + 2 : VBITS_2 (v)) +#define VBITS_8( v) ((((v) & (0x000fU << 4)) != 0) ? VBITS_4 ((v) >> 4) + 4 : VBITS_4 (v)) +#define VBITS_16(v) ((((v) & (0x00ffU << 8)) != 0) ? VBITS_8 ((v) >> 8) + 8 : VBITS_8 (v)) +#define VBITS_32(v) ((((v) & (0xffffU << 16)) != 0) ? VBITS_16((v) >> 16) + 16 : VBITS_16(v)) + + +/*Segger embedded studio originally has offsetof macro which cannot be used in macros (like STATIC_ASSERT). + This redefinition is to allow using that. */ +#if defined(__SES_ARM) && defined(__GNUC__) +#undef offsetof +#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) +#endif + +/**@brief Implementation specific macro for delayed macro expansion used in string concatenation +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs + + +/**@brief Macro used to concatenate string using delayed macro expansion +* +* @note This macro will delay concatenation until the expressions have been resolved +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs) + + +#ifndef __LINT__ + +#ifdef __GNUC__ +#define STATIC_ASSERT_SIMPLE(EXPR) _Static_assert(EXPR, "unspecified message") +#define STATIC_ASSERT_MSG(EXPR, MSG) _Static_assert(EXPR, MSG) +#endif + +#ifdef __CC_ARM +#define STATIC_ASSERT_SIMPLE(EXPR) extern char (*_do_assert(void)) [sizeof(char[1 - 2*!(EXPR)])] +#define STATIC_ASSERT_MSG(EXPR, MSG) extern char (*_do_assert(void)) [sizeof(char[1 - 2*!(EXPR)])] +#endif + +#ifdef __ICCARM__ +#define STATIC_ASSERT_SIMPLE(EXPR) static_assert(EXPR, "unspecified message") +#define STATIC_ASSERT_MSG(EXPR, MSG) static_assert(EXPR, MSG) +#endif + +#else // __LINT__ + +#define STATIC_ASSERT_SIMPLE(EXPR) extern char (*_ignore(void)) +#define STATIC_ASSERT_MSG(EXPR, MSG) extern char (*_ignore(void)) + +#endif + + +#define _SELECT_ASSERT_FUNC(x, EXPR, MSG, ASSERT_MACRO, ...) ASSERT_MACRO + +/** + * @brief Static (i.e. compile time) assert macro. + * + * @note The output of STATIC_ASSERT can be different across compilers. + * + * Usage: + * STATIC_ASSERT(expression); + * STATIC_ASSERT(expression, message); + * + * @hideinitializer + */ +//lint -save -esym(???, STATIC_ASSERT) +#define STATIC_ASSERT(...) \ + _SELECT_ASSERT_FUNC(x, ##__VA_ARGS__, \ + STATIC_ASSERT_MSG(__VA_ARGS__), \ + STATIC_ASSERT_SIMPLE(__VA_ARGS__)) +//lint -restore + + +/**@brief Implementation details for NUM_VAR_ARGS */ +#define NUM_VA_ARGS_IMPL( \ + _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, N, ...) N + + +/**@brief Macro to get the number of arguments in a call variadic macro call + * + * param[in] ... List of arguments + * + * @retval Number of variadic arguments in the argument list + */ +#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61, \ + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ + 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ + 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ + 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ + 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ + 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) + +/**@brief Implementation details for NUM_VAR_ARGS */ +#define NUM_VA_ARGS_LESS_1_IMPL( \ + _ignored, \ + _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, N, ...) N + +/**@brief Macro to get the number of arguments in a call variadic macro call. + * First argument is not counted. + * + * param[in] ... List of arguments + * + * @retval Number of variadic arguments in the argument list + */ +#define NUM_VA_ARGS_LESS_1(...) NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61, \ + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ + 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ + 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ + 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ + 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ + 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~) + + +/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ +typedef uint8_t uint16_le_t[2]; + +/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ +typedef uint8_t uint32_le_t[4]; + +/**@brief Byte array type. */ +typedef struct +{ + uint16_t size; /**< Number of array entries. */ + uint8_t * p_data; /**< Pointer to array entries. */ +} uint8_array_t; + + +/**@brief Macro for performing rounded integer division (as opposed to truncating the result). + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Rounded (integer) result of dividing A by B. + */ +#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) + + +/**@brief Macro for checking if an integer is a power of two. + * + * @param[in] A Number to be tested. + * + * @return true if value is power of two. + * @return false if value not power of two. + */ +#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) + + +/**@brief Macro for converting milliseconds to ticks. + * + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. + */ +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) + + +/**@brief Macro for performing integer division, making sure the result is rounded up. + * + * @details One typical use for this is to compute the number of objects with size B is needed to + * hold A number of bytes. + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Integer result of dividing A by B, rounded up. + */ +#define CEIL_DIV(A, B) \ + (((A) + (B) - 1) / (B)) + + +/**@brief Macro for creating a buffer aligned to 4 bytes. + * + * @param[in] NAME Name of the buffor. + * @param[in] MIN_SIZE Size of this buffor (it will be rounded up to multiples of 4 bytes). + */ +#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))] + + +/**@brief Macro for calculating the number of words that are needed to hold a number of bytes. + * + * @details Adds 3 and divides by 4. + * + * @param[in] n_bytes The number of bytes. + * + * @return The number of words that @p n_bytes take up (rounded up). + */ +#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2) + + +/**@brief The number of bytes in a word. + */ +#define BYTES_PER_WORD (4) + + +/**@brief Macro for increasing a number to the nearest (larger) multiple of another number. + * + * @param[in] alignment The number to align to. + * @param[in] number The number to align (increase). + * + * @return The aligned (increased) @p number. + */ +#define ALIGN_NUM(alignment, number) (((number) - 1) + (alignment) - (((number) - 1) % (alignment))) + +/**@brief Macro for getting first of 2 parameters. + * + * @param[in] a1 First parameter. + * @param[in] a2 Second parameter. + */ +#define GET_ARG_1(a1, a2) a1 + +/**@brief Macro for getting second of 2 parameters. + * + * @param[in] a1 First parameter. + * @param[in] a2 Second parameter. + */ +#define GET_ARG_2(a1, a2) a2 + + +/**@brief Container of macro (borrowed from Linux kernel). + * + * This macro returns parent structure address basing on child member address. + * + * @param ptr Address of child type. + * @param type Type of parent structure. + * @param member Name of child field in parent structure. + * + * @return Parent structure address. + * */ +#define CONTAINER_OF(ptr, type, member) \ + (type *)((char *)ptr - offsetof(type, member)) + + +/** + * @brief Define Bit-field mask + * + * Macro that defined the mask with selected number of bits set, starting from + * provided bit number. + * + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + */ +#define BF_MASK(bcnt, boff) ( ((1U << (bcnt)) - 1U) << (boff) ) + +/** + * @brief Get bit-field + * + * Macro that extracts selected bit-field from provided value + * + * @param[in] val Value from which selected bit-field would be extracted + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + * + * @return Value of the selected bits + */ +#define BF_GET(val, bcnt, boff) ( ( (val) & BF_MASK((bcnt), (boff)) ) >> (boff) ) + +/** + * @brief Create bit-field value + * + * Value is masked and shifted to match given bit-field + * + * @param[in] val Value to set on bit-field + * @param[in] bcnt Number of bits for bit-field + * @param[in] boff Offset of bit-field + * + * @return Value positioned of given bit-field. + */ +#define BF_VAL(val, bcnt, boff) ( (((uint32_t)(val)) << (boff)) & BF_MASK(bcnt, boff) ) + +/** + * @name Configuration of complex bit-field + * + * @sa BF_CX + * @{ + */ +/** @brief Position of bit count in complex bit-field value */ +#define BF_CX_BCNT_POS 0U +/** @brief Mask of bit count in complex bit-field value */ +#define BF_CX_BCNT_MASK (0xffU << BF_CX_BCNT_POS) +/** @brief Position of bit position in complex bit-field value */ +#define BF_CX_BOFF_POS 8U +/** @brief Mask of bit position in complex bit-field value */ +#define BF_CX_BOFF_MASK (0xffU << BF_CX_BOFF_POS) +/** @} */ + +/** + * @brief Define complex bit-field + * + * Complex bit-field would contain its position and size in one number. + * @sa BF_CX_MASK + * @sa BF_CX_POS + * @sa BF_CX_GET + * + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + * + * @return The single number that describes the bit-field completely. + */ +#define BF_CX(bcnt, boff) ( ((((uint32_t)(bcnt)) << BF_CX_BCNT_POS) & BF_CX_BCNT_MASK) | ((((uint32_t)(boff)) << BF_CX_BOFF_POS) & BF_CX_BOFF_MASK) ) + +/** + * @brief Get number of bits in bit-field + * + * @sa BF_CX + * + * @param bf_cx Complex bit-field + * + * @return Number of bits in given bit-field + */ +#define BF_CX_BCNT(bf_cx) ( ((bf_cx) & BF_CX_BCNT_MASK) >> BF_CX_BCNT_POS ) + +/** + * @brief Get lowest bit number in the field + * + * @sa BF_CX + * + * @param[in] bf_cx Complex bit-field + * + * @return Lowest bit number in given bit-field + */ +#define BF_CX_BOFF(bf_cx) ( ((bf_cx) & BF_CX_BOFF_MASK) >> BF_CX_BOFF_POS ) + +/** + * @brief Get bit mask of the selected field + * + * @sa BF_CX + * + * @param[in] bf_cx Complex bit-field + * + * @return Mask of given bit-field + */ +#define BF_CX_MASK(bf_cx) BF_MASK(BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Get bit-field + * + * Macro that extracts selected bit-field from provided value. + * Bit-field is given as a complex value. + * + * @sa BF_CX + * @sa BF_GET + * + * @param[in] val Value from which selected bit-field would be extracted + * @param[in] bf_cx Complex bit-field + * + * @return Value of the selected bits. + */ +#define BF_CX_GET(val, bf_cx) BF_GET(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Create bit-field value + * + * Value is masked and shifted to match given bit-field. + * + * @param[in] val Value to set on bit-field + * @param[in] bf_cx Complex bit-field + * + * @return Value positioned of given bit-field. + */ +#define BF_CX_VAL(val, bf_cx) BF_VAL(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Extracting data from the brackets + * + * This macro get rid of brackets around the argument. + * It can be used to pass multiple arguments in logical one argument to a macro. + * Call it with arguments inside brackets: + * @code + * #define ARGUMENTS (a, b, c) + * BRACKET_EXTRACT(ARGUMENTS) + * @endcode + * It would produce: + * @code + * a, b, c + * @endcode + * + * @param a Argument with anything inside brackets + * @return Anything that appears inside the brackets of the argument + * + * @note + * The argument of the macro have to be inside brackets. + * In other case the compilation would fail. + */ +#define BRACKET_EXTRACT(a) BRACKET_EXTRACT_(a) +#define BRACKET_EXTRACT_(a) BRACKET_EXTRACT__ a +#define BRACKET_EXTRACT__(...) __VA_ARGS__ + + +/** + * @brief Check if number of parameters is more than 1 + * + * @param ... Arguments to count + * + * @return 0 If argument count is <= 1 + * @return 1 If argument count is > 1 + * + * @sa NUM_VA_ARGS + * @sa NUM_IS_MORE_THAN_1 + */ +#define NUM_VA_ARGS_IS_MORE_THAN_1(...) NUM_IS_MORE_THAN_1(NUM_VA_ARGS(__VA_ARGS__)) + +/** + * @brief Check if given numeric value is bigger than 1 + * + * This macro accepts numeric value, that may be the result of argument expansion. + * This numeric value is then converted to 0 if it is lover than 1 or to 1 if + * its value is higher than 1. + * The generated result can be used to glue it into other macro mnemonic name. + * + * @param N Numeric value to check + * + * @return 0 If argument is <= 1 + * @return 1 If argument is > 1 + * + * @note Any existing definition of a form NUM_IS_MORE_THAN_1_PROBE_[N] can + * broke the result of this macro + */ +#define NUM_IS_MORE_THAN_1(N) NUM_IS_MORE_THAN_1_(N) +#define NUM_IS_MORE_THAN_1_(N) NUM_IS_MORE_THAN_1_PROBE_(NUM_IS_MORE_THAN_1_PROBE_ ## N, 1) +#define NUM_IS_MORE_THAN_1_PROBE_(...) GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__)) +#define NUM_IS_MORE_THAN_1_PROBE_0 ~, 0 +#define NUM_IS_MORE_THAN_1_PROBE_1 ~, 0 + +/** + * @brief Get the first argument + * + * @param ... Arguments to select + * + * @return First argument or empty if no arguments are provided + */ +#define GET_VA_ARG_1(...) GET_VA_ARG_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works +#define GET_VA_ARG_1_(a1, ...) a1 + +/** + * @brief Get all the arguments but the first one + * + * @param ... Arguments to select + * + * @return All arguments after the first one or empty if less than 2 arguments are provided + */ +#define GET_ARGS_AFTER_1(...) GET_ARGS_AFTER_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works +#define GET_ARGS_AFTER_1_(a1, ...) __VA_ARGS__ + +/** + * @brief Size of a field in declared structure + * + * Macro that returns the size of the structure field. + * @param struct_type Variable type to get the field size from + * @param field Field name to analyze. It can be even field inside field (field.somethingelse.and_another). + * + * @return Size of the field + */ +#define FIELD_SIZE(struct_type, field) sizeof(((struct struct_type*)NULL)->field) + +/** + * @brief Number of elements in field array in declared structure + * + * Macro that returns number of elementy in structure field. + * @param struct_type Variable type to get the field size from + * @param field Field name to analyze. + * + * @return Number of elements in field array + * + * @sa FIELD_SIZE + */ +#define FIELD_ARRAY_SIZE(struct_type, field) (FIELD_SIZE(struct_type, field) / FIELD_SIZE(struct_type, field[0])) + +/** + * @brief Mapping macro + * + * Macro that process all arguments using given macro + * + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP(...) MACRO_MAP_(__VA_ARGS__) +#define MACRO_MAP_(...) MACRO_MAP_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total + +/** + * @brief Mapping macro, recursive version + * + * Can be used in @ref MACRO_MAP macro + */ +#define MACRO_MAP_REC(...) MACRO_MAP_REC_(__VA_ARGS__) +#define MACRO_MAP_REC_(...) MACRO_MAP_REC_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total +/** + * @brief Mapping N arguments macro + * + * Macro similar to @ref MACRO_MAP but maps exact number of arguments. + * If there is more arguments given, the rest would be ignored. + * + * @param N Number of arguments to map + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument) + * + * @return Selected number of arguments processed by given macro + */ +#define MACRO_MAP_N(N, ...) MACRO_MAP_N_(N, __VA_ARGS__) +#define MACRO_MAP_N_(N, ...) CONCAT_2(MACRO_MAP_, N)(__VA_ARGS__, ) + +/** + * @brief Mapping N arguments macro, recursive version + * + * Can be used in @ref MACRO_MAP_N macro + */ +#define MACRO_MAP_REC_N(N, ...) MACRO_MAP_REC_N_(N, __VA_ARGS__) +#define MACRO_MAP_REC_N_(N, ...) CONCAT_2(MACRO_MAP_REC_, N)(__VA_ARGS__, ) + +#define MACRO_MAP_0( ...) +#define MACRO_MAP_1( macro, a, ...) macro(a) +#define MACRO_MAP_2( macro, a, ...) macro(a) MACRO_MAP_1 (macro, __VA_ARGS__, ) +#define MACRO_MAP_3( macro, a, ...) macro(a) MACRO_MAP_2 (macro, __VA_ARGS__, ) +#define MACRO_MAP_4( macro, a, ...) macro(a) MACRO_MAP_3 (macro, __VA_ARGS__, ) +#define MACRO_MAP_5( macro, a, ...) macro(a) MACRO_MAP_4 (macro, __VA_ARGS__, ) +#define MACRO_MAP_6( macro, a, ...) macro(a) MACRO_MAP_5 (macro, __VA_ARGS__, ) +#define MACRO_MAP_7( macro, a, ...) macro(a) MACRO_MAP_6 (macro, __VA_ARGS__, ) +#define MACRO_MAP_8( macro, a, ...) macro(a) MACRO_MAP_7 (macro, __VA_ARGS__, ) +#define MACRO_MAP_9( macro, a, ...) macro(a) MACRO_MAP_8 (macro, __VA_ARGS__, ) +#define MACRO_MAP_10(macro, a, ...) macro(a) MACRO_MAP_9 (macro, __VA_ARGS__, ) +#define MACRO_MAP_11(macro, a, ...) macro(a) MACRO_MAP_10(macro, __VA_ARGS__, ) +#define MACRO_MAP_12(macro, a, ...) macro(a) MACRO_MAP_11(macro, __VA_ARGS__, ) +#define MACRO_MAP_13(macro, a, ...) macro(a) MACRO_MAP_12(macro, __VA_ARGS__, ) +#define MACRO_MAP_14(macro, a, ...) macro(a) MACRO_MAP_13(macro, __VA_ARGS__, ) +#define MACRO_MAP_15(macro, a, ...) macro(a) MACRO_MAP_14(macro, __VA_ARGS__, ) +#define MACRO_MAP_16(macro, a, ...) macro(a) MACRO_MAP_15(macro, __VA_ARGS__, ) +#define MACRO_MAP_17(macro, a, ...) macro(a) MACRO_MAP_16(macro, __VA_ARGS__, ) +#define MACRO_MAP_18(macro, a, ...) macro(a) MACRO_MAP_17(macro, __VA_ARGS__, ) +#define MACRO_MAP_19(macro, a, ...) macro(a) MACRO_MAP_18(macro, __VA_ARGS__, ) +#define MACRO_MAP_20(macro, a, ...) macro(a) MACRO_MAP_19(macro, __VA_ARGS__, ) +#define MACRO_MAP_21(macro, a, ...) macro(a) MACRO_MAP_20(macro, __VA_ARGS__, ) +#define MACRO_MAP_22(macro, a, ...) macro(a) MACRO_MAP_21(macro, __VA_ARGS__, ) +#define MACRO_MAP_23(macro, a, ...) macro(a) MACRO_MAP_22(macro, __VA_ARGS__, ) +#define MACRO_MAP_24(macro, a, ...) macro(a) MACRO_MAP_23(macro, __VA_ARGS__, ) +#define MACRO_MAP_25(macro, a, ...) macro(a) MACRO_MAP_24(macro, __VA_ARGS__, ) +#define MACRO_MAP_26(macro, a, ...) macro(a) MACRO_MAP_25(macro, __VA_ARGS__, ) +#define MACRO_MAP_27(macro, a, ...) macro(a) MACRO_MAP_26(macro, __VA_ARGS__, ) +#define MACRO_MAP_28(macro, a, ...) macro(a) MACRO_MAP_27(macro, __VA_ARGS__, ) +#define MACRO_MAP_29(macro, a, ...) macro(a) MACRO_MAP_28(macro, __VA_ARGS__, ) +#define MACRO_MAP_30(macro, a, ...) macro(a) MACRO_MAP_29(macro, __VA_ARGS__, ) +#define MACRO_MAP_31(macro, a, ...) macro(a) MACRO_MAP_30(macro, __VA_ARGS__, ) +#define MACRO_MAP_32(macro, a, ...) macro(a) MACRO_MAP_31(macro, __VA_ARGS__, ) + + +#define MACRO_MAP_REC_0( ...) +#define MACRO_MAP_REC_1( macro, a, ...) macro(a) +#define MACRO_MAP_REC_2( macro, a, ...) macro(a) MACRO_MAP_REC_1 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_3( macro, a, ...) macro(a) MACRO_MAP_REC_2 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_4( macro, a, ...) macro(a) MACRO_MAP_REC_3 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_5( macro, a, ...) macro(a) MACRO_MAP_REC_4 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_6( macro, a, ...) macro(a) MACRO_MAP_REC_5 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_7( macro, a, ...) macro(a) MACRO_MAP_REC_6 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_8( macro, a, ...) macro(a) MACRO_MAP_REC_7 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_9( macro, a, ...) macro(a) MACRO_MAP_REC_8 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_10(macro, a, ...) macro(a) MACRO_MAP_REC_9 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_11(macro, a, ...) macro(a) MACRO_MAP_REC_10(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_12(macro, a, ...) macro(a) MACRO_MAP_REC_11(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_13(macro, a, ...) macro(a) MACRO_MAP_REC_12(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_14(macro, a, ...) macro(a) MACRO_MAP_REC_13(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_15(macro, a, ...) macro(a) MACRO_MAP_REC_14(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_16(macro, a, ...) macro(a) MACRO_MAP_REC_15(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_17(macro, a, ...) macro(a) MACRO_MAP_REC_16(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_18(macro, a, ...) macro(a) MACRO_MAP_REC_17(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_19(macro, a, ...) macro(a) MACRO_MAP_REC_18(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_20(macro, a, ...) macro(a) MACRO_MAP_REC_19(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_21(macro, a, ...) macro(a) MACRO_MAP_REC_20(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_22(macro, a, ...) macro(a) MACRO_MAP_REC_21(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_23(macro, a, ...) macro(a) MACRO_MAP_REC_22(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_24(macro, a, ...) macro(a) MACRO_MAP_REC_23(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_25(macro, a, ...) macro(a) MACRO_MAP_REC_24(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_26(macro, a, ...) macro(a) MACRO_MAP_REC_25(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_27(macro, a, ...) macro(a) MACRO_MAP_REC_26(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_28(macro, a, ...) macro(a) MACRO_MAP_REC_27(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_29(macro, a, ...) macro(a) MACRO_MAP_REC_28(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_30(macro, a, ...) macro(a) MACRO_MAP_REC_29(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_31(macro, a, ...) macro(a) MACRO_MAP_REC_30(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_32(macro, a, ...) macro(a) MACRO_MAP_REC_31(macro, __VA_ARGS__, ) + + +/** + * @brief Mapping macro with current index + * + * Basically macro similar to @ref MACRO_MAP, but the processing function would get an argument + * and current argument index (beginning from 0). + * + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index) + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR(...) MACRO_MAP_FOR_(__VA_ARGS__) +#define MACRO_MAP_FOR_N_LIST 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, \ + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 +#define MACRO_MAP_FOR_(...) MACRO_MAP_FOR_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) + +/** + * @brief Mapping N arguments macro with current index + * + * Macro is similar to @ref MACRO_MAP_FOR but maps exact number of arguments. + * If there is more arguments given, the rest would be ignored. + * + * @param N Number of arguments to map + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index) + * + * @return Selected number of arguments processed by given macro + */ +#define MACRO_MAP_FOR_N(N, ...) MACRO_MAP_FOR_N_(N, __VA_ARGS__) +#define MACRO_MAP_FOR_N_(N, ...) CONCAT_2(MACRO_MAP_FOR_, N)((MACRO_MAP_FOR_N_LIST), __VA_ARGS__, ) + +#define MACRO_MAP_FOR_0( n_list, ...) +#define MACRO_MAP_FOR_1( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) +#define MACRO_MAP_FOR_2( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_3( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_4( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_5( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_6( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_7( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_8( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_9( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_10(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_11(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_12(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_13(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_14(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_15(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_16(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_15((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_17(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_16((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_18(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_17((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_19(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_18((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_20(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_19((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_21(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_20((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_22(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_21((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_23(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_22((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_24(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_23((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_25(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_24((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_26(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_25((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_27(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_26((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_28(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_27((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_29(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_28((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_30(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_29((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_31(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_30((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_32(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_31((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) + + +/** + * @brief Mapping macro with current index and parameter + * + * Version of @ref MACRO_MAP_FOR that passes also the same parameter to all macros. + * + * @param param Parameter that would be passed to each macro call during mapping. + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index, param) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR_PARAM(param, ...) MACRO_MAP_FOR_PARAM_(param, __VA_ARGS__) +#define MACRO_MAP_FOR_PARAM_(param, ...) MACRO_MAP_FOR_PARAM_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), param, __VA_ARGS__) + +/** + * @brief Mapping N arguments macro with with current index and parameter + * + * @param N Number of arguments to map + * @param param Parameter that would be passed to each macro call during mapping. + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index, param) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR_PARAM_N(N, param, ...) MACRO_MAP_FOR_PARAM_N_(N, param, __VA_ARGS__) +#define MACRO_MAP_FOR_PARAM_N_(N, param, ...) CONCAT_2(MACRO_MAP_FOR_PARAM_, N)((MACRO_MAP_FOR_N_LIST), param, __VA_ARGS__, ) + + +#define MACRO_MAP_FOR_PARAM_0( n_list, param, ...) +#define MACRO_MAP_FOR_PARAM_1( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) +#define MACRO_MAP_FOR_PARAM_2( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_3( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_4( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_5( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_6( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_7( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_8( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_9( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_10(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_11(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_12(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_13(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_14(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_15(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_16(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_15((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_17(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_16((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_18(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_17((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_19(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_18((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_20(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_19((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_21(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_20((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_22(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_21((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_23(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_22((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_24(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_23((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_25(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_24((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_26(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_25((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_27(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_26((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_28(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_27((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_29(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_28((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_30(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_29((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_31(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_30((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_32(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_31((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) + + + +/** + * @brief Repeating macro. + * + * @param count Count of repeats. + * @param macro Macro must have the following form: MACRO(arguments). + * @param ... Arguments passed to the macro. + * + * @return All arguments processed by the given macro. + */ +#define MACRO_REPEAT(count, macro, ...) MACRO_REPEAT_(count, macro, __VA_ARGS__) +#define MACRO_REPEAT_(count, macro, ...) CONCAT_2(MACRO_REPEAT_, count)(macro, __VA_ARGS__) + +#define MACRO_REPEAT_0(macro, ...) +#define MACRO_REPEAT_1(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_0(macro, __VA_ARGS__) +#define MACRO_REPEAT_2(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_1(macro, __VA_ARGS__) +#define MACRO_REPEAT_3(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_2(macro, __VA_ARGS__) +#define MACRO_REPEAT_4(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_3(macro, __VA_ARGS__) +#define MACRO_REPEAT_5(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_4(macro, __VA_ARGS__) +#define MACRO_REPEAT_6(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_5(macro, __VA_ARGS__) +#define MACRO_REPEAT_7(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_6(macro, __VA_ARGS__) +#define MACRO_REPEAT_8(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_7(macro, __VA_ARGS__) +#define MACRO_REPEAT_9(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_8(macro, __VA_ARGS__) +#define MACRO_REPEAT_10(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_9(macro, __VA_ARGS__) +#define MACRO_REPEAT_11(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_10(macro, __VA_ARGS__) +#define MACRO_REPEAT_12(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_11(macro, __VA_ARGS__) +#define MACRO_REPEAT_13(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_12(macro, __VA_ARGS__) +#define MACRO_REPEAT_14(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_13(macro, __VA_ARGS__) +#define MACRO_REPEAT_15(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_14(macro, __VA_ARGS__) +#define MACRO_REPEAT_16(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_15(macro, __VA_ARGS__) +#define MACRO_REPEAT_17(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_16(macro, __VA_ARGS__) +#define MACRO_REPEAT_18(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_17(macro, __VA_ARGS__) +#define MACRO_REPEAT_19(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_18(macro, __VA_ARGS__) +#define MACRO_REPEAT_20(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_19(macro, __VA_ARGS__) +#define MACRO_REPEAT_21(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_20(macro, __VA_ARGS__) +#define MACRO_REPEAT_22(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_21(macro, __VA_ARGS__) +#define MACRO_REPEAT_23(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_22(macro, __VA_ARGS__) +#define MACRO_REPEAT_24(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_23(macro, __VA_ARGS__) +#define MACRO_REPEAT_25(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_24(macro, __VA_ARGS__) +#define MACRO_REPEAT_26(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_25(macro, __VA_ARGS__) +#define MACRO_REPEAT_27(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_26(macro, __VA_ARGS__) +#define MACRO_REPEAT_28(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_27(macro, __VA_ARGS__) +#define MACRO_REPEAT_29(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_28(macro, __VA_ARGS__) +#define MACRO_REPEAT_30(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_29(macro, __VA_ARGS__) +#define MACRO_REPEAT_31(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_30(macro, __VA_ARGS__) +#define MACRO_REPEAT_32(macro, ...) macro(__VA_ARGS__) MACRO_REPEAT_31(macro, __VA_ARGS__) + + +/** + * @brief Repeating macro with current index. + * + * Macro similar to @ref MACRO_REPEAT but the processing function gets the arguments + * and the current argument index (beginning from 0). + + * @param count Count of repeats. + * @param macro Macro must have the following form: MACRO(index, arguments). + * @param ... Arguments passed to the macro. + * + * @return All arguments processed by the given macro. + */ +#define MACRO_REPEAT_FOR(count, macro, ...) MACRO_REPEAT_FOR_(count, macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_(count, macro, ...) CONCAT_2(MACRO_REPEAT_FOR_, count)((MACRO_MAP_FOR_N_LIST), macro, __VA_ARGS__) + +#define MACRO_REPEAT_FOR_0(n_list, macro, ...) +#define MACRO_REPEAT_FOR_1(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_0((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_2(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_1((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_3(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_2((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_4(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_3((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_5(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_4((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_6(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_5((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_7(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_6((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_8(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_7((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_9(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_8((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_10(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_9((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_11(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_12(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_13(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_14(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_15(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_16(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_15((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_17(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_16((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_18(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_17((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_19(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_18((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_20(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_19((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_21(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_20((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_22(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_21((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_23(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_22((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_24(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_23((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_25(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_24((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_26(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_25((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_27(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_26((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_28(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_27((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_29(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_28((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_30(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_29((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_31(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_30((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) +#define MACRO_REPEAT_FOR_32(n_list, macro, ...) macro(GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), __VA_ARGS__) MACRO_REPEAT_FOR_31((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__) + + +/**@brief Adding curly brace to the macro parameter. + * + * Useful in array of structures initialization. + * + * @param p Parameter to put into the curly brace. */ +#define PARAM_CBRACE(p) { p }, + + +/**@brief Function for changing the value unit. + * + * @param[in] value Value to be rescaled. + * @param[in] old_unit_reversal Reversal of the incoming unit. + * @param[in] new_unit_reversal Reversal of the desired unit. + * + * @return Number of bytes written. + */ +static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal) +{ + return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal); +} + +/**@brief Function for encoding a uint16 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); + return sizeof(uint16_t); +} + +/**@brief Function for encoding a three-byte value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + return 3; +} + +/**@brief Function for encoding a uint32 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); + return sizeof(uint32_t); +} + +/**@brief Function for encoding a uint40 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint40_encode(uint64_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x00000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x000000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x0000FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0x00FF000000) >> 24); + p_encoded_data[4] = (uint8_t) ((value & 0xFF00000000) >> 32); + return 5; +} + +/**@brief Function for encoding a uint48 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24); + p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32); + p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40); + return 6; +} + +/**@brief Function for decoding a uint16 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | + (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); +} + +/**@brief Function for decoding a uint16 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) | + (((uint16_t)((uint8_t *)p_encoded_data)[1])) ); +} + +/**@brief Function for decoding a three-byte value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value (uint32_t). + */ +static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16)); +} + +/**@brief Function for decoding a uint32 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); +} + +/**@brief Function for decoding a uint32 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) ); +} + +/** + * @brief Function for encoding an uint16 value in big-endian format. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data will be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_big_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) (value >> 8); + p_encoded_data[1] = (uint8_t) (value & 0xFF); + + return sizeof(uint16_t); +} + +/*lint -esym(526, __rev) */ +/*lint -esym(628, __rev) */ +/**@brief Function for encoding a uint32 value in big-endian format. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data will be written. + * The address pointed to must be word alligned. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data) +{ + *(uint32_t *)p_encoded_data = __REV(value); + return sizeof(uint32_t); +} + +/**@brief Function for decoding a uint40 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. (uint64_t) + */ +static __INLINE uint64_t uint40_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | + (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 )); +} + +/**@brief Function for decoding a uint48 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. (uint64_t) + */ +static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | + (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) | + (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 )); +} + +/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. + * + * @details The calculation is based on a linearized version of the battery's discharge + * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and + * is considered to be the lower boundary. + * + * The discharge curve for CR2032 is non-linear. In this model it is split into + * 4 linear sections: + * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) + * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) + * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) + * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) + * + * These numbers are by no means accurate. Temperature and + * load in the actual application is not accounted for! + * + * @param[in] mvolts The voltage in mV + * + * @return Battery level in percent. +*/ +static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) +{ + uint8_t battery_level; + + if (mvolts >= 3000) + { + battery_level = 100; + } + else if (mvolts > 2900) + { + battery_level = 100 - ((3000 - mvolts) * 58) / 100; + } + else if (mvolts > 2740) + { + battery_level = 42 - ((2900 - mvolts) * 24) / 160; + } + else if (mvolts > 2440) + { + battery_level = 18 - ((2740 - mvolts) * 12) / 300; + } + else if (mvolts > 2100) + { + battery_level = 6 - ((2440 - mvolts) * 6) / 340; + } + else + { + battery_level = 0; + } + + return battery_level; +} + +/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. + * + * @param[in] p Pointer value to be checked. + * + * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. + */ +static __INLINE bool is_word_aligned(void const* p) +{ + return (((uintptr_t)p & 0x03) == 0); +} + +/*lint -e{568, 685} */ +/** + * @brief Function for checking if provided address is located in stack space. + * + * @param[in] ptr Pointer to be checked. + * + * @return true if address is in stack space, false otherwise. + */ +static __INLINE bool is_address_from_stack(void * ptr) +{ + if (((uint32_t)ptr >= (uint32_t)STACK_BASE) && + ((uint32_t)ptr < (uint32_t)STACK_TOP) ) + { + return true; + } + else + { + return false; + } +} + +#ifdef __cplusplus +} +#endif + +#endif // APP_UTIL_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/util/app_util_platform.c b/HAL_Driver/sdk/components/libraries/util/app_util_platform.c new file mode 100644 index 0000000..663e50f --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_util_platform.c @@ -0,0 +1,127 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "app_util_platform.h" + +#ifdef SOFTDEVICE_PRESENT +/* Global nvic state instance, required by nrf_nvic.h */ +nrf_nvic_state_t nrf_nvic_state; +#endif + +static uint32_t m_in_critical_region = 0; + +void app_util_disable_irq(void) +{ + __disable_irq(); + m_in_critical_region++; +} + +void app_util_enable_irq(void) +{ + m_in_critical_region--; + if (m_in_critical_region == 0) + { + __enable_irq(); + } +} + +void app_util_critical_region_enter(uint8_t *p_nested) +{ +#if __CORTEX_M == (0x04U) + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_enter(p_nested); +#else + app_util_disable_irq(); +#endif +} + +void app_util_critical_region_exit(uint8_t nested) +{ +#if __CORTEX_M == (0x04U) + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_exit(nested); +#else + app_util_enable_irq(); +#endif +} + + +uint8_t privilege_level_get(void) +{ +#if __CORTEX_M == (0x00U) || defined(_WIN32) || defined(__unix) || defined(__APPLE__) + /* the Cortex-M0 has no concept of privilege */ + return APP_LEVEL_PRIVILEGED; +#elif __CORTEX_M == (0x04U) + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (0 == isr_vector_num) + { + /* Thread Mode, check nPRIV */ + int32_t control = __get_CONTROL(); + return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED; + } + else + { + /* Handler Mode, always privileged */ + return APP_LEVEL_PRIVILEGED; + } +#endif +} + + +uint8_t current_int_priority_get(void) +{ + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (isr_vector_num > 0) + { + int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); + return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); + } + else + { + return APP_IRQ_PRIORITY_THREAD; + } +} diff --git a/HAL_Driver/sdk/components/libraries/util/app_util_platform.h b/HAL_Driver/sdk/components/libraries/util/app_util_platform.h new file mode 100644 index 0000000..58559af --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/app_util_platform.h @@ -0,0 +1,279 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup app_util_platform Utility Functions and Definitions (Platform) + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications when using SoftDevice. + */ + +#ifndef APP_UTIL_PLATFORM_H__ +#define APP_UTIL_PLATFORM_H__ + +#include +#include "compiler_abstraction.h" +#include "nrf.h" +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#include "nrf_nvic.h" +#endif +#include "nrf_assert.h" +#include "app_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if __CORTEX_M == (0x00U) +#define _PRIO_SD_HIGH 0 +#define _PRIO_APP_HIGH 1 +#define _PRIO_APP_MID 1 +#define _PRIO_SD_LOW 2 +#define _PRIO_APP_LOW 3 +#define _PRIO_APP_LOWEST 3 +#define _PRIO_THREAD 4 +#elif __CORTEX_M == (0x04U) +#define _PRIO_SD_HIGH 0 +#define _PRIO_SD_MID 1 +#define _PRIO_APP_HIGH 2 +#define _PRIO_APP_MID 3 +#define _PRIO_SD_LOW 4 +#define _PRIO_SD_LOWEST 5 +#define _PRIO_APP_LOW 6 +#define _PRIO_APP_LOWEST 7 +#define _PRIO_THREAD 15 +#else + #error "No platform defined" +#endif + + +//lint -save -e113 -e452 +/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ +typedef enum +{ +#ifndef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH, +#else + APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH, +#endif + APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH, +#ifndef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW, +#else + APP_IRQ_PRIORITY_MID = _PRIO_APP_MID, +#endif + APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW, + APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST, + APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */ +} app_irq_priority_t; +//lint -restore + + +/*@brief The privilege levels available to applications in Thread Mode */ +typedef enum +{ + APP_LEVEL_UNPRIVILEGED, + APP_LEVEL_PRIVILEGED +} app_level_t; + +/**@cond NO_DOXYGEN */ +#define EXTERNAL_INT_VECTOR_OFFSET 16 +/**@endcond */ + +/**@brief Macro for setting a breakpoint. + */ +#if defined(__GNUC__) +#define NRF_BREAKPOINT __asm__("BKPT 0"); +#else +#define NRF_BREAKPOINT __BKPT(0) +#endif + +/** @brief Macro for setting a breakpoint. + * + * If it is possible to detect debugger presence then it is set only in that case. + * + */ +#if __CORTEX_M == 0x04 +#define NRF_BREAKPOINT_COND do { \ + /* C_DEBUGEN == 1 -> Debugger Connected */ \ + if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) \ + { \ + /* Generate breakpoint if debugger is connected */ \ + NRF_BREAKPOINT; \ + } \ + }while (0) +#else +#define NRF_BREAKPOINT_COND NRF_BREAKPOINT +#endif // __CORTEX_M == 0x04 + +#if defined ( __CC_ARM ) +#define PACKED(TYPE) __packed TYPE +#define PACKED_STRUCT PACKED(struct) +#elif defined ( __GNUC__ ) +#define PACKED __attribute__((packed)) +#define PACKED_STRUCT struct PACKED +#elif defined (__ICCARM__) +#define PACKED_STRUCT __packed struct +#endif + +#if defined ( __CC_ARM ) +#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma ("push") \ + _Pragma ("O3") +#define PRAGMA_OPTIMIZATION_FORCE_END _Pragma ("pop") +#elif defined ( __GNUC__ ) +#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma("GCC push_options") \ + _Pragma ("GCC optimize (\"Os\")") +#define PRAGMA_OPTIMIZATION_FORCE_END _Pragma ("GCC pop_options") +#elif defined (__ICCARM__) +#define PRAGMA_OPTIMIZATION_FORCE_START _Pragma ("optimize=high z") +#define PRAGMA_OPTIMIZATION_FORCE_END +#endif + + +void app_util_critical_region_enter (uint8_t *p_nested); +void app_util_critical_region_exit (uint8_t nested); + +/**@brief Macro for entering a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_ENTER() \ + { \ + uint8_t __CR_NESTED = 0; \ + app_util_critical_region_enter(&__CR_NESTED); +#else +#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL) +#endif + +/**@brief Macro for leaving a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_EXIT() \ + app_util_critical_region_exit(__CR_NESTED); \ + } +#else +#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0) +#endif + +/* Workaround for Keil 4 */ +#ifndef IPSR_ISR_Msk +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +#endif + + + +/**@brief Macro to enable anonymous unions from a certain point in the code. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_ENABLE _Pragma("push") \ + _Pragma("anon_unions") \ + struct semicolon_swallower +#elif defined(__ICCARM__) + #define ANON_UNIONS_ENABLE _Pragma("language=extended") \ + struct semicolon_swallower +#else + #define ANON_UNIONS_ENABLE struct semicolon_swallower + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + +/**@brief Macro to disable anonymous unions from a certain point in the code. + * @note Call only after first calling @ref ANON_UNIONS_ENABLE. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_DISABLE _Pragma("pop") \ + struct semicolon_swallower +#elif defined(__ICCARM__) + #define ANON_UNIONS_DISABLE struct semicolon_swallower + // for IAR leave anonymous unions enabled +#else + #define ANON_UNIONS_DISABLE struct semicolon_swallower + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + +/**@brief Macro for adding pragma directive only for GCC. + */ +#ifdef __GNUC__ +#define GCC_PRAGMA(v) _Pragma(v) +#else +#define GCC_PRAGMA(v) +#endif + +/* Workaround for Keil 4 */ +#ifndef CONTROL_nPRIV_Msk +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ +#endif + +/**@brief Function for finding the current interrupt level. + * + * @return Current interrupt level. + * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. + * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. + * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. + */ +uint8_t current_int_priority_get(void); + + +/**@brief Function for finding out the current privilege level. + * + * @return Current privilege level. + * @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level. + * @retval APP_LEVEL_PRIVILEGED We are running in privileged level. + */ +uint8_t privilege_level_get(void); + + +#ifdef __cplusplus +} +#endif + +#endif // APP_UTIL_PLATFORM_H__ + +/** @} */ diff --git a/HAL_Driver/sdk/components/libraries/util/nordic_common.h b/HAL_Driver/sdk/components/libraries/util/nordic_common.h new file mode 100644 index 0000000..76dd8e6 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/nordic_common.h @@ -0,0 +1,215 @@ +/** + * Copyright (c) 2008 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * @brief Common defines and macros for firmware developed by Nordic Semiconductor. + */ + +#ifndef NORDIC_COMMON_H__ +#define NORDIC_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if selected module is enabled + * + * This is save function for driver enable checking. + * Correct from Lint point of view (not using default of undefined value). + * + * Usage: + * @code + #if NRF_MODULE_ENABLED(UART) + ... + #endif + * @endcode + * + * @param module The module name. + * + * @retval 1 The macro _ENABLE is defined and is non-zero. + * @retval 0 The macro _ENABLE is not defined or it equals zero. + * + * @note + * This macro intentionally does not implement second expansion level. + * The name of the module to be checked has to be given directly as a parameter. + * And given parameter would be connected with @c _ENABLED postfix directly + * without evaluating its value. + */ +//lint -emacro(491,NRF_MODULE_ENABLED) // Suppers warning 491 "non-standard use of 'defined' preprocessor operator" +#ifdef NRF_MODULE_ENABLE_ALL +#warning "Do not use NRF_MODULE_ENABLE_ALL for real builds." +#define NRF_MODULE_ENABLED(module) 1 +#else +#define NRF_MODULE_ENABLED(module) \ + ((defined(module ## _ENABLED) && (module ## _ENABLED)) ? 1 : 0) +#endif +/** The upper 8 bits of a 32 bit value */ +//lint -emacro(572,MSB_32) // Suppress warning 572 "Excessive shift value" +#define MSB_32(a) (((a) & 0xFF000000) >> 24) +/** The lower 8 bits (of a 32 bit value) */ +#define LSB_32(a) ((a) & 0x000000FF) + +/** The upper 8 bits of a 16 bit value */ +//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value" +#define MSB_16(a) (((a) & 0xFF00) >> 8) +/** The lower 8 bits (of a 16 bit value) */ +#define LSB_16(a) ((a) & 0x00FF) + +/** Leaves the minimum of the two 32-bit arguments */ +/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */ +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +/** Leaves the maximum of the two 32-bit arguments */ +/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */ +#define MAX(a, b) ((a) < (b) ? (b) : (a)) + +/**@brief Concatenates two parameters. + * + * It realizes two level expansion to make it sure that all the parameters + * are actually expanded before gluing them together. + * + * @param p1 First parameter to concatenating + * @param p2 Second parameter to concatenating + * + * @return Two parameters glued together. + * They have to create correct C mnemonic in other case + * preprocessor error would be generated. + * + * @sa CONCAT_3 + */ +#define CONCAT_2(p1, p2) CONCAT_2_(p1, p2) +/** Auxiliary macro used by @ref CONCAT_2 */ +#define CONCAT_2_(p1, p2) p1##p2 + +/**@brief Concatenates three parameters. + * + * It realizes two level expansion to make it sure that all the parameters + * are actually expanded before gluing them together. + * + * @param p1 First parameter to concatenating + * @param p2 Second parameter to concatenating + * @param p3 Third parameter to concatenating + * + * @return Three parameters glued together. + * They have to create correct C mnemonic in other case + * preprocessor error would be generated. + * + * @sa CONCAT_2 + */ +#define CONCAT_3(p1, p2, p3) CONCAT_3_(p1, p2, p3) +/** Auxiliary macro used by @ref CONCAT_3 */ +#define CONCAT_3_(p1, p2, p3) p1##p2##p3 + +#define STRINGIFY_(val) #val +/** Converts a macro argument into a character constant. + */ +#define STRINGIFY(val) STRINGIFY_(val) + +/** Counts number of elements inside the array + */ +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +/**@brief Set a bit in the uint32 word. + * + * @param[in] W Word whose bit is being set. + * @param[in] B Bit number in the word to be set. + */ +#define SET_BIT(W, B) ((W) |= (uint32_t)(1U << (B))) + + +/**@brief Clears a bit in the uint32 word. + * + * @param[in] W Word whose bit is to be cleared. + * @param[in] B Bit number in the word to be cleared. + */ +#define CLR_BIT(W, B) ((W) &= (~(uint32_t)(1U << (B)))) + + +/**@brief Checks if a bit is set. + * + * @param[in] W Word whose bit is to be checked. + * @param[in] B Bit number in the word to be checked. + * + * @retval 1 if bit is set. + * @retval 0 if bit is not set. + */ +#define IS_SET(W, B) (((W) >> (B)) & 1) + +#define BIT_0 0x01 /**< The value of bit 0 */ +#define BIT_1 0x02 /**< The value of bit 1 */ +#define BIT_2 0x04 /**< The value of bit 2 */ +#define BIT_3 0x08 /**< The value of bit 3 */ +#define BIT_4 0x10 /**< The value of bit 4 */ +#define BIT_5 0x20 /**< The value of bit 5 */ +#define BIT_6 0x40 /**< The value of bit 6 */ +#define BIT_7 0x80 /**< The value of bit 7 */ +#define BIT_8 0x0100 /**< The value of bit 8 */ +#define BIT_9 0x0200 /**< The value of bit 9 */ +#define BIT_10 0x0400 /**< The value of bit 10 */ +#define BIT_11 0x0800 /**< The value of bit 11 */ +#define BIT_12 0x1000 /**< The value of bit 12 */ +#define BIT_13 0x2000 /**< The value of bit 13 */ +#define BIT_14 0x4000 /**< The value of bit 14 */ +#define BIT_15 0x8000 /**< The value of bit 15 */ +#define BIT_16 0x00010000 /**< The value of bit 16 */ +#define BIT_17 0x00020000 /**< The value of bit 17 */ +#define BIT_18 0x00040000 /**< The value of bit 18 */ +#define BIT_19 0x00080000 /**< The value of bit 19 */ +#define BIT_20 0x00100000 /**< The value of bit 20 */ +#define BIT_21 0x00200000 /**< The value of bit 21 */ +#define BIT_22 0x00400000 /**< The value of bit 22 */ +#define BIT_23 0x00800000 /**< The value of bit 23 */ +#define BIT_24 0x01000000 /**< The value of bit 24 */ +#define BIT_25 0x02000000 /**< The value of bit 25 */ +#define BIT_26 0x04000000 /**< The value of bit 26 */ +#define BIT_27 0x08000000 /**< The value of bit 27 */ +#define BIT_28 0x10000000 /**< The value of bit 28 */ +#define BIT_29 0x20000000 /**< The value of bit 29 */ +#define BIT_30 0x40000000 /**< The value of bit 30 */ +#define BIT_31 0x80000000 /**< The value of bit 31 */ + +#define UNUSED_VARIABLE(X) ((void)(X)) +#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X) +#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X) + +#ifdef __cplusplus +} +#endif + +#endif // NORDIC_COMMON_H__ diff --git a/HAL_Driver/sdk/components/libraries/util/nrf_assert.c b/HAL_Driver/sdk/components/libraries/util/nrf_assert.c new file mode 100644 index 0000000..fd98ebd --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/nrf_assert.c @@ -0,0 +1,54 @@ +/** + * Copyright (c) 2006 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "nrf_assert.h" +#include "app_error.h" +#include "nordic_common.h" + +__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name) +{ + assert_info_t assert_info = + { + .line_num = line_num, + .p_file_name = file_name, + }; + app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info)); + + UNUSED_VARIABLE(assert_info); +} diff --git a/HAL_Driver/sdk/components/libraries/util/nrf_assert.h b/HAL_Driver/sdk/components/libraries/util/nrf_assert.h new file mode 100644 index 0000000..97c5152 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/nrf_assert.h @@ -0,0 +1,122 @@ +/** + * Copyright (c) 2006 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * @brief Utilities for verifying program logic + */ + +#ifndef NRF_ASSERT_H_ +#define NRF_ASSERT_H_ + +#include +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Function for handling assertions. + * + * + * @note + * This function is called when an assertion has triggered. + * + * @note + * This function is deprecated and will be removed in future releases. + * Use app_error_fault_handler instead. + * + * + * @post + * All hardware is put into an idle non-emitting state (in particular the radio is highly + * important to switch off since the radio might be in a state that makes it send + * packets continiously while a typical final infinit ASSERT loop is executing). + * + * + * @param line_num The line number where the assertion is called + * @param file_name Pointer to the file name + */ +//lint -save -esym(14, assert_nrf_callback) +void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name); +//lint -restore + +#if (defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)) +#define NRF_ASSERT_PRESENT 1 +#else +#define NRF_ASSERT_PRESENT 0 +#endif + +//#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) + +/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */ +/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \ + +/** @brief Function for checking intended for production code. + * + * Check passes if "expr" evaluates to true. */ + +#ifdef _lint +#define ASSERT(expr) \ +if (expr) \ +{ \ +} \ +else \ +{ \ + while (1); \ +} +#else //_lint +#define ASSERT(expr) \ +if (NRF_ASSERT_PRESENT) \ +{ \ + if (expr) \ + { \ + } \ + else \ + { \ + assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \ + } \ +} + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_ASSERT_H_ */ diff --git a/HAL_Driver/sdk/components/libraries/util/nrf_bitmask.h b/HAL_Driver/sdk/components/libraries/util/nrf_bitmask.h new file mode 100644 index 0000000..f5b304b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/nrf_bitmask.h @@ -0,0 +1,147 @@ +/** + * Copyright (c) 2006 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_BITMASK_H +#define NRF_BITMASK_H + +#include "compiler_abstraction.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8) +#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007) + +/** + * Function for checking if bit in the multi-byte bit mask is set. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + * + * @return 0 if bit is not set, positive value otherwise. + */ +__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask) +{ + uint8_t const * p_mask8 = (uint8_t const *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + return (1 << bit) & p_mask8[byte_idx]; +} + +/** + * Function for setting a bit in the multi-byte bit mask. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + */ +__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask) +{ + uint8_t * p_mask8 = (uint8_t *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + p_mask8[byte_idx] |= (1 << bit); +} + +/** + * Function for clearing a bit in the multi-byte bit mask. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + */ +__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask) +{ + uint8_t * p_mask8 = (uint8_t *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + p_mask8[byte_idx] &= ~(1 << bit); +} + +/** + * Function for performing bitwise OR operation on two multi-byte bit masks. + * + * @param p_mask1 A pointer to the first bit mask. + * @param p_mask2 A pointer to the second bit mask. + * @param p_mask_out A pointer to the output bit mask. + * @param length Length of output mask in bytes. + */ +__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1, + void const * p_mask2, + void * p_out_mask, + uint32_t length) +{ + uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; + uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; + uint8_t * p_mask8_out = (uint8_t *)p_out_mask; + uint32_t i; + for (i = 0; i < length; i++) + { + p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i]; + } +} + +/** + * Function for performing bitwise AND operation on two multi-byte bit masks. + * + * @param p_mask1 A pointer to the first bit mask. + * @param p_mask2 A pointer to the second bit mask. + * @param p_mask_out A pointer to the output bit mask. + * @param length Length of output mask in bytes. + */ +__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1, + void const * p_mask2, + void * p_out_mask, + uint32_t length) +{ + uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; + uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; + uint8_t * p_mask8_out = (uint8_t *)p_out_mask; + uint32_t i; + for (i = 0; i < length; i++) + { + p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i]; + } +} + +#ifdef __cplusplus +} +#endif + +#endif //NRF_BITMASK_H diff --git a/HAL_Driver/sdk/components/libraries/util/sdk_common.h b/HAL_Driver/sdk/components/libraries/util/sdk_common.h new file mode 100644 index 0000000..62294b0 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/sdk_common.h @@ -0,0 +1,77 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @cond */ +/**@file + * + * @ingroup experimental_api + * @defgroup sdk_common SDK Common Header + * @brief All common headers needed for SDK examples will be included here so that application + * developer does not have to include headers on him/herself. + * @{ + */ + +#ifndef SDK_COMMON_H__ +#define SDK_COMMON_H__ + +#include +#include +#include +#include "sdk_config.h" +#include "nordic_common.h" +#include "compiler_abstraction.h" +#include "sdk_os.h" +#include "sdk_errors.h" +#include "app_util.h" +#include "sdk_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @} */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_COMMON_H__ + diff --git a/HAL_Driver/sdk/components/libraries/util/sdk_errors.h b/HAL_Driver/sdk/components/libraries/util/sdk_errors.h new file mode 100644 index 0000000..b7f992d --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/sdk_errors.h @@ -0,0 +1,167 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + * @defgroup sdk_error SDK Error codes + * @{ + * @ingroup app_common + * @{ + * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for + * identifying the module where the error occurred while the least least significant LSB + * are used to provide the cause or nature of error. Each module is assigned a 16-bit + * unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit + * LSB range is with module id as the MSB in the 32-bit error code is reserved for the + * module. As an example, if 0x8800 identifies a certain SDK module, all values from + * 0x88000000 - 0x8800FFFF are reserved for this module. + * It should be noted that common error reasons have been assigned values to make it + * possible to decode error reason easily. As an example, lets module uninitialized has + * been assigned an error code 0x000A0. Then, if application encounters an error code + * 0xZZZZ00A0, it knows that it accessing a certain module without initializing it. + * Apart from this, each module is allowed to define error codes that are not covered by + * the common ones, however, these values are defined in a range that does not conflict + * with common error values. For module, specific error however, it is possible that the + * same error value is used by two different modules to indicated errors of very different + * nature. If error is already defined by the NRF common error codes, these are reused. + * A range is reserved for application as well, it can use this range for defining + * application specific errors. + * + * @note Success code, NRF_SUCCESS, does not include any module identifier. + + */ + +#ifndef SDK_ERRORS_H__ +#define SDK_ERRORS_H__ + +#include +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sdk_err_base Base defined for SDK Modules + * @{ + */ +#define NRF_ERROR_SDK_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x8000) /**< Base value defined for SDK module identifiers. */ +#define NRF_ERROR_SDK_COMMON_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x0080) /**< Base error value to be used for SDK error values. */ +/** @} */ + +/** + * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred. + * @{ + */ +#define NRF_ERROR_MEMORY_MANAGER_ERR_BASE (0x8100) /**< Base address for Memory Manager related errors. */ +#define NRF_ERROR_PERIPH_DRIVERS_ERR_BASE (0x8200) /**< Base address for Peripheral drivers related errors. */ +#define NRF_ERROR_GAZELLE_ERR_BASE (0x8300) /**< Base address for Gazelle related errors. */ +#define NRF_ERROR_BLE_IPSP_ERR_BASE (0x8400) /**< Base address for BLE IPSP related errors. */ +#define NRF_ERROR_CRYPTO_ERR_BASE (0x8500) /**< Base address for crypto related errors. */ +/** @} */ + + +/** + * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors. + * @{ + */ +#define NRF_ERROR_IOT_ERR_BASE_START (0xA000) +#define NRF_ERROR_IOT_ERR_BASE_STOP (0xAFFF) +/** @} */ + + +/** + * @defgroup sdk_common_errors Codes reserved as identification for common errors. + * @{ + */ +#define NRF_ERROR_MODULE_NOT_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0000) ///< Module not initialized +#define NRF_ERROR_MUTEX_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0001) ///< Mutex initialization failed +#define NRF_ERROR_MUTEX_LOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0002) ///< Mutex lock failed +#define NRF_ERROR_MUTEX_UNLOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0003) ///< Mutex unlock failed +#define NRF_ERROR_MUTEX_COND_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0004) ///< Mutex conditional initialization failed +#define NRF_ERROR_MODULE_ALREADY_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0005) ///< Module already initialized +#define NRF_ERROR_STORAGE_FULL (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0006) ///< Storage full +#define NRF_ERROR_API_NOT_IMPLEMENTED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0010) ///< API not implemented +#define NRF_ERROR_FEATURE_NOT_ENABLED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0011) ///< Feature not enabled +#define NRF_ERROR_IO_PENDING (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0012) ///< Input/Output pending +/** @} */ + + +/** + * @defgroup drv_specific_errors Error / status codes specific to drivers. + * @{ + */ +#define NRF_ERROR_DRV_TWI_ERR_OVERRUN (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0000) +#define NRF_ERROR_DRV_TWI_ERR_ANACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0001) +#define NRF_ERROR_DRV_TWI_ERR_DNACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0002) +/** @} */ + + +/** + * @defgroup ble_ipsp_errors IPSP codes + * @brief Error and status codes specific to IPSP. + * @{ + */ +#define NRF_ERROR_BLE_IPSP_RX_PKT_TRUNCATED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0000) +#define NRF_ERROR_BLE_IPSP_CHANNEL_ALREADY_EXISTS (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0001) +#define NRF_ERROR_BLE_IPSP_LINK_DISCONNECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0002) +#define NRF_ERROR_BLE_IPSP_PEER_REJECTED (NRF_ERROR_BLE_IPSP_ERR_BASE + 0x0003) +/* @} */ + + +/** + * @brief API Result. + * + * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive + * error code indicating cause or reason for failure is provided. + * + * Though called an API result, it could used in Asynchronous notifications callback along + * with asynchronous callback as event result. This mechanism is employed when an event + * marks the end of procedure initiated using API. API result, in this case, will only be + * an indicative of whether the procedure has been requested successfully. + */ +typedef uint32_t ret_code_t; + +/** @} */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_ERRORS_H__ diff --git a/HAL_Driver/sdk/components/libraries/util/sdk_macros.h b/HAL_Driver/sdk/components/libraries/util/sdk_macros.h new file mode 100644 index 0000000..3c621b5 --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/sdk_macros.h @@ -0,0 +1,215 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/**@file + * + + * @defgroup sdk_common_macros SDK Common Header + * @ingroup app_common + * @brief Macros for parameter checking and similar tasks + * @{ + */ + +#ifndef SDK_MACROS_H__ +#define SDK_MACROS_H__ + +#include "nrf_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/**@brief Macro for parameter checking. + * + * If @p _cond evaluates to true, does nothing. Otherwise, + * if @p _module ## _PARAM_CHECK_DISABLED is @e not set (default), prints an error message + * if @p _printfn is provided, and returns from the calling function context with code @p _err. + * If @p _module ## _PARAM_CHECK_DISABLED is set, behaves like the ASSERT macro. + * + * Parameter checking implemented using this macro can be optionally turned off for release code. + * Only disable runtime parameter checks if size if a major concern. + * + * @param _module The module name. + * @param _cond The condition to be evaluated. + * @param _err The error to be returned. + * @param _printfn A printf-compatible function used to log the error. + * Leave empty if no logging is needed. + * + * @hideinitializer + */ +/*lint -esym(666, NRF_PARAM_CHECK*) : Expression with side effects passed to macro */ +#define NRF_PARAM_CHECK(_module, _cond, _err, _printfn) \ + do \ + { \ + if ((_cond)) \ + { \ + /* Do nothing. */ \ + } \ + else if (!(_module ## _PARAM_CHECK_DISABLED)) \ + { \ + _printfn("%s check failed in %s() with value 0x%x.", #_cond, __func__, _err); \ + return (_err); \ + } \ + else \ + { \ + ASSERT((_cond)); \ + } \ + } while (0); + + +/**@brief Macro for verifying statement to be true. It will cause the exterior function to return + * err_code if the statement is not true. + * + * @param[in] statement Statement to test. + * @param[in] err_code Error value to return if test was invalid. + * + * @retval nothing, but will cause the exterior function to return @p err_code if @p statement + * is false. + */ +#define VERIFY_TRUE(statement, err_code) \ +do \ +{ \ + if (!(statement)) \ + { \ + return err_code; \ + } \ +} while (0) + + +/**@brief Macro for verifying statement to be true. It will cause the exterior function to return + * if the statement is not true. + * + * @param[in] statement Statement to test. + */ +#define VERIFY_TRUE_VOID(statement) VERIFY_TRUE((statement), ) + + +/**@brief Macro for verifying statement to be false. It will cause the exterior function to return + * err_code if the statement is not false. + * + * @param[in] statement Statement to test. + * @param[in] err_code Error value to return if test was invalid. + * + * @retval nothing, but will cause the exterior function to return @p err_code if @p statement + * is true. + */ +#define VERIFY_FALSE(statement, err_code) \ +do \ +{ \ + if ((statement)) \ + { \ + return err_code; \ + } \ +} while (0) + + +/**@brief Macro for verifying statement to be false. It will cause the exterior function to return + * if the statement is not false. + * + * @param[in] statement Statement to test. + */ +#define VERIFY_FALSE_VOID(statement) VERIFY_FALSE((statement), ) + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior + * function to return error code of statement if it is not @ref NRF_SUCCESS. + * + * @param[in] statement Statement to check against NRF_SUCCESS. + */ +#define VERIFY_SUCCESS(statement) \ +do \ +{ \ + uint32_t _err_code = (uint32_t) (statement); \ + if (_err_code != NRF_SUCCESS) \ + { \ + return _err_code; \ + } \ +} while(0) + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior + * function to return if the err_code is not @ref NRF_SUCCESS. + * + * @param[in] err_code The error code to check. + */ +#define VERIFY_SUCCESS_VOID(err_code) VERIFY_TRUE_VOID((err_code) == NRF_SUCCESS) + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return @ref NRF_ERROR_INVALID_STATE if not. + * + * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED + * should be true if the module is initialized, false if not. + */ +#define VERIFY_MODULE_INITIALIZED() VERIFY_TRUE((MODULE_INITIALIZED), NRF_ERROR_INVALID_STATE) + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED + * should be true if the module is initialized, false if not. + */ +#define VERIFY_MODULE_INITIALIZED_VOID() VERIFY_TRUE_VOID((MODULE_INITIALIZED)) + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @param[in] param The variable to check if is NULL. + */ +#define VERIFY_PARAM_NOT_NULL(param) VERIFY_FALSE(((param) == NULL), NRF_ERROR_NULL) + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @param[in] param The variable to check if is NULL. + */ +#define VERIFY_PARAM_NOT_NULL_VOID(param) VERIFY_FALSE_VOID(((param) == NULL)) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_MACROS_H__ + diff --git a/HAL_Driver/sdk/components/libraries/util/sdk_os.h b/HAL_Driver/sdk/components/libraries/util/sdk_os.h new file mode 100644 index 0000000..aa3b04b --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/sdk_os.h @@ -0,0 +1,76 @@ +/** + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @cond */ +/**@file + * + * @defgroup sdk_os SDK OS Abstraction + * @ingroup experimental_api + * @details In order to made SDK modules independent of use of an embedded OS, and permit + * application with varied task architecture, SDK abstracts the OS specific + * elements here in order to make all other modules agnostic to the OS or task + * architecture. + * @{ + */ + +#ifndef SDK_OS_H__ +#define SDK_OS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDK_MUTEX_DEFINE(X) +#define SDK_MUTEX_INIT(X) +#define SDK_MUTEX_LOCK(X) +#define SDK_MUTEX_UNLOCK(X) + +/** + * @defgroup os_data_type Data types. + */ + +/** @} */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_OS_H__ + diff --git a/HAL_Driver/sdk/components/libraries/util/sdk_resources.h b/HAL_Driver/sdk/components/libraries/util/sdk_resources.h new file mode 100644 index 0000000..462ddbf --- /dev/null +++ b/HAL_Driver/sdk/components/libraries/util/sdk_resources.h @@ -0,0 +1,86 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** @file + * @brief Definition file for resource usage by SoftDevice, ESB and Gazell. + */ + +#ifndef SDK_RESOURCES_H__ +#define SDK_RESOURCES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SOFTDEVICE_PRESENT) || defined (BLE_STACK_SUPPORT_REQD) || defined (ANT_STACK_SUPPORT_REQD) + #include "nrf_sd_def.h" +#else + #define SD_PPI_RESTRICTED 0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */ + #define SD_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */ + #define SD_PPI_GROUPS_USED 0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */ + #define SD_TIMERS_USED 0uL /**< Timers used by SoftDevice. */ + #define SD_SWI_USED 0uL /**< Software interrupts used by SoftDevice. */ +#endif + +#ifdef GAZELL_PRESENT + #include "nrf_gzll_resources.h" +#else + #define GZLL_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by Gazell (not available to th spplication). */ + #define GZLL_TIMERS_USED 0uL /**< Timers used by Gazell. */ + #define GZLL_SWI_USED 0uL /**< Software interrupts used by Gazell */ +#endif + +#ifdef ESB_PRESENT + #include "nrf_esb_resources.h" +#else + #define ESB_PPI_CHANNELS_USED 0uL /**< PPI channels utilized by ESB (not available to th spplication). */ + #define ESB_TIMERS_USED 0uL /**< Timers used by ESB. */ + #define ESB_SWI_USED 0uL /**< Software interrupts used by ESB */ +#endif + +#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED) +#define NRF_PPI_GROUPS_USED (SD_PPI_GROUPS_USED) +#define NRF_SWI_USED (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED) +#define NRF_TIMERS_USED (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED) + +#ifdef __cplusplus +} +#endif + +#endif // SDK_RESOURCES_H__ diff --git a/HAL_Driver/sdk/documentation/NordicS.jpg b/HAL_Driver/sdk/documentation/NordicS.jpg new file mode 100644 index 0000000..2edfeee Binary files /dev/null and b/HAL_Driver/sdk/documentation/NordicS.jpg differ diff --git a/HAL_Driver/sdk/documentation/index.html b/HAL_Driver/sdk/documentation/index.html new file mode 100644 index 0000000..ab908ea --- /dev/null +++ b/HAL_Driver/sdk/documentation/index.html @@ -0,0 +1,184 @@ + + + +nRF5 SDK Documentation + + + + +
+ + +
+ nRF5 Software Development Kit v15.3.0
+

The nRF5 Software Development Kit (SDK) enables Bluetooth® low energy, ANT, and 2.4 GHz proprietary product development with Nordic Semiconductor's advanced nRF5 Series System on Chip (SoC) devices.

+ + +

+ SDK documentation +
+ The SDK documentation is available in Nordic Semiconductor's Documentation Library. +
+ VIEW DOCUMENTATION » +

+ +

+ S112 SoftDevice API documentation +
+ Bluetooth® low energy Peripheral protocol stack for the nRF52810 SoC. +
+ VIEW API DOCUMENTATION » +

+ +

+ S132 SoftDevice API documentation +
+ Bluetooth® low energy Peripheral and Central protocol stack for the nRF52832 SoC. +
+ VIEW API DOCUMENTATION » +

+ +

+ S140 SoftDevice API documentation +
+ Bluetooth® low energy Peripheral and Central protocol stack for the nRF52840 SoC. +
+ VIEW API DOCUMENTATION » +

+ + +

+ S212 SoftDevice API documentation +
+ ANT protocol stack for the nRF52 Series. +
+ VIEW API DOCUMENTATION » +

+ + +

+ S312 SoftDevice API documentation +
+ ANT and BLE protocol stack for the nRF52810 SoC. +
+ VIEW API DOCUMENTATION » +

+ + + +

+ S332 SoftDevice API documentation +
+ ANT and BLE protocol stack for the nRF52832 SoC. +
+ VIEW API DOCUMENTATION » +

+ + + +

+ S340 SoftDevice API documentation +
+ ANT and BLE protocol stack for the nRF52840 SoC. +
+ VIEW API DOCUMENTATION » +

+ + + +

+ Offline documentation +
+ You can download documentation for offline use from http://developer.nordicsemi.com. +
+ DOWNLOAD OFFLINE DOCUMENTATION » +

+ +
+ + To view Nordic Semiconductor's license agreement, please click here.
+ To see release notes for this product, please click here.
+ +
+ +
+ + + \ No newline at end of file diff --git a/HAL_Driver/sdk/documentation/licenses.html b/HAL_Driver/sdk/documentation/licenses.html new file mode 100644 index 0000000..66d224d --- /dev/null +++ b/HAL_Driver/sdk/documentation/licenses.html @@ -0,0 +1,87 @@ + + + +Licenses in the nRF5 SDK + + + + +
+ + +
+ Licenses in the nRF5 SDK
+ +

+See the top of each source file for the license under which the file is +released.

+

+The following licenses are used in the nRF5 SDK: +

    +
  1. nRF5 SDK license: The majority of the source code included in the nRF5 SDK (nRF5_Nordic_license.txt)
    2. +
  2. nRF5 Garmin Canada license: Files released by Garmin Canada included in the nRF5 SDK (nRF5_Garmin_Canada_license.txt)
    3. +
  3. SoftDevice license: The SoftDevice and its headers (..\components\softdevice\sxxx\doc\license_file)
    4. +
  4. ARM 3-clause BSD license: CMSIS and system files (..\components\toolchain)
    5. +
  5. FreeRTOS license: FreeRTOS configuration files (FreeRTOSConfig.h in the examples that show how to use FreeRTOS)
    6. +
  6. Third-party licenses: All third-party code contained in ..\external (respective licenses included in each of the imported projects)
    7. +
+

+ + +
+
+ + diff --git a/HAL_Driver/sdk/documentation/licenses.txt b/HAL_Driver/sdk/documentation/licenses.txt new file mode 100644 index 0000000..5bfda63 --- /dev/null +++ b/HAL_Driver/sdk/documentation/licenses.txt @@ -0,0 +1,23 @@ +See the top of each source file for the license under which the file is +released. +The following licenses are used in the nRF5 SDK: + + i) nRF5 SDK license: The majority of the source code included in the + nRF5 SDK (nRF5_Nordic_license.txt) + + ii) nRF5 Garmin Canada license: Files released by Garmin Canada + included in the nRF5 SDK (nRF5_Garmin_Canada_license.txt) + + iii) SoftDevice license: The SoftDevice and its headers + (..\components\softdevice\sxxx\doc\) + + iv) ARM 3-clause BSD license: CMSIS and system files (..\components\toolchain) + + v) FreeRTOS license: FreeRTOS configuration files (FreeRTOSConfig.h + in the examples that show how to use FreeRTOS) + + vi) Third-party licenses: All third-party code contained in + ..\external (respective licenses included in each of the imported + projects) + + diff --git a/HAL_Driver/sdk/documentation/nRF5_Garmin_Canada_license.txt b/HAL_Driver/sdk/documentation/nRF5_Garmin_Canada_license.txt new file mode 100644 index 0000000..58c176a --- /dev/null +++ b/HAL_Driver/sdk/documentation/nRF5_Garmin_Canada_license.txt @@ -0,0 +1,50 @@ +This software is subject to the ANT+ Shared Source License +www.thisisant.com/swlicenses +Copyright (c) Garmin Canada Inc. 2010 +All rights reserved. + +Redistribution and use in source and binary forms, with or +without modification, are permitted provided that the following +conditions are met: + + 1) Redistributions of source code must retain the above + copyright notice, this list of conditions and the following + disclaimer. + + 2) Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + + 3) Neither the name of Garmin nor the names of its + contributors may be used to endorse or promote products + derived from this software without specific prior + written permission. + +The following actions are prohibited: + + 1) Redistribution of source code containing the ANT+ Network + Key. The ANT+ Network Key is available to ANT+ Adopters. + Please refer to http://thisisant.com to become an ANT+ + Adopter and access the key. + + 2) Reverse engineering, decompilation, and/or disassembly of + software provided in binary form under this license. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE HEREBY +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; DAMAGE TO ANY DEVICE, LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +OF THE POSSIBILITY OF SUCH DAMAGE. SOME STATES DO NOT ALLOW +THE EXCLUSION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO THE +ABOVE LIMITATIONS MAY NOT APPLY TO YOU. + diff --git a/HAL_Driver/sdk/documentation/nRF5_Nordic_license.txt b/HAL_Driver/sdk/documentation/nRF5_Nordic_license.txt new file mode 100644 index 0000000..06c2d4e --- /dev/null +++ b/HAL_Driver/sdk/documentation/nRF5_Nordic_license.txt @@ -0,0 +1,37 @@ +Copyright (c) 2010 - 2019, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + diff --git a/HAL_Driver/sdk/documentation/nRF5x_series_logo.png b/HAL_Driver/sdk/documentation/nRF5x_series_logo.png new file mode 100644 index 0000000..4002538 Binary files /dev/null and b/HAL_Driver/sdk/documentation/nRF5x_series_logo.png differ diff --git a/HAL_Driver/sdk/documentation/release_notes.txt b/HAL_Driver/sdk/documentation/release_notes.txt new file mode 100644 index 0000000..2a1b7cf --- /dev/null +++ b/HAL_Driver/sdk/documentation/release_notes.txt @@ -0,0 +1,6445 @@ +nRF5 SDK v15.3.0 +------------------------ +Release Date: Week 7, 2019 + +Highlights: + +- Added support for a new chip - nRF52811. +- Added support for two new ANT SoftDevices: S312 targeting nRF52810 and nRF52832, and S340 targeting nRF52840. +- Added back support for the ANT SoftDevice S332 v6.1.1, as well as updated the latest SoftDevices S112, S132, S140 and S212 v6.1.1. +- Updated the SDFU solution with ANT transport layer. +- Updated DTM to support nRF52811, and updated the existing code to correctly handle Anomaly 172. + + + +The following toolchains/devices have been used for testing and verification: + + - ARM: MDK-ARM version 5.25 + - GCC: GCC ARM Embedded 7.2018q2.update + - IAR: IAR Workbench 7.80.4 + - SES: SES 4.12 + +Note: The selected GCC version has shown instabilities when using the Link Time Optimization feature, and using the feature is not recommended. + +***** +Note for IAR 8 users: +(Libraries for IAR 8 require wchar_t to be of size 32 bits while IAR 7 requires 16 bits). + +To run a project using IAR 8, follow these intructions: + - Open the IAR project in IAR 8. The IAR workbench will automatically generate an IAR 8 compatible project file. + - If the project contains one of the precompiled libraries listed below, replace it with the IAR 8 compatible alternative + (there are no projects targeting nRF51 in this SDK). + - Save the project. + - When building the project, you might get the warning: "The header file 'cmsis_iar.h' is obsolete and should not be used. [...]". + - The problem is described in DevZone post: https://devzone.nordicsemi.com/f/nordic-q-a/31123/iar-ewarm-8-22-1-complains-about-cmsis_iar-h + The solution is to remove all occurrences of #include . + +The affected libraries are: + - micro-ecc crypto: + - IAR7: Includes library located in the folder named “…_iar\…”. + - IAR8: Switch to using the library from the folder named “…_armgcc\…”. + - nrf_cc310, nrf_cc310_bl, and nrf_oberon: + - IAR7: Link to a library where “short_wchar” is part of the folder name. + - IAR8: Link to a library without “short_wchar” in part of the folder name. + - Gazell, NFC Tag, and 802.15.4: + - IAR7: Includes the library where the file name ends with “_iar”. + - IAR8: Switch to using the library with similar file name that ends with “_gcc”. +***** + +Supported SoftDevices: + - S112 v6.1.x + - S132 v6.1.x + - S140 v6.1.x + - S212 v6.1.x + - S312 v6.1.x + - S332 v6.1.x + - S340 v6.1.x + +Supported boards: + - PCA10040 + - PCA10040E (nRF52810 emulation on PCA10040) + - PCA10056 + - PCA10056E (nRF52811 emulation on PCA10056) + - PCA10059 (support in selected examples) + - D52DK1 from Garmin Canada (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** New features +***************** + +** ANT ** + +- Added the new ANT Secure DFU Bootloader example. + The example demonstrates how to use the new ANT transport with Secure DFU components + (with support only for SES and GCC toolchains). +- Removed legacy ANT bootloader solution. + + +** Drivers and libraries ** + +- nrf_cli can now prompt and autocomplete both sorted and unsorted subcommands. +- nrf_libuarte and nrf_libuarte_async now support multiple instances. + + +** BLE** + +- nrf_ble_lesc (part of the Peer Manager) now supports the LESC OOB pairing mode. + The ble_nfc_pairing_reference_c example demonstrates how to pass the OOB data to the module. + + +** DFU ** + +- Added the option to perform signature validation of the application on each boot. + This functionality requires nrfutil version 5.0.0 or higher. +- The DFU procedure can now mandate strictly increasing application versions. +- Added the option to send applications that will not be activated, but will remain in slot 1 ("external applications"). + This functionality requires nrfutil version 5.0.0 or higher. +- Added masking of GPREGRET and GPREGRET2 registers, enabling the upper 3 bytes of each register to be used by the application independently of the bootloader. + +** Crypto ** + +- Added nrf_crypto backend support for Infineon OPTIGA™ Trust X devices (selected features). +- Added new example to showcase Infineon OPTIGA Trust X functionality: examples/crypto/ifx_optiga_custom_example. + + +*** Changes +************ + +** DFU ** + +- Turned off Link Time Optimization in all DFU projects due to instabilities in the supported GCC compiler. + +** Drivers and libraries ** + +- nrf_cli: CLI will now automatically add the `\r` character before each printed `\n` character. + This feature can be switched off in sdk_config using flag `NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF`. +- USB: A complete list of changes is available under this link: https://github.com/NordicSemiconductor/nrfx/blob/a0dcb1350f6798f12479921a0a376d00e2316fd4/CHANGELOG.md + +** NFC ** + +- The NFC libraries (nfc_t2t_lib and nfc_t4t_lib) now use the NFCT driver instead of the NFC HAL modules (hal_nfc_t2t and hal_nfc_t4t). + The NFCT driver is a part of nrfx repository. +- Replaced hal_nfc_t2t and hal_nfc_t4t components with the nrfx_nfct driver. +- Added the NFC platform module (nfc_platform) to abstract runtime environment specific implementation from the driver. + HFCLK activation, required for NFC to operate correctly, is managed in this module. +- Removed the nfc_fixes.h file with NFC workaround description. The content of this file was moved to nrfx_nfct.h. + +** Crypto ** + +- nrf_oberon, nrf_cc310, and nrf_cc310_bl libraries have changed naming and placement compared to the previous release. + They are now available in the following folder scheme: + - GCC and IAR 8.x: lib//hard-float/.a + - IAR 7.80.x: lib//hard-float/short-wchar/.a + - Keil: lib//hard-float/short-wchar/.lib + Due to this naming convention change, updated nrf_cc310 and nrf_cc310_bl library version to 0.9.12. + Due to this naming convention change, updated nrf_oberon library version to 2.0.7. +- Changed ECC Public Key Validation from "Full" to "Partial" in nrf_crypto backend for ARM CC310. + This improves LESC pairing and ECDSA verify timing. + + +*** Bug fixes +**************** + +** Drivers and libraries ** + +- nrf_cli: The module can now be used with terminals with no standard background color (for example, white). +- USB: Fixed a bug where USB IRQ was not cleared after unplugging the USB cable. +- Fixed an issue where NRF_LOG_INIT(timestamp, frequency) failed to compile if the logger was disabled. +- Fixed a compilation failure issue when using NRF_LOG_HEXDUMP_WARNING. +- Fixed a scenario where the emulated project delay function (nrfx_coredep_delay_us) did not work correctly. + +** BLE ** + +- Peer Manager: + - Slave Security Requests received during a pairing or encryption procedure will now be ignored (to align with the BLE specification). + - Fixed a bug where Peer Manager would misinterpret a peer central's ability to resolve resolvable addresses in directed advertisements. + - Fixed a bug where Peer Manager would sometimes give a fatal error if the link disconnected during a pairing procedure. + - Fixed a bug where flash could be full but no Peer Manager event was sent. + - Fixed a bug where Peer Manager would silently drop Service Changed indications if an ATT MTU exchange was happening at the same time. +- Eddystone: + - Fixed a bug where EID was not correctly updated. + - Fixed bug where factory reset would not work correctly when followed by an immediate disconnect. + +** DFU ** + +- Various security improvements and fixes. +- Fixed various bugs in background DFU. +- Fixed bugs that appeared when combining transports (for example, UART + BLE). + +** DTM ** + +- Fixed a bug which made the workaround for nRF52840 Anomaly 172 non-functional. + +** Serialization ** + +- Fixed an issue with HCI transport sending redundant bytes on certain packet payloads containing escape codes. +- Fixes in serialization codecs. + + +*** Known Issues +**************** + +** General ** + +- Programming and debugging the nRF52811 chip may require an update of the J-Link firmware in order to recognize the new chip. +- The workaround for Anomaly 198 for nRF52840 SPIM3 peripheral that has been implemented in nrfx_spim cannot be used with a SoftDevice. + Flag NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED must be set to zero. + The workaround based on a dedicated RAM block for SPIM3 must be used instead. + +** BLE ** + +- GATTC: the ble_gattc_service_t::uuid field is incorrectly populated in the BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP event + if the sd_ble_gattc_primary_services_discover() or sd_ble_gattc_read() are called when a Primary Service Discovery by Service UUID is already ongoing. + When the application has called sd_ble_gattc_primary_services_discover(), it should wait for the BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP event before calling sd_ble_gattc_primary_services_discover() or sd_ble_gattc_read(). +- The TFTP Background DFU example has known instabilities. + +** Drivers and libraries ** + +- The SAADC driver does not handle detection limits 'high' and 'low' correctly if SAADC resolution is greater than 10 bits. +- USBD: + - The library may handle Remote Wakeup incorrectly. + - Issuing a SET_ADDRESS(0) request does not cause the device to change its state to default. + - The device does not STALL when a DATA transaction is received outside of SETUP. It ACKs instead. + +** IoT ** + +- For Linux kernels >= 4.12, The BLE_6LOWPAN_LEGACY_MODE configuration parameter must be set to 0 (the default is 1). + The default value must be kept for Linux kernels < 4.12. + With this configuration set up incorrectly, the examples do not work and are difficult to debug. + + + +====================================================================== + +nRF5 SDK v15.2.0 +------------------------ +Release Date: Week 37, 2018 + +This SDK release is an update replacing the non-published nRF5 SDK release v15.1.0. +The main updates compared to v15.1.0 are summarized in the last three points of the Highlights section. + +Highlights: + - Added support for the new SoftDevices S140, S132, and S112 v6.1.0. + - Added new targets for running S112 on nRF52832 (PCA10040). + - Updated ESB library to support all nRF52 devices (nRF52810, nRF52832 (Rev.1 & Rev.2), and nRF52840). + - Updated SDFU to include nRF52810 target (PCA10040E). + - Released nrf_log in production quality. + - Removed the workaround in nrf_sdh.c overriding the default priority level on SWI interrupt SD_EVT_IRQn and RADIO_NOTIFICATION_IRQn used by the SoftDevice. + - Changed the default interrupt priority level for the peripherals from 7 to 6. This is done to be aligned with the priority of the SWI coming from the SoftDevice. + - Fixed an interoperability issue with some Windows 10 versions when bonded and using directed advertising. + +Note: Due to compatibility issues, you must run the upgrade using nRF Connect Desktop v2.5.0 or later when testing the Bluetooth examples in nRF5 SDK v15.2.0. + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.18a + - GCC: GCC ARM Embedded 6.3 2017-q2-update + - IAR: IAR Workbench 7.80.4 (IAR 8 - see note below) + - SES: SES 3.40 + +***** +Note for IAR 8 users: +(Libraries for IAR 8 require wchar_t to be of size 32 bits while IAR 7 requires 16 bits). + +To run a project using IAR 8, follow these intructions: + - Open the IAR project in IAR 8. The IAR workbench will automatically generate an IAR 8 compatible project file. + - If the project contains one of the precompiled libraries listed below, replace it with the IAR 8 compatible alternative + (there are no projects targeting nRF51 in this SDK). + - Save the project. + - When building the project, you might get the warning: "The header file 'cmsis_iar.h' is obsolete and should not be used. [...]". + - The problem is described in DevZone post: https://devzone.nordicsemi.com/f/nordic-q-a/31123/iar-ewarm-8-22-1-complains-about-cmsis_iar-h + The solution is to remove all occurrences of #include . + +The affected libraries are: + - micro-ecc crypto: + - IAR7: Includes library located in the folder named “…_iar\…”. + - IAR8: Switch to using the library from the folder named “…_armgcc\…”. + - nrf_cc310, nrf_cc310_bl, and nrf_oberon: + - IAR7: Includes the library where “_short_wchar_” is part of the file name. + - IAR8: Switch to using the library with similar naming, but where the “short_wchar” is removed. + - Gazell, NFC Tag, and 802.15.4: + - IAR7: Includes the library where the file name ends with “_iar”. + - IAR8: Switch to using the library with similar file name that ends with “_gcc”. +***** + +Supported SoftDevices: + - S112 v6.1.x + - S132 v6.1.x + - S140 v6.1.x + - S212 v5.0.x + +Supported boards: + - PCA10040 + - PCA10040E (nRF52810 emulation on PCA10040) + - PCA10056 + - PCA10059 (support in selected examples) + - D52DK1 from Garmin Canada (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** New features +***************** + +** BLE ** + - Added new targets to demonstrate the use of S112 on nRF52832 (PCA10040). + - Added "Property Read" for the Object Transfer Service client (ble_app_ots_c). + - Added a Scanning Module to simplify scanning for BLE devices in central role. + - Peer Manager: + - peer_manager_handler.h: There are now standard event handlers available to users of the Peer Manager. + The event handlers provide features like logging, automatically securing the link, and automatically + deleting the oldest bond if the flash is full. + - PM_RA_PROTECTION_ENABLED: The Peer Manager can now be configured to reject repeated security requests + from peers that failed pairing. + - PM_LESC_ENABLED: Improved LESC support. + - PM_LOG_ENABLED: Added error and warning level logging messages to the Peer Manager. + - PM_EVT_FLASH_GARBAGE_COLLECTION_FAILED: Added new event. + - PM_PEER_DATA_ID_CENTRAL_ADDR_RES: Added automatic storing of the peer's Central Address Resolution value during bonding. + - pm_peer_id_list(): Added a new function for creating lists of Peer IDs, including some filtering. + - Added LESC support to the following examples: ble_app_hrs, ble_app_hrs_c, and ble_app_gls. + - Added support for nRF52840 (PCA10056) in the beacon example (ble_app_beacon). + - Added Swift Pair support to the HID mouse example (ble_app_hids_mouse). + - Battery Service: Added the possibility to notify a reconnected, bonded peer of an updated battery level. + This feature is demonstrated in the Immediate Alert Server example. + +** Crypto ** + - EdDSA: Added support for Edwards-curve Digital Signature Algorithm (Ed25519). + - In documentation, added a table showing supported nrf_crypto backends for different examples: + http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.sdk5.v15.2.0/nrf_crypto_default_backends.html + +** DFU/Bootloader ** + - Added a new target to the SDFU example to demonstrate SDFU running on nRF52810 (PCA10040E). In a single bank update, there is only + about 60 kB of flash available. This restricts what can be updated. + - The bootloader settings page is now backed up before being updated. This increases protection from corruption caused by chance events + (for example, power failure) and malicious apps. + - The advertising interval of BLE DFU can now be configured in sdk_config (NRF_DFU_BLE_ADV_INTERVAL). + - The size of the application data area that is left alone by the bootloader can now be configured + in sdk_config (NRF_DFU_APP_DATA_AREA_SIZE). + - The bootloader code now supports most of nrf_crypto backends. However, the size of the binary will likely be too large if other backends + are used, so you will need to accomodate by increasing the size of the bootloader. + +** USB ** + - Added response/no response to an IN token on ISO IN endpoint with a ZLP when no data is ready. This can be set with USBD_CONFIG_ISO_IN_ZLP. + - Added support for configuration string ID. + - Added an option to give priority to isochronous transfers using USBD_CONFIG_DMASCHEDULER_ISO_BOOST. + - Implemented SOF event callback in interrupt for classes. + - Added an enum and get function for a selected protocol (boot or report) in HID. Implemented a SET_PROTOCOL propagation mechanism using + on_set_protocol methods. Buffers can now be cleared after the SET_PROTOCOL command using clear_buffer methods. + - Redesigned the idle report mechanism in HID. It now allows a callback function and handles multiple report IDs. + - Added an option to send a ZLP on write with the same size as the endpoint in CDC ACM class using APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE. + - Implemented macros to set interval for individual endpoints. See APP_USBD_EP_WITH_INTERVAL. + - Transfers in Audio class can now be started in SOF interrupt set in the app_usbd_audio_sof_interrupt_register function. + + +*** Changes +************ + +** BLE ** + - Increased the length of the advertising name for the Running Speed and Cadence sensor example (ble_app_rscs) to make it easy to verify + that it is using the extended advertising. + - Included the Scanning module into all BLE examples. This aligns how scanning is performed in these examples. + - Updated the NFC pairing examples (ble_app_hids_keyboard_pairing_nfc, ble_app_hrs_nfc_pairing, ble_nfc_pairing_reference) to start using + the LESC functionality in the Peer Manager (which uses the nrf_ble_lesc module). + - Removed the manual handling of credits for the Object Transfer Service (ble_app_ots and ble_app_ots_c). Most use cases now work faster + and simpler when the SoftDevice is controlling it. + - Updated the API documentation for advertising_init in the Advertising module (ble_advertising). It was clarified that UUID arrays were not + copied into the Advertising module. + - Advertising module (ble_advertising) is no longer dependent on the fstorage module. + - Changed the ANCS example (ble_app_ancs_c) so that it no longer performs service discovery after connecting to an already bonded peer. + - Lowered the advertising interval in the Eddystone example (ble_app_eddystone), because some advertising packets would be lost when combined + with the timeslot API. + - Reduced the maximum supported value for advertising interval in Eddystone from 20000 to 16384. If a higher value is set, the SoftDevice returns + an error code that asserts the application. + - Peer Manager: + - Various improvements to documentation. + - The Peer Manager will now take less space for the same features. + - To decrease complexity, the Peer Manager no longer uses the 'reserve' functionality in FDS, meaning that PM_EVT_STORAGE_FULL + events will come slightly later if bonds cannot be stored during bonding. + - Error event parameters now specify whether the error code is to be interpreted as an FDS_ error or an NRF_ error. + - Peers without a stored rank are now never returned from pm_peer_ranks_get(). + - The function pm_peer_data_load() now fills the array even when returning NRF_ERROR_DATA_SIZE. + - Enabled internal LESC key handling through PM_LESC_ENABLED. Function pm_lesc_public_key_set() is now deprecated because of this change. + - All examples using the Peer Manager now use the new standard event handlers. + While some examples implement custom behavior, all examples do the following: + - Log Peer Manager events (at different log levels). + - Encrypt immediately on connection with bonded peers. + - Delete old bonds to make room for new peer data. + - Some examples supporting central mode disconnect when link encryption fails. Look for functions calling pm_handler_disconnect_on_sec_failure(). + - The ble_app_bms example will now request for security procedure to be initiated if the Central does not initiate it. + - Updated examples with directed advertisement to take into account Central Address Resolution value. + +** IEEE 802.15.4 ** + - Updated the radio test example to support 802.15.4 radio modes. + +** Crypto ** + - Updated documentation about RAM requirements on mbed TLS. + - Added endianness change Curve25519 (to little endian). + - Removed the following defines. A compile error is shown if they are enabled in a configuration: + - NRF_CRYPTO_BACKEND_CC310_BL_HASH_LITTLE_ENDIAN_DIGEST_ENABLED + - NRF_CRYPTO_BACKEND_CC310_BL_ECC_LITTLE_ENDIAN_ENABLED + - NRF_CRYPTO_BACKEND_MICRO_ECC_LITTLE_ENDIAN_ENABLED + - NRF_CRYPTO_BACKEND_NRF_SW_HASH_LITTLE_ENDIAN_DIGEST_ENABLED + - nrf_crypto micro-ecc backend: Moved ECDH public key validation from the key convert function to ECDH compute + (moved from nrf_crypto_backend_micro_ecc_public_key_from_raw to nrf_crypto_backend_micro_ecc_ecdh_compute). + - Upgraded nrf_cc310 and nrf_cc310_bl to version 0.9.10 including minor changes to some default configurations. + - Removed micro-ecc library/mbed TLS from BLE LESC examples for better user experience. + - micro-ecc library prevented a working compilation in a fresh LESC example (requires external download). + - mbed TLS significantly increases compilation time in the project, even if it is not configured as the enabled nrf_crypto backend. + +** DFU and Bootloader ** + - Updated documentation about how to change the existing SDFU project, so that the application can be uploaded without signature verification, + but at the same time to keep the signature verification when updating a SoftDevice and/or bootloader. + - The bootloader now does not use app_timer, which saves flash space. + - The bootloader now does the endian-conversion in code, instead of relying on endian-conversion in nrf_crypto. + +** Drivers and libraries ** + - Changed the peripherals' default interrupt priority level from 7 to 6. + - Included new version of nrfx (v1.1.0). For the nrfx changelog, see https://github.com/NordicSemiconductor/nrfx/blob/master/CHANGELOG.md + - nrf_log: + - Updated to production quality. + - You can now store/load the filtering configuration in FDS. + - You can now control one backend from another. + - nrf_cli: Added support for terminal meta keys. + +** Proprietary ** + - Updated ESB library to support all current variants of nRF52. This mainly involves adding proper handling of Errata related to the radio. + - Added a function to skip the next packet in the TX queue. This was previously a function used internally in the module under another name. + +** USB ** + - Moved USBD strings configuration to sdk_config. + - Rebuilt MSC class write procedure. + - Moved APP_USBD_CONFIG_LOG_ENABLED to nrf_log settings. + - HID report protocol is now default after reset. + - HID default idle rate after reset can now be defined. + - OUT transfers are now dropped when clearing stall on endpoint. + - SET_ADDRESS command is now defined as a separate event in app_usbd. It does not change the state of the device anymore. + - EP0 is now disabled until USB RESET condition is detected. + - HID OUT reports are now limited to 63 bytes of data + 1 byte reserved for report ID. + + +*** Bug fixes +**************** + +** BLE ** + - Fixed a bug in the BLE UART client (ble_app_uart_c) where it would check the wrong error code when issuing multiple write commands. + - Fixed a bug in the ANCS example (ble_app_ancs) where app_timer was included too many times. + - Fixed a bug in the Advertising module (ble_advertising) where a comment referred to seconds instead of 10 ms. + - Fixed a bug in the LESC connection example (ble_app_multirole_lesc) where the procedure for connection parameter update would not be started + immediately upon connection. + - Fixed a bug where a precompiled hex was missing for Immediate Alert Server (ble_app_ias) and Service Changed server (ble_app_gatts) examples. + - Fixed a bug in the Radio Notification Event Handler (ble_radio_notification) where a missing include stopped it from compiling. + - Fixed a bug in the BLE Interactive Command Line Interface Example in service discovery procedure. + - Fixed a bug in the Alert Notification Service, where it was not possible to enable notifications for an unread alert. + - Peer Manager: + - Fixed a bug where the event PM_EVT_FLASH_GARBAGE_COLLECTED was also sent when garbage collection failed. + - Fixed a bug in pm_next_peer_id_get() where it could report a peer with no data attached to it if used during bonding. + - Fixed a bug where peer data would not be written because the internal retry mechanism failed after two attempts. + - Fixed a bug where pairing (no bonding) could happen with an already bonded peer without triggering a PM_EVT_CONN_SEC_CONFIG_REQ event. + - Fixed several documentation bugs related to error codes. + - Eddystone: + - Fixed a bug where the default TX power was set to 0 instead of using the DEFAULT_FRAME_TX_POWER define. + - Fixed a bug where an invalid reference of a variable could cause incorrect data to be sent. + +** IEEE 802.15.4 ** + - Adjusted CCA threshold value to be correct for nRF52840 Rev. 1 (different from what was available on the Engineering sample). + - Implemented a fix for Anomaly 153 (temperature correction of RSSI measurement): added an API in RAL module for calculating the corrected RSSI value. + +** Drivers and libraries ** + - Fixed a bug in the SPI manager where app_timer was included too many times. + - Fixed a wrapping issue in the Ring Buffer library. + +** DFU/Bootloader ** + - Fixed a bug where the watchdog feeding in the bootloader did not happen during a certain FW activation. + +** DTM ** + - Added support for 8 dB on nRF52840 targets. + - Implemented the workaround for nRF52840 Anomaly 172 which caused the device to fail a test with interference in co-channels (RF-PHY/RCV/BV-29-C). + +** Proprietary ** + - Fixed a bug in bytewise_bit_swap where it was harder to backport the implementation to nRF51. + - Fixed a bug in nrf_esb_pop_tx where the packet queue would occasionally be corrupted. + - Added shutdown of the system timer as the workaround for Anomaly 78 and to save energy. + +** NFC ** + - Integrated fixes from EMVCo test suite (improved interoperability). + - Added automatic fix for Anomaly 181. + - Fixed a bug where HFCLK was requested too early for nRF52840 Rev. 1 chip. + - Changed the way the fixes for chip errata are switched: use chip defines from MDK instead of board defines (simplifying usage of custom boards). + +** USB ** + - Removed redundant barriers in USBD HAL. + - Fixed a bug in HID library where the report descriptor was limited to 64 bytes. + - Fixed a bug where USBD was not able to wake up after SOF event. + - Fixed a bug where the SET_ADDRESS command was not processed in time. + - USB application library (stack) now properly supports a situation when the HOST requests a descriptor but sets wLength Setup field to 0. + + +*** Known Issues +**************** + +** BLE ** + - Peer Manager: + - When a link is already secured and the peer sends a slave security request for a higher level of security, the request will not be honored. + - Service Changed indications might be silently dropped without being sent if the attempt to send them happens during an ATT MTU exchange. + - Service Changed indications might be silently dropped if the flash is full when the Service Changed flag is being stored in flash. + +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the router advertisement to be set to create a SLAAC address from the prefix. + However, RFC 7668 (https://tools.ietf.org/html/rfc7668) requires this bit to be zero. Therefore, the nd6.c from lwIP source has been modified + to relax this check. + - There are some issues when using the IoT examples against Linux Kernel 4.12+ that cause the kernel to only work with one 6LoWPAN connection. + If more than one kit is connected using 6LoWPAN, none of the nodes will be accessible. + - Scheduler has been included in most IoT examples to avoid race conditions found when using the lwIP stack, more precisely the TCP examples. + The issue was that the TCP client would stop working after about 15 hours. However, when using mbed TLS, the use of scheduler is not possible. + Therefore, the MQTT client examples might be affected by this issue. + - The use of security, both with TLS and DTLS, should be treated as experimental. + - MQTT examples cannot be used with commissioning on nRF52832. There is not enough RAM to accommodate both TLS and the commissioning service. + - If enabled, RTT logs in IoT bootloader might not be printed before resetting. + - The background_dfu example does not work. + +** Drivers and libraries ** + - SAADC driver is not handling detection limits: high and low correctly if SAADC resolution is greater than 10 bits. + - In the radio test example, modulated packets will only have the requested content in the first two bytes. + Further bytes have random values. + - In the radio test example, start_duty_cycle_modulated_tx is not working as intended. + The actual duty cycle on air is not what was requested in the command. + +** USBD ** + - Due to Anomaly 199, the USBD driver blocks code execution during EasyDMA transfer (for stability). + - USBD BLE UART FreeRTOS example is not working when combined with Nordic UART Service Client example. + + +======================================================================== + +nRF5 SDK v15.1.0 +------------------------ +Release Date: Week 34, 2018 + +Highlights: + - Added support for the new SoftDevices S140, S132, and S112 v6.1.0. + - Added new targets for running S112 on nRF52832 (PCA10040). + - Updated ESB library to support all nRF52 devices (nRF52810, nRF52832 (Rev.1 & Rev.2), and nRF52840). + - Updated SDFU to include nRF52810 target (PCA10040E). + - Released nrf_log in production quality. + +Note: Due to compatibility issues, you must run the upgrade using nRF Connect Desktop v2.5.0 or later when testing the Bluetooth examples in nRF5 SDK v15.1.0. + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.18a + - GCC: GCC ARM Embedded 6.3 2017-q2-update + - IAR: IAR Workbench 7.80.4 (IAR 8 - see note below) + - SES: SES 3.40 + +***** +Note for IAR 8 users: +(Libraries for IAR 8 require wchar_t to be of size 32 bits while IAR 7 requires 16 bits). + +To run a project using IAR 8, follow these intructions: + - Open the IAR project in IAR 8. The IAR workbench will automatically generate an IAR 8 compatible project file. + - If the project contains one of the precompiled libraries listed below, replace it with the IAR 8 compatible alternative + (there are no projects targeting nRF51 in this SDK). + - Save the project. + - When building the project, you might get the warning: "The header file 'cmsis_iar.h' is obsolete and should not be used. [...]". + - The problem is described in DevZone post: https://devzone.nordicsemi.com/f/nordic-q-a/31123/iar-ewarm-8-22-1-complains-about-cmsis_iar-h + The solution is to remove all occurrences of #include . + +The affected libraries are: + - micro-ecc crypto: + - IAR7: Includes library located in the folder named “…_iar\…”. + - IAR8: Switch to using the library from the folder named “…_armgcc\…”. + - nrf_cc310, nrf_cc310_bl, and nrf_oberon: + - IAR7: Includes the library where “_short_wchar_” is part of the file name. + - IAR8: Switch to using the library with similar naming, but where the “short_wchar” is removed. + - Gazell, NFC Tag, and 802.15.4: + - IAR7: Includes the library where the file name ends with “_iar”. + - IAR8: Switch to using the library with similar file name that ends with “_gcc”. +***** + +Supported SoftDevices: + - S112 v6.1.x + - S132 v6.1.x + - S140 v6.1.x + - S212 v5.0.x + +Supported boards: + - PCA10040 + - PCA10040E (nRF52810 emulation on PCA10040) + - PCA10056 + - PCA10059 (support in selected examples) + - D52DK1 from Garmin Canada (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** New features +***************** + +** BLE ** + - Added new targets to demonstrate the use of S112 on nRF52832 (PCA10040). + - Added "Property Read" for the Object Transfer Service client (ble_app_ots_c). + - Added a Scanning Module to simplify scanning for BLE devices in central role. + - Peer Manager: + - peer_manager_handler.h: There are now standard event handlers available to users of the Peer Manager. + The event handlers provide features like logging, automatically securing the link, and automatically + deleting the oldest bond if the flash is full. + - PM_RA_PROTECTION_ENABLED: The Peer Manager can now be configured to reject repeated security requests + from peers that failed pairing. + - PM_LESC_ENABLED: Improved LESC support. + - PM_LOG_ENABLED: Added error and warning level logging messages to the Peer Manager. + - PM_EVT_FLASH_GARBAGE_COLLECTION_FAILED: Added new event. + - Added LESC support to the following examples: ble_app_hrs, ble_app_hrs_c, and ble_app_gls. + - Added support for nRF52840 (PCA10056) in the beacon example (ble_app_beacon). + - Added Swift Pair support to the HID mouse example (ble_app_hids_mouse). + - Battery Service: Added the possibility to notify a reconnected, bonded peer of an updated battery level. + This feature is demonstrated in the Immediate Alert Server example. + +** Crypto ** + - EdDSA: Added support for Edwards-curve Digital Signature Algorithm (Ed25519). + - In documentation, added a table showing supported nrf_crypto backends for different examples: + http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.sdk5.v15.1.0/nrf_crypto_default_backends.html + +** DFU/Bootloader ** + - Added a new target to the SDFU example to demonstrate SDFU running on nRF52810 (PCA10040E). In a single bank update, there is only + about 60 kB of flash available. This restricts what can be updated. + - The bootloader settings page is now backed up before being updated. This increases protection from corruption caused by chance events + (for example, power failure) and malicious apps. + - The advertising interval of BLE DFU can now be configured in sdk_config (NRF_DFU_BLE_ADV_INTERVAL). + - The size of the application data area that is left alone by the bootloader can now be configured + in sdk_config (NRF_DFU_APP_DATA_AREA_SIZE). + - The bootloader code now supports most of nrf_crypto backends. However, the size of the binary will likely be too large if other backends + are used, so you will need to accomodate by increasing the size of the bootloader. + +** USB ** + - Added response/no response to an IN token on ISO IN endpoint with a ZLP when no data is ready. This can be set with USBD_CONFIG_ISO_IN_ZLP. + - Added support for configuration string ID. + - Added an option to give priority to isochronous transfers using USBD_CONFIG_DMASCHEDULER_ISO_BOOST. + - Implemented SOF event callback in interrupt for classes. + - Added an enum and get function for a selected protocol (boot or report) in HID. Implemented a SET_PROTOCOL propagation mechanism using + on_set_protocol methods. Buffers can now be cleared after the SET_PROTOCOL command using clear_buffer methods. + - Redesigned the idle report mechanism in HID. It now allows a callback function and handles multiple report IDs. + - Added an option to send a ZLP on write with the same size as the endpoint in CDC ACM class using APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE. + - Implemented macros to set interval for individual endpoints. See APP_USBD_EP_WITH_INTERVAL. + - Transfers in Audio class can now be started in SOF interrupt set in the app_usbd_audio_sof_interrupt_register function. + + +*** Changes +************ + +** BLE ** + - Increased the length of the advertising name for the Running Speed and Cadence sensor example (ble_app_rscs) to make it easy to verify + that it is using the extended advertising. + - Included the Scanning module into all BLE examples. This aligns how scanning is performed in these examples. + - Updated the NFC pairing examples (ble_app_hids_keyboard_pairing_nfc, ble_app_hrs_nfc_pairing, ble_nfc_pairing_reference) to start using + the LESC functionality in the Peer Manager (which uses the nrf_ble_lesc module). + - Removed the manual handling of credits for the Object Transfer Service (ble_app_ots and ble_app_ots_c). Most use cases now work faster + and simpler when the SoftDevice is controlling it. + - Updated the API documentation for advertising_init in the Advertising module (ble_advertising). It was clarified that UUID arrays were not + copied into the Advertising module. + - Advertising module (ble_advertising) is no longer dependent on the fstorage module. + - Changed the ANCS example (ble_app_ancs_c) so that it no longer performs service discovery after connecting to an already bonded peer. + - Lowered the advertising interval in the Eddystone example (ble_app_eddystone), because some advertising packets would be lost when combined + with the timeslot API. + - Reduced the maximum supported value for advertising interval in Eddystone from 20000 to 16384. If a higher value is set, the SoftDevice returns + an error code that asserts the application. + - Peer Manager: + - Various improvements to documentation. + - The Peer Manager will now take less space for the same features. + - To decrease complexity, the Peer Manager no longer uses the 'reserve' functionality in FDS, meaning that PM_EVT_STORAGE_FULL + events will come slightly later if bonds cannot be stored during bonding. + - Error event parameters now specify whether the error code is to be interpreted as an FDS_ error or an NRF_ error. + - Peers without a stored rank are now never returned from pm_peer_ranks_get(). + - The function pm_peer_data_load() now fills the array even when returning NRF_ERROR_DATA_SIZE. + - Enabled internal LESC key handling through PM_LESC_ENABLED. Function pm_lesc_public_key_set() is now deprecated because of this change. + - All examples using the Peer Manager now use the new standard event handlers. + While some examples implement custom behavior, all examples do the following: + - Log Peer Manager events (at different log levels). + - Encrypt immediately on connection with bonded peers. + - Delete old bonds to make room for new peer data. + - Some examples supporting central mode disconnect when link encryption fails. Look for functions calling pm_handler_disconnect_on_sec_failure(). + - The ble_app_bms example will now request for security procedure to be initiated if the Central does not initiate it. + +** IEEE 802.15.4 ** + - Updated the radio test example to support 802.15.4 radio modes. + +** Crypto ** + - Updated documentation about RAM requirements on mbed TLS. + - Added endianness change Curve25519 (to little endian). + - Removed the following defines. A compile error is shown if they are enabled in a configuration: + - NRF_CRYPTO_BACKEND_CC310_BL_HASH_LITTLE_ENDIAN_DIGEST_ENABLED + - NRF_CRYPTO_BACKEND_CC310_BL_ECC_LITTLE_ENDIAN_ENABLED + - NRF_CRYPTO_BACKEND_MICRO_ECC_LITTLE_ENDIAN_ENABLED + - NRF_CRYPTO_BACKEND_NRF_SW_HASH_LITTLE_ENDIAN_DIGEST_ENABLED + - nrf_crypto micro-ecc backend: Moved ECDH public key validation from the key convert function to ECDH compute + (moved from nrf_crypto_backend_micro_ecc_public_key_from_raw to nrf_crypto_backend_micro_ecc_ecdh_compute). + - Upgraded nrf_cc310 and nrf_cc310_bl to version 0.9.10 including minor changes to some default configurations. + +** DFU and Bootloader ** + - Updated documentation about how to change the existing SDFU project, so that the application can be uploaded without signature verification, + but at the same time to keep the signature verification when updating a SoftDevice and/or bootloader. + - The bootloader now does not use app_timer, which saves flash space. + - The bootloader now does the endian-conversion in code, instead of relying on endian-conversion in nrf_crypto. + +** Drivers and libraries ** + - Included new version of nrfx (v1.1.0). For the nrfx changelog, see https://github.com/NordicSemiconductor/nrfx/blob/master/CHANGELOG.md + - nrf_log: + - Updated to production quality. + - You can now store/load the filtering configuration in FDS. + - You can now control one backend from another. + - nrf_cli: Added support for terminal meta keys. + +** Proprietary ** + - Updated ESB library to support all current variants of nRF52. This mainly involves adding proper handling of Errata related to the radio. + - Added a function to skip the next packet in the TX queue. This was previously a function used internally in the module under another name. + +** USB ** + - Moved USBD strings configuration to sdk_config. + - Rebuilt MSC class write procedure. + - Moved APP_USBD_CONFIG_LOG_ENABLED to nrf_log settings. + - HID report protocol is now default after reset. + - HID default idle rate after reset can now be defined. + - OUT transfers are now dropped when clearing stall on endpoint. + - SET_ADDRESS command is now defined as a separate event in app_usbd. It does not change the state of the device anymore. + - EP0 is now disabled until USB RESET condition is detected. + - HID OUT reports are now limited to 63 bytes of data + 1 byte reserved for report ID. + + +*** Bug fixes +**************** + +** BLE ** + - Fixed a bug in the BLE UART client (ble_app_uart_c) where it would check the wrong error code when issuing multiple write commands. + - Fixed a bug in the Eddystone example (ble_app_eddystone) where the default TX power was set to 0 directly + instead of using the DEFAULT_FRAME_TX_POWER define. + - Fixed a bug in the ANCS example (ble_app_ancs) where app_timer was included too many times. + - Fixed a bug in the Advertising module (ble_advertising) where a comment referred to seconds instead of 10 ms. + - Fixed a bug in the LESC connection example (ble_app_multirole_lesc) where the procedure for connection parameter update would not be started + immediately upon connection. + - Fixed a bug where a precompiled hex was missing for Immediate Alert Server (ble_app_ias) and Service Changed server (ble_app_gatts) examples. + - Fixed a bug in the Radio Notification Event Handler (ble_radio_notification) where a missing include stopped it from compiling. + - Fixed a bug in the BLE Interactive Command Line Interface Example in service discovery procedure. + - Fixed a bug in the Alert Notification Service, where it was not possible to enable notifications for an unread alert. + - Peer Manager: + - Fixed a bug where the event PM_EVT_FLASH_GARBAGE_COLLECTED was also sent when garbage collection failed. + - Fixed a bug in pm_next_peer_id_get() where it could report a peer with no data attached to it if used during bonding. + - Fixed a bug where peer data would not be written because the internal retry mechanism failed after two attempts. + - Fixed several documentation bugs related to error codes. + +** IEEE 802.15.4 ** + - Adjusted CCA threshold value to be correct for nRF52840 Rev. 1 (different from what was available on the Engineering sample). + - Implemented a fix for Anomaly 153 (temperature correction of RSSI measurement): added an API in RAL module for calculating the corrected RSSI value. + +** Drivers and libraries ** + - Fixed a bug in the SPI manager where app_timer was included too many times. + - Fixed a wrapping issue in the Ring Buffer library. + +** DTM ** + - Added support for 8 dB on nRF52840 targets. + - Implemented the workaround for nRF52840 Anomaly 172 which caused the device to fail a test with interference in co-channels (RF-PHY/RCV/BV-29-C). + +** Proprietary ** + - Fixed a bug in bytewise_bit_swap where it was harder to backport the implementation to nRF51. + - Fixed a bug in nrf_esb_pop_tx where the packet queue would occasionally be corrupted. + - Added shutdown of the system timer as the workaround for Anomaly 78 and to save energy. + +** NFC ** + - Integrated fixes from EMVCo test suite (improved interoperability). + - Added automatic fix for Anomaly 181. + - Fixed a bug where HFCLK was requested too early for nRF52840 Rev. 1 chip. + - Changed the way the fixes for chip errata are switched: use chip defines from MDK instead of board defines (simplifying usage of custom boards). + +** USB ** + - Removed redundant barriers in USBD HAL. + - Fixed a bug in HID library where the report descriptor was limited to 64 bytes. + - Fixed a bug where USBD was not able to wake up after SOF event. + - Fixed a bug where the SET_ADDRESS command was not processed in time. + + +*** Known Issues +**************** + +** BLE ** + - Peer Manager: + - When a link is already secured and the peer sends a slave security request for a higher level of security, the request will not be honored. + - Service Changed indications might be silently dropped without being sent if the attempt to send them happens during an ATT MTU exchange. + +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the router advertisement to be set to create a SLAAC address from the prefix. + However, RFC 7668 (https://tools.ietf.org/html/rfc7668) requires this bit to be zero. Therefore, the nd6.c from lwIP source has been modified + to relax this check. + - There are some issues when using the IoT examples against Linux Kernel 4.12+ that cause the kernel to only work with one 6LoWPAN connection. + If more than one kit is connected using 6LoWPAN, none of the nodes will be accessible. + - Scheduler has been included in most IoT examples to avoid race conditions found when using the lwIP stack, more precisely the TCP examples. + The issue was that the TCP client would stop working after about 15 hours. However, when using mbed TLS, the use of scheduler is not possible. + Therefore, the MQTT client examples might be affected by this issue. + - The use of security, both with TLS and DTLS, should be treated as experimental. + - MQTT examples cannot be used with commissioning on nRF52832. There is not enough RAM to accommodate both TLS and the commissioning service. + - If enabled, RTT logs in IoT bootloader might not be printed before resetting. + - The background_dfu example does not work. + +** Drivers and libraries ** + - SAADC driver is not handling detection limits: high and low correctly if SAADC resolution is greater than 10 bits. + - In the radio test example, modulated packets will only have the requested content in the first two bytes. + Further bytes have random values. + - In the radio test example, start_duty_cycle_modulated_tx is not working as intended. + The actual duty cycle on air is not what was requested in the command. + +** USBD ** + - Due to Anomaly 199, the USBD driver blocks code execution during EasyDMA transfer (for stability). + + +======================================================================== + +nRF5 SDK v15.0.0 +------------------------ +Release Date: Week 12, 2018 + +Highlights: +- Full support for nRF52840 and production quality of libraries and examples for this device. +- Support for the new SoftDevices S140, S132, and S112 v6.0.0. +- Peripheral drivers now use nrfx. +- Extensive rework of the DFU functionality. +- Extensive rework of the cryptography library (nrf_crypto). +- USB firmware is now in production quality. +- Serialization of SoftDevices S140, S132, and S112 v6.0.0. +- IEEE 802.15.4 protocol in production quality. +- Included nrf_oberon crypto library with standard Nordic 5-clause license. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 6.3 2017-q2-update +- IAR: IAR Workbench 7.80.4 (IAR 8 - see note below) +- SES: SES 3.34 +- Linux: Ubuntu 17.04, Kernel 4.10.0. +- Jlink: 6.22g +     +***** +Note for IAR 8 users: +Libraries for IAR 8 require wchar_t to be of size 32 bits while IAR 7 requires 16 bits. +To run a project using IAR 8, follow these intructions: + - Open the IAR project in IAR 8. The IAR workbench will automatically generate an IAR 8 compatible project file. + - If the project contains one of the precompiled libraries listed below, replace it with the IAR 8 compatible alternative +   (there are no projects targeting nRF51 in this SDK). + - Save the project. + - When building the project, you might get the warning: "The header file 'cmsis_iar.h' is obsolete and should not be used. ....". +   The problem is described in DevZone post: https://devzone.nordicsemi.com/f/nordic-q-a/31123/iar-ewarm-8-22-1-complains-about-cmsis_iar-h +   The solution is to remove all occurrences of #include . + +The affected libraries are +- micro-ecc crypto: +    - IAR 7: Includes the library located in the folder named "…_iar\…". +    - IAR 8: Switch to using the library from the folder named "…_armgcc\…". +- nrf_cc310, nrf_cc310_bl, and nrf_oberon: +    - IAR 7: Includes the library where "_short_wchar_" is part of the file name. +    - IAR 8: Switch to using the library with similar naming, but where the "short_wchar" is removed. +- Gazell, NFC Tag, and 802.15.4: +    - IAR 7: Includes the library where the file name ends with "_iar". +    - IAR 8: Switch to using the library with similar file name that ends with "_gcc". +***** +  +Supported SoftDevices: +- S112 v6.0.x +- S132 v6.0.x +- S140 v6.0.0 +- S212 v5.0.x +      +Supported boards: +- PCA10040 +- PCA10040E (nRF52810 emulation on PCA10040) +- PCA10056 +- PCA10059 (support in selected examples) +- Dynastream's D52DK1 (only for ANT examples) +      +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". +      +  +*** New features +***************** +  +** IEEE 802.15.4 ** + - Added support for SES toolchain. +  +** ANT ** + - Added support for SES and GCC toolchains in the following examples: +    - ANT-FS Client +    - ANT Bootloader/DFU +  +** BLE ** + - Added support for the new SoftDevices S140, S132, and S112 v6.0.0. For more information about SoftDevice v6.0.0, refer to the SoftDevice documentation. + - Extended advertising and selection of advertising PHYs can now be configured using the advertising module (ble_advertising). + - Running Speed and Cadence Service Application (ble_app_rscs) now advertises using extended advertising. Note that this makes it incompatible with devices that do not support extended advertising. + - Added multilink support for a selected group of BLE services (including separate GATT context for each connected client). +    - Affected services: +        - Human Interface Device Service: ble_hids. +        - Nordic UART Service: ble_nus. +        - Immediate Alert Service: ble_ias. +        - Battery Service: ble_bas. +    - Added BLE Link Context Manager module +    - Modified the Immediate Alert Application to show this feature. + - Added a new application: BLE Interactive Command Line Interface Example. + - Added Device Information Service client. This module can be used to read any characteristic of Device Information Service. +    - Modified the Running Speed and Cadence Collector example application (ble_app_rscs) to show the use of this module. + - Immediate Alert Service client example application (ble_app_ias_c) is no longer experimental. + - Immediate Alert Service server example application (ble_app_ias) is no longer experimental. + - GATT Service Client Example Application (ble_app_gatts_c) is no longer experimental. + - GATT Service Server Example Application (ble_app_gatts) is no longer experimental. + - Improved the test description documentation for Continuous Glucose Monitoring Service Example Application (ble_app_cgms). It now showcases more capabilities of the application and how to test them. + - ble_conn_state: Added new function ble_conn_state_for_each_set_user_flag() which calls a function for each flag in a collection that is set. + - Peer Manager: +    - Two new configuration parameters to disable functionality to save space: +        - PM_SERVICE_CHANGED_ENABLED to enable/disable Service Changed sending. This must be enabled if Service Changed is enabled in the GATT database. +        - PM_PEER_RANKS_ENABLED to enable/disable the tracking of peer ranks. +    - The relevant APIs have gained the error code NRF_ERROR_NOT_SUPPORTED if the function is called when the configuration is disabled. + - Added NRF_SDH_BLE_GAP_DATA_LENGTH configuration (under nrf_sdh_ble) to configure BLE data length negotiated by the nrf_ble_gatt module. + - Added BLE LESC module as experimental. +  +** BLE IOT ** + - Added support for the nRF52840 (PCA10056 board) with the use of the S140 SoftDevice. +  +** NFC ** + - Added support for SES toolchain in the Adafruit Tag Reader Example. + +** Crypto ** + - Production quality nrf_crypto interface that supports software and hardware backends (using the CC310 hardware accelarator in nRF52840 devices). + - nrf_crypto API supports the following cryptographic family of algorithms (subject to support in nrf_crypto backends): +    - AES (CBC, CTR, CFB, ECB, CBC_MAC, CMAC) +    - AEAD (CCM, CCM*, EAX, GCM, ChaCha-Poly) +    - ECC (Elliptic Curve Cryptography) +        - Key generation +        - Key validation +        - Key conversions (from/to raw format) +    - ECDH (multiple curves) +    - ECDSA (multiple curves) +    - SHA-2 family hash +    - HMAC +    - HKDF +    - RNG using AES CTR or through dedicated hardware/sofware (on nRF52840) +    - Experimental Ed25519 support (available through the nrf_crypto_ecdsa API) + - nrf_crypto API support for dynamic memory management by configuration: +    - User-specified macros to NRF_CRYPTO_ALLOC and NRF_CRYPTO_FREE +    - Stack allocation (using alloca) +    - C dynamic allocation (malloc) +    - SDK Memory Manager (nrf_malloc) + - nrf_crypto backends include the following: +    - Cifra +    - mbed TLS +    - micro-ecc +    - nrf_cc310 +    - nrf_cc310_bl (code size optimized, to use in Secure DFU) +    - nRF HW (for RNG) +    - nrf_oberon +    - nRF software (legacy) + - Examples of nrf_crypto usage with the option to change the nrf_crypto backends. + - Test example to verify the cryptographic routines and APIs through standardized test vectors. +  +** DFU/Bootloader ** + - SoftDevice independence: +     - Only the BLE bootloader is now dependent on the SoftDevice. The others depend only on the MBR (which is now part of the SDK). +     - The DFU now supports updating applications that do not use the SoftDevice. Such an application must be compiled to be placed above the MBR. + - The DFU protocol has been extended to support new messages: +     - Protocol version - To retrieve information about the protocol version. +     - Firmware version - To retrieve information (size, version) about each piece of firmware on the chip. +     - Hardware version - To retrieve information (flash/RAM size, page size) about the hardware. +     - DFU Abort - To instruct the bootloader to abort the DFU procedure and reset the device. + - Configurable security: New configuration parameters to turn on and off version checking and signature checking of application transfers. Added a new example using the new configurations (open_bootloader). + - DFU Trigger (USB): Added a library to allow DFU mode to be triggered through USB in the application. The library is used in the new ble_connectivity example that uses USB CDC ACM. + - Added optional skipping of application CRC check. CRC check can be skipped on wakeup from System Off or on special value written to GPREGRET2 register. + - Added watchdog support to the bootloader. If application had enabled watchdog before resetting to the bootloader, it is fed in the bootloader. +  + ** Drivers and libraries ** + - Added support for wildcards in the CLI module. + - Added TWI sensor module. + - Added drivers for sensors on Thingy:52 (LPS22HB, BH1745, HTS221, CCS811, SX1509B, LIS2DH12). + - Added the nrfx project as a set of default drivers and provided a legacy layer for supporting deprecated API. + - Added support for filtering log messages on instance level in the logger module. Instance level logging added to nrf_balloc, nrf_queue, and nrf_atfifo. + - Added new logger backends for writing logs to flash: flashlog backend for storing logs in standard operation, crashlog backend for dumping logs on error condition. Added CLI commands for controlling data stored in flash. + - Added optional timestamp formatting in the logger.  + - Added new implementation of app_timer (libraries/timer/experimental/app_timer2.c) which does not use SWI, uses less RAM and flash, and has modular, simpler design. It shares the same API as the legacy implementation. The new implementation is used by bootloaders and peripheral/CLI. + - Added bsp_cli module to send BSP events through CLI. + - Added nrf_atflags module for atomic manipulation of bit fields. + - Added improved CLI UART backend called libUARTE. This backend is recommended when the CLI must exchange big amounts of data fast, for example when CLI is used with a script. +  +** Serialization ** + - Added serialization of the S112, S132, and S140 v6.0.0 SoftDevices. + - Added serialization connectivity application for PCA10059 using USB CDC ACM as the transport layer. +  +** USB ** + - Added example with the SoftDevice and USB (usbd_ble_uart). + - Added configuration of the self-powered descriptor bit (APP_USBD_CONFIG_SELF_POWERED). + - Added buffering of transfers in CDC. + - Added configuration of power in a descriptor (APP_USBD_CONFIG_MAX_POWER). + - Added option to specify the CDC ACM protocol. + - Added dummy interface class. + - Implemented USBD power event processing in app_usbd event queue. + - Implemented different ways of processing SOF events: +    - Normal - SOF events are pushed normally into the event queue. +    - Compress - SOF events are counted and bound with other events or executed when the queue is empty. This prevents the queue from filling up with SOF events. +    - Interrupt - SOF events are processed in the interrupt. + - Implemented Get Output Report in HID class. + - New SoftDevice API used for USB power events. + - Button events can now be sent through CLI in the usbd_cdc_acm, usbd_hid_composide, and usbd_hid generic examples. +  +  +*** Changes +************ +  +** ANT ** + - Added welcome message to all ANT examples. Logging is enabled by default in all of them. + - Removed obsolete module: ant_stack_config. The ANT SoftDevice Handler module has taken over its functionality. +  +** BLE ** + - Minor improvements to consistency of BLE examples main functions (comments, function call ordering, function names). + - BLE examples changed to use the Queued Write module (nrf_ble_qwr). Applications must explicitly configure characteristics to accept long writes. See app_ble_qwr for an example of this. This fixes a problem where peers could cause our devices to assert by issuing long writes. + - BLE examples changed to use the Power Management library. Most examples now call nrf_pwr_mgmt_run() instead of sd_app_evt_wait(). + - Eddystone modules have been moved from components/libraries to components/ble. + - ble_app_uart changed to have 247-byte MTU, up from 64. + - Peer Manager: +     - The members of pm_conn_sec_procedure_t have been renamed from PM_LINK_SECURED_PROCEDURE_* to PM_CONN_SEC_PROCEDURE_*. +     - The following functions have gained new error codes: +         - pm_conn_secure() +         - pm_peer_data_store() +         - pm_peer_ranks_get() +         - pm_peer_rank_highest() +  +** BLE IOT ** + - Minor updates in TFTP background DFU modules to align with changed DFU libraries. +  +** Crypto ** + - nrf_crypto APIs have been changed to use big-endian only. +    - Previous versions of nrf_crypto used little-endian ordering to conform to BLE requirements in LESC. +      This has now been changed to big-endian everywhere. There are conversion functions available to +      change between little-endian and big-endian input/output. +    - See the Migration Guide for details. + - nrf_crypto memory management has changed extensively. +    - See the Migration Guide for details. + - nrf_crypto configuration of frontends and backends is now primarily done through sdk_config.h. +    - See the Migration Guide for details. +  +** DFU/Bootloader ** + - Configuration parameters (sdk_config) have changed. See the Migration Guide for details. + - Refactoring: The DFU/bootloader code has been extensively refactored. +     - The split between DFU and bootloader has been improved. +        - New events from DFU. +        - Resetting has been moved from DFU to bootloader, based on DFU events. +        - Much of the code in nrf_dfu_utils has been extracted into the new nrf_bootloader_fw_activation and nrf_bootloader_dfu_timers modules. +     - Request handling module: +        - The dfu_req_handling module has been renamed to nrf_dfu_req_handler and moved to components/libraries/bootloader/dfu. +        - The request handling now uses app_scheduler and is entirely asynchronous and executed in the main context. +        - The init command validation was refactored out and into two new modules nrf_dfu_validation and nrf_dfu_ver_validation. +     - The Serial transport is now called UART. +     - The shared parts of the USB and UART transports have been placed in a separate module nrf_dfu_serial. +     - Most of the assembly code in bootloader_app_start has been replaced with C code and extracted into a separate file nrf_bootloader_app_start_final. +     - Examples: +        - The secure bootloader examples have been moved into a 'secure_bootloader' folder. +        - The experimental ANT bootloader has been moved into an 'experimental' folder. +        - The USB secure bootloader is no longer experimental. + - Bootloader examples have been reorganized. Examples "bootloader_secure_ble", "bootloader_secure_serial", and "experimental_bootloader_secure_usb" have been merged into "secure_bootloader" with projects for each transport and board. + - Write protection of the bootloader: Before booting the app, the bootloader will write-protect the flash areas of the bootloader and MBR (using BPROT on nRF52832/nRF52810 and ACL on nRF52840). +     - The BLE Buttonless SVCI interface needs access to the bootloader settings page from the application, so there is a new configuration parameter to specify whether that page should be part of the protection. +     - The SVCI interface will now return NRF_ERROR_FORBIDDEN if using the interface when the page is protected. + - WDT compatibility: The bootloader will feed the WDT if the app has started it. + - BLE DFU: +     - The BLE DFU bootloader now explicitly requests the preferred connection interval upon connection. The minimum and maximum connection intervals can be set in sdk_config.h. +     - The BLE DFU bootloader will use long ATT MTUs and data length extension when the host supports these features. This increases DFU transfer speed considerably. +     - Several stability improvements over different transport configurations. + - USB serial number: The serial number of the USB bootloaders has changed to be the same as the default BLE address (found under DEVICEADDR in FICR). + - New crypto backend for nRF52840: The bootloaders for nRF52840 use the hardware crypto backend (CC310) instead of micro-ecc. +  +** Drivers and libraries ** + - The way peripheral drivers are handled in the SDK has been reorganized: +     - Replaced existing drivers with the "external" drivers from nrfx project. See https://github.com/NordicSemiconductor/nrfx/blob/master/README.md for more information on nrfx. +     - New drivers from nrfx are located in "..\modules\nrfx". +     - Drivers replaced by nrfx are removed from "..\components\driver_nrf". +     - A glue layer is added to make the nrfx driver compatible with SDK and the SoftDevice. + - Refactored I2S driver. + - New reliable delay implementation. + - Added CLI commands to nrf_balloc and nrf_queue which print out the status of all instances present in the system. + - CLI built-in root commands: cli_stats, colors, and echo have been changed to subcommands: cli colors, cli echo, and cli stats. + - The CMSIS-SVD files with device descriptions have been moved from the "..\svd" folder to the "..\modules\nrfx\mdk" folder. + - Infineon OPTIGA: +     - Replaced "crypto\ifx_optiga_auth" example with the new one: "crypto\ifx_optiga_ecdsa_simple". +     - Updated related libraries from the "external\infineon" directory. +     - Replaced support for Infineon OPTIGA Trust E HSM with Infineon OPTIGA Trust X HSM. +     - Added support for IAR toolchain. +  +** Proprietary ** + - New Gazell functionalities: +     - Transmission statistics gathering - counts successful packet transactions and timeouts on each of the RF channels. +     - External analog frontend module control - generates TX/RX signals during transmission/receiving, which can be used to control the external PA/LNA module. + - Updated gzll_ack_payload examples with the example usage of the new Gazell features. + - Dynamic changes of TX attempts and TX power parameters are now allowed when the Gazell stack is enabled. + - Removed the nRF52840 project from ble_app_gzll example (removed "pca10056" folder). +  +** NFC ** + - Type 2 Tag Library: +    - Modified Dynamic Memory structure of the Tag. Added Terminator TLV to indicate that there is no more relevant user data after NDEF TLV. + - Type 4 Tag HAL: +    - Modified Frame Wait Time setting to support full range available on the nRF52840 Rev. 1 chip. + - Type 4 Tag Library: +    - Modified behavior of the NFC_T4T_EVENT_NDEF_READ event: the event is always triggered when the last byte of the NDEF File is sent to an NFC Reader device - even if the Reader repeats the read operation multiple times in one session, i.e. before the Reader sends a DESELECT or SLP_REQ frame. + - NFC BLE pairing library: modified to support multiple connections. + - BLE/NFC examples: updated application behavior to comply with NFC Forum user experience recommendations. + - NFC libraries which can enable nrf_log independently (using sdk_config.h) register the logger instance conditionally, i.e. only if nrf_log is enabled in the sdk_config.h +  +** USB ** + - app_usbd_init: when called with NULL configuration structure or NULL ev_handler member of a structure, the default event handler will be used. + - app_usbd_init: removed clock initialization. + - Descriptors are now generated on the fly using simple stackless thread code. + - Added a warning for wrong interface order. + - Combined USB CDC ACM driver for all examples into one. +  +    +*** Bugfixes +**************** +  +** ANT ** + - Added missing logger backends to all examples. +  +** BLE ** +  - Fixed a bug in ble_app_uart where Data Length update requests would be handled twice. +  - Fixed a bug in ble_app_uart and ble_app_uart_c where the "start" message in the main function was not followed by a line feed. This could make the applications seem unresponsive. +  - Fixed a bug in ble_app_cgms where properties of the characteristics were not configured. +  - Fixed a bug in ble_app_cgms where directed advertising was enabled by the advertising module but was ignored by the application. Directed advertising is now disabled. +  - Fixed a bug in ble_app_cgms where advertising was triggered twice when deleting bonds. The second call to advertising start would cause the example to assert on the busy error. +  - Fixed a bug in ble_app_gls  where the seconds field of the glucose measurement was never updated. +  - Fixed a bug in ble_tps where documentation for ble_tps_tx_power_level_set() was describing another unrelated function. +  - Fixed a bug in most main.c files where fds garbage collection fds_gc() would retry upon returning FDS_ERR_BUSY. However, this function call will never return FDS_ERR_BUSY. +  - Fixed a bug in nrf_ble_gatts_c where setting NRF_LOG_DEFAULT_LEVEL to debug (4) would cause an assert because it was not registered with the logger module (NRF_LOG_MODULE_REGISTER();) +  - Added missing Errata workaround to Direct Test Mode (DTM) on nRF52840. +  - Peer Manager: +      - Fixed the bonded flag in pm_conn_sec_status_get(). +      - Fixed a performance bug in peer_database.c. +      - Split the error code NRF_ERROR_INVALID_STATE from pm_conn_secure() that could have two different meanings. +  +** BLE IOT ** +  - Corrected logging module name, such that logs could be enabled in the LWIP platform module. +  - Fixed a reassembly bug in BSD socket module. +  - Fixed flushing of ports when the kit disconnects. Added API to flush the ports. +  - Added handling of BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event to generate the BLE_IPSP_EVT_CHANNEL_DATA_TX_COMPLETE in case link disconnection occured before the TX was complete. +  - Resolved an issue with MQTT/lwIP packets stuck in a TX queue. Now forcing out enqueued data before close. +  - Conformed to MQTT specification in the use of QoS flag in MQTT connect. +  +** DFU/Bootloader ** +  - Bootloaders for nRF52840 now support bootloader updates (if used with the new MBR or SoftDevice). +   +** Drivers and libraries ** +  - Extended input pin configuration in the GPIOTE driver: configuration of GPIOTE INPUT pin added, which does not change the current GPIO configuration. +  - CLI module - fixed echo command behavior. When echo is off, the command will not be printed after log print. +  - Logger modules - stability fixes (including https://devzone.nordicsemi.com/f/nordic-q-a/31178/bug-nrf_log_frontend-m_log_data-buffer-overflow). +  - More changes in drivers can be found in the modules/nrfx directory in the CHANGELOG.md file. + +** Proprietary ** + - Gazell stack: +    - Fixed a bug with high current consumption in disabled state, related with TIMER issue 78. +    - Fixed a bug with reenabling Gazell stack after the SoftDevice activity. + - Gazell Pairing Library: +    - Fixed a bug with unreserved flash memory region for the Host ID. +    - Fixed a bug with wrong initialization of database flash memory page on nRF52 chips. +  +** NFC ** + - Type 2 Tag Library: +    - Modified Dynamic Memory content of the Tag. Dynamic Lock Bytes use proper values now. +    - Updated CC1 byte setting (one of the Type 2 Tag Reserved bytes) according to the new NFC Forum Type 2 Tag Technical Specification v1.0. + - Type 2 Tag HAL: +    - Handling of erroneous NFC-A data frames (with parity and CRC errors) has been improved. + +** USB ** + - Fixed a bug in USB CDC ACM class where the APP_USBD_CDC_ACM_USER_EVT_PORT_OPEN event was not raised. + - Fixed a bug in USB CDC ACM class where RX stopped working after the port was closed or the cable was detached. + - Fixed a bug in USB MSC where it could not satisfy the number of required bytes by the host. + - Fixed a bug in app_usbd.c where APP_USBD_EVT_DRV_RESUME event was raised after a reset instead of APP_USBD_EVT_DRV_RESET. + - Fixed a bug in HID class where Remote Wake Up was not properly handled. + - Fixed a bug in nrf_drv_usbd_transfer_out_drop() where it was clearing an isochronous endpoint. + - Fixed a bug in app_usbd_core.c where transfer status was not checked during EP0 processing. + - FTPAN-171 workaround has been implemented. + - FTPAN-199 workaround has been implemented. + - Fixed minor issues. +  + +*** Known Issues +**************** +  +** Missing feature on nRF52840 ** +  - ANT protocol support is missing due to ANT SoftDevices not available for this device. +  - FreeRTOS +  - ESB +  +** BLE ** + - BLE LESC module should be treated as experimental, even though it has not been marked as such. + - Eddystone example should be treated as experimental on nRF52840. +  +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the +   router advertisement to be set in order to create a SLAAC address +   from the prefix. However, RFC 7668 (https://tools.ietf.org/html/rfc7668) +   requires this bit to be zero. Therefore, the nd6.c from lwIP source +   has been modified to relax this check. + - There are some issues when using the IoT examples against Linux +   Kernel 4.12+ which causes the kernel to only work with one 6LoWPAN +   connection. If more than one kit is connected using 6LoWPAN, none of +   the nodes will be accessible. + - Scheduler has been included in most IoT examples to avoid race +   conditions found when using the lwIP stack, more precisely the TCP +   examples. +   The issue was that the TCP client stopped working after about 15 +   hours. However, when using mbed TLS, the use of scheduler is not +   possible. +   Therefore, the MQTT client examples might be affected by this issue. + - The use of security, both with TLS and DTLS, should be treated as +   experimental. + - MQTT examples cannot be used with commissioning on nRF52832. There is not enough +   RAM to accommodate both TLS and the commissioning service. + - If enabled, RTT logs in IoT bootloader might not be printed before resetting. +  +** DFU/Bootloader ** + - Changing the backend for nrf_crypto in sdk_config.h alone is not sufficient +   because the relevant files are not included in the build and include paths. +   See the Migration Guide for a walkthrough of changing from the µECC to the +   Oberon backend. + - ble_app_buttonless_dfu will silently hang during bootup if a compatible +   bootloader, i.e. the BLE bootloader, is not present. + - SES will not detect whether the debug bootloader is too large, instead it will place the code in the MBR params page. To make SES detect this, add the following line in flash_placement.xml: +  + Place this line immediately after: + + The production bootloader is not affected by this issue. + - nrfutil version 3.5.0 has an optional argument to increase the time delay "--connect-delay ". + It is recommended to set this value to 10 when Serial DFU (UART / USB) is performed for large images (SoftDevice + Application or SoftDevice + Bootloader + Application). + - You may experience some instability with the µECC library in IAR due to faulty decoding of symbol information. Compile the µECC library without symbol information to fix these issues. + +** Proprietary ** + - Gazell stack for all devices is working with sensitivity reduced by 3 dB due to the RADIO issues 102, 106, 107, and 143. +  +** NFC ** + - NFC Type 2 and Type 4 Tag HAL modules require using TIMER 4 on nRF52840 and nRF52832 chips. +  +** USBD ** + - For the sake of stability, the USBD driver blocks code execution during EasyDMA transfer. + - Isochronous transfers must be processed as fast as possible, but using the event queue may postpone SOF processing too long if the CPU is busy. In such situations, isochronous transfers should be started inside a SOF interrupt. Configure APP_USBD_CONFIG_SOF_HANDLING_MODE as interrupt. The implementation of special SOF interrupt callbacks is subject of the future updates. +  +** Drivers and Libraries ** + - SAADC driver is not handling detection limits: high and low correctly if SAADC resolution is greater than 10 bits. + - The following examples do not have Keil 4 support: nrf_cc310, nrf_cc310_bl, ifx_optiga_ecdsa_simple. + +======================================================================== + +nRF5 SDK v14.2.0 +------------------------ +Release Date: Week 46, 2017 + +Highlights: + +- Support for the new S112 SoftDevice v5.1.0. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.80.4 +- SES: SES 3.30 +- Linux: Ubuntu 17.04, Kernel 4.10.0. +- Jlink: 6.20d + +Supported SoftDevices: +- S112 v5.1.x +- S132 v5.0.x (for v5.1.x, see the note below) +- S140 v5.0.0-2.alpha +- S212 v5.0.x +- S332 v5.0.x + +S132 compatibility: +The newly released S132 SoftDevice v5.1.0 is drop-in compatible with +S132 v5.0.0, which is included in this SDK release. +However, there are some limitations that you must be aware of when +replacing the included SoftDevice with the new one: +- In S132 v5.1.0, the SoftDevice RAM usage is reduced. Examples that are + optimized on RAM usage return a warning that the application RAM start + address can be lowered. The examples work as before but are not fully + optimized on RAM usage. +- The test images in examples\dfu\secure_dfu_test_images are tightly + connected with the precompiled HEX files located in + examples\dfu\bootloader_secure_ble\hex. Therefore, they cannot be used + in combination with the new SoftDevice. + +Supported boards: +- PCA10040E (nRF52810 emulation on PCA10040) +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - IEEE 802.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - DTM including support for the new Bluetooth 5 features + - Gazell + +The following SDK features are not supported on the new nRF52840 chip: + - ANT + - Eddystone + - ESB + - FreeRTOS + - IoT components + - Serialization of the S140 SoftDevice v5.0.0-2.alpha + +*** New features +***************** + +** BLE ** + - Added support for the S112 SoftDevice v5.1.0. + +** Crypto ** + - Added a makefile for compiling the micro-ecc library with a "soft" + FPU ABI (required for nRF52810, which does not have hardware FPU + support). + +** Drivers and libraries ** + - Added support for a "soft" FPU ABI in the Task Manager library + (required for nRF52810, which does not have hardware FPU support). + +*** Changes +************ + +** Drivers and libraries ** + - TWI Transaction Manager: Added support for passing the TWI + configuration in function nrf_twi_mngr_perform(). Pass NULL if you do + not want to use this new feature. + - Command Line Interface: Added support for commands longer than 255 + characters. + + +*** Bugfixes +**************** + +** Drivers and libraries ** + - Fixed "echo" command behavior in nrf_cli. + - Fixed a bug in nrf_ringbuf where allocation protection failed on a + second attempt to allocate a buffer in use. + - Fixed a compile error in the Task Manager library when stack guard is + off. + - Fixed invalid module names in logger output when LTO was used in the + GCC compiler. + - Fixed a bug in the logger where output could get corrupted when + logging was interrupted by NRF_LOG_PROCESS() (for example, flushing + in error handler). + +** DTM ** + - Fixed a bug preventing certain TX power values to be set. + - Set the PDU header payload type field of coded PHY 0xFF packets to + 0x04 instead of 0x03 to make the 0xFF packets valid. + +*** Known Issues +**************** + +** BLE ** + - When working on the emulated nRF52810 target, if you change the + optimization level and/or add the logging functionality, the project + might not compile or fail at runtime due to not enough flash + available for FDS or Peer Manager. + - All Bluetooth applications not using the nrf_queued_write module will + assert when a peer sends a Write request with the opcode 'cancel all + operations' (BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL), after the + SoftDevice call to sd_ble_gatts_rw_authorize_reply. This SoftDevice + call, for the opcode 'cancel all operations', returns + NRF_INVALID_PARAMS if the gatt_status is not BLE_GATT_STATUS_SUCCESS. + +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the + router advertisement to be set in order to create a SLAAC address + from the prefix. However, RFC 7668 (https://tools.ietf.org/html/rfc7668) + requires this bit to be zero. Therefore, the nd6.c from lwIP source + has been modified to relax this check. + - There are some issues when using the IoT examples against Linux + Kernel 4.12+ which causes the kernel to only work with one 6LoWPAN + connection. If more than one kit is connected using 6LoWPAN, none of + the nodes will be accessible. + - Scheduler has been included in most IoT examples to avoid race + conditions found when using lwIP stack, more precisely the TCP + examples. + The issue was that the TCP client stopped working after about 15 + hours. However, when using mbedTLS, the use of scheduler is not + possible. + Therefore, the MQTT client examples might be affected by this issue. + - The use of security, both with TLS and DTLS, should be treated as + experimental. + - MQTT examples cannot be used with commissioning. There is not enough + RAM to accommodate both TLS and the commissioning service. + +** NFC ** + - NFC Type 2 and Type 4 Tag HAL modules require using TIMER 4 on + nRF52832. + - Some mobile phone apps cannot write Type 4 Tag ("NFC Tools" and + "TagWriter" v4.1 seem to be okay to use). + +** USB (experimental) ** + - MSC implementation does not stall when the host requires more bytes + than are available in the selected descriptor. It is not a problem + for any tested driver on Windows and Linux, but still violates the + specification. + - During high USB traffic, in rare cases, communication might hang or + the endpoint data might be transferred twice. See PAN 104. + +** Drivers and libraries ** + - SAADC driver is not handling detection limits 'high' and 'low' + correctly if SAADC resolution is greater than 10 bits. + +======================================================================== + +nRF5 SDK v14.1.0 +------------------------ +Release Date: Week 42, 2017 + +Highlights: + +- Integrated nRF5 IoT SDK into nRF5 SDK. Subsequent updates of IoT components will be available through nRF5 SDK. + This release marks IoT SDK v1.0.0. The IoT SDK is no longer prototype. +- Added Segger Embedded Studio (SES) IDE support. +- The new SoC nRF52810 supported for the BLE examples using the new S112 SoftDevice and for a few peripheral examples. + Examples targeting this new device are located in the 'PCA10040E' folder. + For more details, see 'Developing for nRF52810' in the SDK documentation. +- Support for the new S112 SoftDevice. + Added new S112 target for most of the Bluetooth Peripheral examples. +- The NFC library includes an API change that may need extra attention. See Changes -> NFC BLE Pairing Library. + +The following toolchains/devices have been used for testing and +verification: +- SES: SES 3.30 +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.80.4 +- Linux: Ubuntu 17.04, Kernel 4.10.0. (for the 6LoWPAN Border Router) +- J-link: 6.20d + +Supported SoftDevices: +- S112 v5.1.0-2.alpha +- S132 v5.0.x +- S140 v5.0.0-2.alpha +- S212 v5.0.x +- S332 v5.0.x + +Supported boards: +- PCA10040E (nRF52810 emulation on PCA10040) +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - IEEE 802.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - DTM including support for the new Bluetooth 5 features + - Gazell + +The following SDK features are not supported on the new nRF52840 chip: + - ANT + - Eddystone + - ESB + - FreeRTOS + - IoT components + - Serialization of the S140 SoftDevice v5.0.0-2.alpha + +*** New features +***************** + +** Common ** + - Added support for the new chip nRF52810. + - New example flash_fstorage added to examples\peripheral\flash_fstorage. + This example shows how to use the nrf_fstorage library. + - New example flash_fds added to examples\peripheral\flash_fds. + This example shows how to use the FDS library. + - Added support in Segger Embedded Studio and armgcc for editing the sdk_config.h file in the external graphical editor (CMSIS Configuration Wizard). + +** BLE ** + - Bluetooth Peripheral examples now support the S112 SoftDevice. + S112 is designed to work with the new SoC nRF52810. Examples targeting this new device are located in folder 'PCA10040E'. + See SDK documentation for more details. + + - Added support for IPSP (Internet Protocol Support Profile). + IPSP is now based on production-quality SoftDevice S132 v5.0.0. The IPSP is, also, a qualified profile. + The IPSP service uses L2CAP Connection Oriented Channels to transfer data between devices. + - The profile implementation added to components\ble\ble_services. + - The IPSP Acceptor example added to examples\ble_peripheral\ble_app_ipsp_acceptor. + - The IPSP Initiator example added to examples\ble_central\ble_app_ipsp_initiator. + + - Added all IoT components, including BLE 6LoWPAN, Nordic's IPv6 Stack, CoAP, MQTT, DFU over TFTP, lwIP port on nRF platform, and others. + - Changes in these components in comparison to IoT SDK v0.9.0 are described in the Changes section of the release notes. + + - The SDK now supports firmware upgrade over TFTP (IPv6). + - This mechanism for updating the firmware was earlier available in the IoT SDK, and is now a part of the nRF SDK. + + - New example app_ble_gatts added to examples\ble_central\experimental\ble_app_gatts. + This application can be used to test the Service Changed indications together with app_ble_gatts_c. + + - Added S332 projects in Heart Rate Sensor and Heart Rate Collector examples. + +** ANT ** + - Added support for the new SoftDevices: S212 v5.0.x and S332 v5.0.x. + - Added S332 examples: 'Ant Shared Channels' and 'ANT and BLE Heart Rate Monitor Relay Application'. + - Added S332 projects in ANT Message Types and ANT Bootloader examples. + +** NFC ** + - Dynamic NFCID1 configuration in Type 2 and Type 4 Tag libraries. + +** USB (Experimental) ** +NOTE: The USB implementation is currently experimental and work in progress. Because of this, the code base and APIs +will change in-between SDK versions and will not necessarily be backwards compatible. This also applies to minor and +bugfix versions. Migration notes might not be complete for these changes. + - nrf_drv_usbd: + - New API function nrf_drv_usbd_ep_dtoggle_clear() implemented. + - app_usbd: + - Added a new function app_usbd_sof_timestamp_get() and its configuration APP_USBD_PROVIDE_SOF_TIMESTAMP. + This function may be used to stamp the timing of the logger messages. + - Interface selection mechanism provided. + Currently, every class that contains alternate interface settings requires the class methods + iface_select, iface_deselect, and iface_selection_get to be implemented. + No action is required if only the classes provided in the SDK are used. + - New event implemented: + APP_USBD_EVT_STATE_CHANGED – called when the state of USB interface is updated. + +** DTM ** + - Added support for the new SoC nRF52810. + +** Serialization ** + - Added solution for serialization of the combined BLE and ANT SoftDevice, using the ble_ant_app_hrm example as the use case. + - Added BLE connectivity (S132) support for nRF52810 (emulated on PCA10040). + +** Drivers and libraries ** + - Added examples: UART and SAADC for nRF52810. + Examples targeting this new chip are located in the 'PCA10040E' folder. See SDK documentation for more details. + - Added the sorted list module (nrf_sortlist). + +** IOT ** + - Added experimental examples under the "examples\iot" folder and libraries in the "components\iot" folder. + They show the usage of IPv6 over Bluetooth low energy using IPSP and 6LoWPAN. The demonstrated protocols include: + - BSD Sockets, + - UDP and TCP, + - DTLS and TLS, + - CoAP and Secure CoAP, + - MQTT and Secure MQTT, + - TFTP and LWM2M, + - Device Firmware Upgrade (DFU) over TFTP, + - DNS, ICMP, and SNTP. + + +*** Changes +************ + +** BLE ** + - BLE event handler priorities have changed (BLE_OBSERVER_PRIO). + - The order of some module BLE event handlers has been changed. This means that compiling + new sdk_config.h files with old modules might lead to crashes. + - A new priority has been added, and all BLE applications have been changed to have + the new priority (NRF_SDH_BLE_OBSERVER_PRIO_LEVELS has been changed from 3 to 4). + This means that compiling new main files with old sdk_config.h files will not work + unless NRF_SDH_BLE_OBSERVER_PRIO_LEVELS is set to 4 or more. + - Peer Manager + - Added a new event PM_EVT_CONN_SEC_PARAMS_REQ and a new function pm_conn_sec_params_reply() + to allow setting security parameters for individual security procedures. Calling + pm_conn_sec_params_reply() is optional. + - Added a new configuration parameter PM_CENTRAL_ENABLED which removes the pairing functionality + for the central role when turned off, saving code size. + - Added a new informational event PM_EVT_SLAVE_SECURITY_REQ. No further Peer Manager action is + expected from the user in response to this event. + - Added a new event PM_EVT_FLASH_GARBAGE_COLLECTED which indicates that garbage collection has happened + in the flash storage, possibly freeing up space for new bonds. + - Added new function pm_address_resolve() for resolving BLE addresses. + - NFC BLE Pairing Library + - Added library support for the PM_EVT_CONN_SEC_PARAMS_REQ event from the Peer Manager. + NOTE: + ---------------------------------------- + After the change in Peer Manager priority, this change in API was necessary to properly support all pairing modes. + Action: Call the nfc_ble_pair_on_pm_params_req() function inside the Peer Manager event handler in response to the + PM_EVT_CONN_SEC_PARAMS_REQ event: + case PM_EVT_CONN_SEC_PARAMS_REQ: + { + // Send event to the NFC BLE pairing library as it may dynamically alternate + // security parameters to achieve highest possible security level. + err_code = nfc_ble_pair_on_pm_params_req(p_evt); + APP_ERROR_CHECK(err_code); + } break; + ------------------------------------------ + - The Heart Rate Application with BLE Pairing Using NFC Pairing Library now requires LESC + pairing to enable Heart Rate notifications. + - The LESC example now generates the DH key in the main thread so as not to hold up the + SoftDevice's BLE event queue. + +** BLE IoT ** + - Changes from the previous IoT SDK v0.9.0 release: + - The 6LoWPAN library has been rewritten to adopt the new S132 v5.0.0 SoftDevice providing L2CAP Connection Oriented Channels feature. + The library is now distributed in source code format and not as a precompiled library. + - API breakers in many of the components including BLE IPSP, BLE 6LoWPAN, MQTT, nRF lwIP driver port, and background DFU. + - Deprecated the cloud examples. Cloud services used in them were not suitable any more. + The protocol features required to connect to a cloud are included and supported. + - lwIP external component has been updated to version 2.0.2. + - mbedTLS external component has been updated to version 2.4.2. + +** NFC ** + - Removed the SoftDevice from the Writable NDEF Message example. + This example no longer requires the SoftDevice. + - All NFC libraries now have static configuration in the sdk_config.h file. + +** USB (experimental) ** + - nrf_drv_usbd: + - Endpoint transfers are no longer aborted inside the USB RESET handler, + any transfer is now aborted when an endpoint is disabled. + - The nrf_drv_usbd_transfer_out_drop() function now does not start any dummy transfer – the endpoint is cleared by + writing correct values to SIZE.EPOUT registers or backdoor interface for the sample chip. + - Transfer can be started on a stalled endpoint. + In the previous version, NRF_ERROR_FORBIDDEN error was returned. + However, the possibility to stall the endpoint and prepare the answer that will be sent + after the stall is cleared by the HOST appeared to be widely used in MSC. + - Function rename: usbd_drv_ep_abort -> nrf_drv_usbd_ep_abort. + - app_usbd: + - All endpoints but 0 are disabled when the device is not configured. + This matches USB requirements. + - Function app_usbd_active_check provided – this allows to check whether + there is any active USB traffic or interface is suspended. + The macros APP_USB_STATE_BASE and APP_USBD_STATE_SUSPENDED_MASK removed. + The app_usbd_state_t enumeration now provides no information about suspended states. + Use app_usbd_active_check function whenever the SUSPEND state was checked via app_usbd_core_state_get function. + - The SETUP event processing cleaned up, normalized, and documented. + Clear rules for the order in which a class and default handlers are called. + - Functions app_usbd_core_ep_(handled_)transfer() and app_usbd_core_setup_data_(handled_)transfer() + unified and replaced by app_usbd_ep_(handled_)transfer functions: + app_usbd_core_ep_transfer() -> app_usbd_ep_transfer() + app_usbd_core_ep_handled_transfer() -> app_usbd_ep_handled_transfer() + app_usbd_core_setup_data_transfer() -> app_usbd_ep_transfer() + app_usbd_core_setup_data_handled_transfer() -> app_usbd_ep_handled_transfer() + - Classes implementation: + - Audio class implementation aligned to use the new alternate interface selection functionality. + - MSC class implementation error handling totally rebuilt to match the specification. + Now, it is stable and passes all USB precertification tests (with one small warning to be corrected in the future). + +** Crypto ** + - Infineon Optiga Trust E communication library and authentication example are now in production quality. + +** Drivers and libraries ** + - Command Line Interface (CLI) library is now in production quality. + - Logger (nrf_log) can process logs after panic mode. + - app_twi modules renamed to nrf_twi_mngr. Translation layer (app_twi.h) kept for backward compatibility. + + +*** Bugfixes +**************** + +** BLE ** + - Peer Manager: + - Fixed a bug where a bonded and encrypted link could have invalid peer ID when the + Central uses a random non-resolvable address. + - Fixed a bug where the Service Changed state was always reported as "true" when + changed. + - Fixed a bug where peer rank was not written during pm_peer_rank_highest() if the + highest ranked peer was deleted and the peer ID was reused, or if the peer rank + value was manually changed or deleted. + - Fixed a bug where pm_conn_sec_status() would incorrectly return false for bonded field when + called during the PM_EVT_CONN_SEC_SUCCEEDED event for a reconnected bonded peer. + - Fixed a bug where pm_conn_secure() would return an undocumented error code if called + multiple times before the first procedure has completed. + - Fixed the ordering of events from pm_peers_delete(). The PM_EVT_PEERS_DELETE_SUCCEEDED + will now arrive after all PM_EVT_PEER_DELETE_SUCCEEDED events. + - Fixed a bug in ble_app_queued_writes where the characteristic would use the BLE UUID type + instead of a vendor type. + - Fixed a bug in ble_app_gls where the connection handle would be unassigned before the + disconnect call is issued (The connection handle is needed for the disconnect call). + - Fixed a bug in ble_app_gls where the Record Access Control Point indications would not be retried if an indication procedure was already in progress. + - Fixed a bug in ble_app_ancs_c where a missing C++ guard prevented it from compiling + correctly using C++. + - Fixed the LESC example so that it properly handles simultaneous security operations on both + links (numeric match and DHKEY generation). + - Fixed a bug in ble_app_ias_c where receiving a "Mild Alert" would print "No Alert" on the log, and "No Alert" would print "Mild Alert". + - Fixed a bug in ble_app_cgms where the connection handle would be set to invalid before calling sd_ble_gap_disconnect(). This would cause the call to fail and the app would assert. + - Fixed a bug in ble_app_hids_keyboard and ble_app_hids_mouse where the battery reading done before the connection was secured could cause the app to assert. + - Fixed a bug in ble_app_multirole_lesc where it would not handle PHY update requests. + - Fixed a bug that could prevent FDS from working properly when using the new nrf_fstorage_nvmc backend. + - Fixed a bug that could prevent FDS from working properly when using the nrf_fstorage_sd backend with the SoftDevice disabled. + - Keil will no longer delete the SoftDevice HEX file if the flash_softdevice target is compiled. + +** Crypto ** + - Enforced the alignment on nrf_crypto buffers for signature types. + - Removed an unused file (nrf_crypto.c) that would cause compilation errors for some users. + +** DFU ** + - Added a workaround for updating SoftDevices with changed size (from SDK 12.x.y -> 14.1.x). See configuration parameter NRF_DFU_WORKAROUND_PRE_SDK_14_1_0_SD_BL_UPDATE. + +** NFC ** + - Type 4 Tag HAL: + - Handling of erroneous NFC-A data frames (with parity and CRC errors) has been + improved. + +** USB (Experimental) ** + - HAL: + - Function nrf_usbd_dtoggle_set() is fixed. The previous version was not functional. + It was working in the examples thanks to the fact that nrf_usbd_dtoggle_get() + function was called before every nrf_usbd_dtoggle_set(). + +** Drivers and libraries ** + - Fixed a bug where SPI MISO was missing a pulldown. + Currently, the pulldown status can be configured with the SDK configuration parameter: NRF_SPI_DRV_MISO_PULLUP_CFG. + - Fixed a bug where the length parameters passed to macro NRF_LOG_HEXDUMP_DEBUG were not calculated correctly. + - Fixed a bug where a user could receive a "wrong configuration" error during the compilation of SPI driver. + - Fixed a bug where extern "C" was not terminated correctly in the Logger module. + - Fixed a bug in the PPI example where Timer 2 was not generating a CC event every odd second. + - Fixed the header guard in the ble_l2cap_conn.h file. + - Fixed a bug where nrf_log could crash when heavily loaded. + - Fixed the pwm_library example which was not working correcly when compiled with highest optimization on IAR. + +** Serialization ** + - Fixed encoding of ble_gap_data_length_params_t and ble_gap_data_length_limitation_t structures. + - Fixed encoding of ble_gap_evt_auth_status_t::lesc. + - Fixed serialization of GATT MTU value + (https://devzone.nordicsemi.com/question/165596/scanner-doesnt-work-on-nrf52832sdk-14/) + - Fixed improper configuration of scheduler event size in serialized examples + (https://devzone.nordicsemi.com/question/166657/serialization-for-s132-5x-triggers-buffer-overflow-in-event-scheduling/) + + +*** Known Issues +**************** + +** BLE ** + - When working on the emulated nRF52810 target, if you change the optimization level and/or add the logging functionality, the project might not compile or fail at runtime due to not enough flash available for FDS or Peer Manager. + - All Bluetooth applications not using the nrf_queued_write module will assert when a peer sends a Write request with the opcode 'cancel all operations' (BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL), after the SoftDevice call to sd_ble_gatts_rw_authorize_reply. This SoftDevice call, for the opcode 'cancel all operations', returns NRF_INVALID_PARAMS if the gatt_status is not BLE_GATT_STATUS_SUCCESS. + +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the router advertisement to be set in order to create a SLAAC address from the prefix. However, RFC 7668 (https://tools.ietf.org/html/rfc7668) requires this bit to be zero. Therefore, the nd6.c from lwIP source has been modified to relax this check. + - There are some issues when using the IoT examples against Linux Kernel 4.12+ which causes the kernel to only work with one 6LoWPAN connection. If more than one kit is connected using 6LoWPAN, none of the nodes will be accessible. + - Scheduler has been included in most IoT examples to avoid race conditions found when using lwIP stack, more precisely the TCP examples. + The issue was that the TCP client stopped working after about 15 hours. However, when using mbedTLS, the use of scheduler is not possible. + Therefore, the MQTT client examples might be affected by this issue. + - The use of security, both with TLS and DTLS, should be treated as experimental. + - MQTT examples cannot be used with commissioning. There is not enough RAM to accommodate both TLS and the commissioning service. + +** NFC ** + - NFC Type 2 and Type 4 Tag HAL modules require using TIMER 4 on nRF52832. + - Some mobile phone apps cannot write Type 4 Tag ("NFC Tools" and "TagWriter" v4.1 + seem to be okay to use). + +** USB (experimental) ** + - MSC implementation does not stall when the host requires more bytes than are available in the selected descriptor. It is not a problem for any tested driver on Windows and Linux, but still violates the specification. + - During high USB traffic, in rare cases, communication might hang or the endpoint data might be transferred twice. See PAN 104. + +** Drivers and libraries ** + - SAADC driver is not handling detection limits 'high' and 'low' correctly if SAADC resolution is greater than 10 bits. + + +======================================================================== + +nRF5 SDK v14.1.0-1.alpha +------------------------ +Release Date: Week 32, 2017 + +Highlights: +- Integrated what was previously known as nRF5 IoT SDK into nRF5 SDK. Subsequent updates of IoT components will be available through nRF5 SDK. +- Migrated IoT components to use L2CAP Connection Oriented Channels feature of S132 v5.0.0. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.80.4 +- Linux: Ubuntu 17.04, Kernel 4.10.0. + +Supported SoftDevices: +- S132 v5.0.x +- S140 v5.0.0-2.alpha +- S212 v4.0.x + +Supported boards: +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - IEEE 802.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - DTM including support for the new Bluetooth 5 features + +The following SDK features are not supported on the new nRF52840 chip: + - ANT + - ESB and Gazell + - FreeRTOS + - Eddystone + - Serialization of the S140 SoftDevice v5.0.0-2.alpha + + +*** New features +***************** + +** BLE ** + - Added support for IPSP (Internet Protocol Support Profile). The IPSP service uses L2CAP Connection Oriented Channels to transfer data between devices. + - Implementation added to components\ble\ble_services. + - IPSP Acceptor example added to examples\ble_peripheral\ble_app_ipsp_acceptor. + - IPSP Initiator example added to examples\ble_central\ble_app_ipsp_initiator. + +** Drivers and libraries ** + - Added experimental examples under the "examples\iot" folder and libraries in the "components\iot" folder that show the usage of IPv6 over Bluetooth Smart using IPSP and 6LoWPAN. The demonstrated protocols include: + - BSD Sockets, + - UDP and TCP, + - DTLS and TLS, + - CoAP and Secure CoAP, + - MQTT and Secure MQTT, + - TFTP and LWM2M, + - Device Firmware Upgrade (DFU) over TFTP, + - DNS, ICMP, and SNTP. + +*** Changes +************ + +** BLE IOT ** + - Changes from the previous nRF5 IoT SDK 0.9.0 release + - The 6LoWPAN library has been rewritten to adopt the new S132 v5.0.0 SoftDevice providing L2CAP Connection Oriented Channels. The library is now distributed in source code format and not as a precompiled library. + - LWIP external component has been updated to version 2.0.2. + - mbedTLS external component has been updated to version 2.4.2. + +*** Known Issues +**************** + +** Overall ** + - In the UART peripheral example, only a line feed (LF) is output on startup and when resetting the board. + - Serialized Direct Test Mode does not report RX packet count correctly. + +** BLE ** + - It is possible that the Peer Manager may return corrupt data when attempting to read the GATT attributes table under some circumstances when FDS CRC checks are enabled. + - In the Multiperipheral Example, LED 3 will toggle when writing any non-zero value to it. Also, two notifications instead of one are received on the Button Characteristic (0x1524) when pressing Button 1. + - For all serialized applications, the MTU size (NRF_SDH_BLE_GATT_MAX_MTU_SIZE in sdk_config.h) should be kept at the default level. Changing this value makes the application non-functional as the connectivity application uses static size buffers. + - Eddystone Beacon Application - LED indication might differ from what is described in documentation under the Testing section. + +** BLE IOT ** + - Neighbor discovery module for lwIP requires the on-link flag in the router advertisement to be set in order to create a SLAAC address from the prefix. However, RFC 7668 (https://tools.ietf.org/html/rfc7668) requires this bit to be zero. Therefore, the nd6.c from lwIP source has been modified to relax this check. + - There are some issues using the IoT examples against Linux Kernel 4.12+ which causes the kernel to only work with one 6LoWPAN connection. If more than one kit is connected using 6LoWPAN, none of the nodes will be accessible. + +** ANT ** +- Most ANT examples do not have the nrf_log backend in the project files, so enabling logging does not have any effect. + +** NFC ** + - NFC Type 2 and Type 4 Tag HAL modules require using TIMER4 on nRF52832. + - Some mobile phone apps cannot write Type 4 Tag (the "NFC Tools" app seems to + be okay to use). + - BLE peripheral examples with NFC pairing work as expected only with Android 7.1.2. + +** DFU ** + - Downgrading from nRF5 SDK v14.0.0 to nRF5 SDK v13.0.0 has been observed to cause the v13.0.0 bootloader to corrupt itself (Upgrading works as expected). + - The S140 SoftDevice currently does not support updating of the bootloader. + - The CTX pin (P0.07) should be grounded to run the Serial Secure DFU on both nRF52832 and nRF52840 boards. + - BLE/Serial Secure DFU only supports nrfutil 2.3.0. + - For nRF52840, a combined SoftDevice and application update on Serial transport fails when using nrfutil 2.3.0. Running a single SoftDevice and application update sequentially works as expected. + + ** USB ** + - USB driver Anomaly 104 solution is very unstable in IAR compilation with high optimization level. + + +======================================================================== + +nRF5 SDK v14.0.0 +------------------------ +Release Date: Week 31, 2017 + +Highlights: +- Added nRF52810 peripheral driver support. +- Added support for the latest SoftDevice (S132 v5.0.0). +- Added a new BLE example, Object Transfer Service, that shows how to set up and use the L2CAP Connection Oriented Channels feature of S132 v5.0.0. +- Updated Direct Test Mode (DTM) to support the new features of Bluetooth 5. +- Added a new NFC example: ISO-DEP raw mode. +- Buttonless DFU feature is now in production quality. +- Added USB CDC as a transport layer for DFU (Experimental, only nRF52840). +- Added a library and examples that show how to integrate and use the Infineon OPTIGA Trust E hardware security module. +- Refactored the logging system (nrf_log) to support multiple independent backends and dynamic logs filtering. +- Refactored the console (nrf_cli). The console can now act as one of the logger backends. Bluetooth UART is now a supported transport (using the ble_nus service). + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.80.4 + +Supported SoftDevices: +- S132 v5.0.x +- S140 v5.0.0-2.alpha +- S212 v4.0.x + +Supported boards: +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - IEEE 802.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - DTM including support for the new Bluetooth 5 features + +The following SDK features are not supported on the new nRF52840 chip: + - ANT + - ESB and Gazell + - FreeRTOS + - Eddystone + - Serialization of the S140 SoftDevice v5.0.0-2.alpha + + +*** New features +***************** + +** Common ** + - SoftDevice Handler: + - Can now register 'state event observers' that are notified when the SoftDevice state changes. + - Can now register 'request event observers' that are notified when a change of the SoftDevice state is requested. + - Console: + - Advanced cooperation with the Logger module (nrf_log). Console can work as a logger backend. + - Added support for static and dynamic subcommands. + - Easy-to-use macros for creating commands and subcommands. + - Added a smart auto-completion feature for commands and subcommands. + - Added a convenient help handler. + - Added support for multiline commands. + - Added support for text edition using the following keys: Left, Right, End, Home, and Insert. + - Implemented transport layers include: Bluetooth, USB CDC ACM, UART, RTT. + +** BLE ** + - Added support the for the latest SoftDevice (S132 v5.0.0). + - Object Transfer Service added as experimental. The Object Transfer service uses L2CAP Connection Oriented Channels to transfer data between devices. + - Client implementation added to components\ble\ble_services. + - Server implementation added to components\ble\ble_services. + - Central client example application added to examples\ble_central\experimental\ble_ots_c. + - Peripheral server example application added to examples\ble_peripheral\experimental\ble_app_ots. + - GATT Service client added as experimental. The GATT Service client is used to receive Service Changed indications from the connected peer. + - Services featured in the Proximity example are now also accessible as stand-alone service examples. + - Immediate Alert Service client example application added as experimental. + - Immediate Alert Service server example application added as experimental. + - Link Loss Service server example application added as experimental. + - Added BLE transport Command Line Interface. An example "ble_app_cli" can be found in the 'experimental' folder. + +** NFC ** + - Added a new example showing how to use the NFC Type 4 Tag library in raw ISO-DEP mode: NFC UART Example. + - Added a new pairing mode in the NFC BLE pairing library that supports OOB pairing in both "Secure Connections" and "Legacy" modes. + - Added flash support in the Writable NDEF Message Example - after the NDEF update operation, the new tag content is stored in flash. + +** DFU ** + - Added production quality buttonless bootloader with support for bond sharing. + - Added configurable inactivity timeout timer that automatically resets the device in case no new commands are received before the timeout triggers. Default value is 120 seconds. + - Added support for USB CDC as a new transport layer for DFU (Experimental, only for nRF52840). + +** DTM ** + - Added support for new Bluetooth 5 features LE 2M and LE Coded PHY. + - Added support for nRF52840 devices. + +** Drivers and libraries ** + - Added a new example that demonstrates strong cryptographic authentication using the Infineon OPTIGA Trust E hardware security module. + This example uses the following two new libraries located in the 'external' folder: + - Infineon OPTIGA Trust E command library that provides a high-level API to access cryptographic and security-related functions. + - Infineon I2C Protocol Stack library that enables communication with Infineon OPTIGA Trust E and is placed on top of the TWI transaction manager (app_twi). + - Added Stack guard module that allows for enabling stack violation control. + - Added Task Manager module, a simple co-operative scheduler. + - Added fprintf module that can be used for writing C strings. + - Added Ring Buffer module that provides functions to manage a ring buffer. + - Added Memory Object module that allows for creating and managing memory object pools. + +*** Changes +************ +** Common ** + - All examples are modified to use the new SoftDevice Handler (nrf_sdh). + +** BLE ** + - BLE Connection Parameter module supports multiple peripheral links. + - BLE ATT MTU example uses nrf_cli for the user interface. + +** NFC ** + - Improved the Type 4 Tag library interoperability (added support for fragmented command APDUs and fixed DID field handling). + - NDEF record and message definition macros are defined as automatic data (used to be static). + +** DFU ** + - Serial DFU has been updated to be production quality. + +** Proprietary ** + - ESB: Added workarounds for several anomalies that were impacting performance for certain addresses. + - ESB: Added functionality to update certain radio parameters while ESB is running: + - uint32_t nrf_esb_set_retransmit_delay(uint16_t delay); + - uint32_t nrf_esb_set_retransmit_count(uint16_t count); + - uint32_t nrf_esb_set_bitrate(nrf_esb_bitrate_t bitrate); + - uint32_t nrf_esb_reuse_pid(uint8_t pipe); + - Gazell: Released in production quality, added workarounds for RADIO anomalies. + +** Serialization ** + - Added S132 v5.0.0 support. Removed support for S140 5.0.0-2.alpha. + +** Drivers and libraries ** +- Reworked and improved the fstorage library (now called nrf_fstorage). + - Now supports operation with no SoftDevice. + - Now supports operation when the SoftDevice is present and its state changes. +- Refactored nrf_log to support multiple backends. Each backend has independent, dynamic filtering of logs. +- Refactored nrf_cli to act as the logger backend. Improved user interface with smart auto-completion and easy commands addition. +- Updated drivers to work with the nRF52810 device. +- Updated Flash data storage (FDS). + - Can now work with no SoftDevice by using the nrf_fstorage_nvmc backend. + - The 'Chunk' functionality has been removed. + +*** Bugfixes +**************** + +** BLE ** + - Fixed a bug where the multiperipheral example would not be able to connect to more than one link. + +** NFC ** + - Implemented several fixes in Type 2 and Type 4 libraries (fixed nfc_t4t_parameter_set function, removed nRF52 startup code and FPU support from library compilation). + +** Drivers and libraries ** + - Fixed potential overflow in the watchdog timer (WDT) driver initialization. + - Fixed wrong header guard in nrf_nvic.h (https://devzone.nordicsemi.com/question/121041/incorrect-header-guard-in-nrf_nvich/). + - Fixed a bug where nrf_drv_spi_uninit did not clear an event (https://devzone.nordicsemi.com/question/116308/spi-init-triggers-old-nrf_spim_event_end). + - Implemented a fix for nrf_drv_spi - no pulldown on MISO line. + +*** Known Issues +**************** + +** Overall ** + - In the UART peripheral example, only a line feed (LF) is output on startup and when resetting the board. + - Serialized Direct Test Mode does not report RX packet count correctly. + +** BLE ** + - It is possible that the Peer Manager may return corrupt data when attempting to read the GATT attributes table under some circumstances when FDS CRC checks are enabled. + - In the Multiperipheral Example, LED 3 will toggle when writing any non-zero value to it. Also, two notifications instead of one are received on the Button Characteristic (0x1524) when pressing Button 1. + - For all serialized applications, the MTU size (NRF_SDH_BLE_GATT_MAX_MTU_SIZE in sdk_config.h) should be kept at the default level. Changing this value makes the application non-functional as the connectivity application uses static size buffers. + - Eddystone Beacon Application - LED indication might differ from what is described in documentation under the Testing section. + +** ANT ** +- Most ANT examples do not have the nrf_log backend in the project files, so enabling logging does not have any effect. + +** NFC ** + - NFC Type 2 and Type 4 Tag HAL modules require using TIMER4 on nRF52832. + - Some mobile phone apps cannot write Type 4 Tag (the "NFC Tools" app seems to + be okay to use). + - BLE peripheral examples with NFC pairing work as expected only with Android 7.1.2. + +** DFU ** + - Downgrading from nRF5 SDK v14.0.0 to nRF5 SDK v13.0.0 has been observed to cause the v13.0.0 bootloader to corrupt itself (Upgrading works as expected). + - The S140 SoftDevice currently does not support updating of the bootloader. + - The CTX pin (P0.07) should be grounded to run the Serial Secure DFU on both nRF52832 and nRF52840 boards. + - BLE/Serial Secure DFU only supports nrfutil 2.3.0. + - For nRF52840, a combined SoftDevice and application update on Serial transport fails when using nrfutil 2.3.0. Running a single SoftDevice and application update sequentially works as expected. + + ** USB ** + - USB driver Anomaly 104 solution is very unstable in IAR compilation with high optimization level. + + +======================================================================== + +nRF5 SDK v13.1.0 +------------------------ +Release Date: Week 27, 2017 + +Highlights: +- Added support for the SoftDevice S332 v4.0.x. +- Added serialization solution for the combined BLE and ANT SoftDevice. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.80.4 + +Supported SoftDevices: +- S132 v4.0.x +- S140 v5.0.0-2.alpha +- S212 v4.0.x +- S332 v4.0.x + +Supported boards: +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - New 804.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - Serialization of the S140 SoftDevice v5.0.0-2.alpha with UART + +The following SDK features are not supported on the new nRF52840 chip yet: + - ANT + - DTM + - ESB and Gazell + - FreeRTOS + - Eddystone + + +*** New features +***************** + +** BLE ** +- Added S332 projects in Heart Rate Sensor and Heart Rate Collector examples. + +** ANT ** +- Added support the for the new SoftDevice S332 v4.0.x. +- Added S332 examples: 'Ant Shared Channels' and 'ANT and BLE Heart Rate Monitor Relay Application'. +- Added an S332 project for the D52DK1 Development Kit in the ANT Message Types example. + +** Serialization ** +- Added a solution for serialization of combined BLE and ANT SoftDevice + using the ble_ant_app_hrm example as the use case. + + +*** Changes +************ + +** ANT ** +- Removed the nrf_sd_def.h file. It will be now distributed just like the rest of SoftDevice header files through + https://www.thisisant.com + + +*** Bugfixes +************* + +** Drivers and libraries ** +- Fixed a potential overflow in watchdog timer (WDT) driver initialization. + + +*** Known Issues +***************** + +** Overall ** +- Updating the MDK requires to manually copy the header and linker files + into the SDK folder (ARM Keil uVision 4, IAR Workbench, ARMGCC). +- When uploading an application to an nRF52 IC using nrfjprog, you must + provide the "--reset/-r" argument or powercycle the board. + +** BLE ** +- Some examples might have excessively verbose logging. +- Examples that use the Peer Manager might assert when deleting bonds, + because advertising is started twice. +- In the Proximity Application, writing "High Alert" to the AlertLevel + characteristic of the Link Loss Service does not trigger a high alert + when the link is lost. +- When an Android device is used as a peripheral, it sends slave + security request with the MITM bit set. The central applications in + the SDK will reject the security request (Pairing Failed) because + they do not support MITM. +- Advertisement intervals in the Eddystone Beacon Application are not + verified. Clients must ensure that the configured advertisement + interval is within the valid range. Note that EID/eTLM configurations + might require advertisement intervals to be larger than the default value. + +** NFC ** +- NFC Type 2 and Type 4 Tag HAL modules require using TIMER4 on nRF52832. +- Type 2 Tag on nRF52840 chips might fail unpredictably. +- Some mobile phone apps cannot write Type 4 Tag ("NFC Tool" seems to + be okay to use). + + +======================================================================== + +nRF5 SDK v13.0.0 +------------------------ +Release Date: Week 11, 2017 + +Highlights: +- Implemented a new license scheme for the SDK distribution. See the + documentation folder for details. +- Updated the Bluetooth and ANT examples to support the newest + SoftDevices S132 v4.0.2, S140 v5.0.0-2.alpha, and S212 v4.0.0. +- Included a new 804.15.4 stack library with an example. +- Released the Eddystone example and the NFC Type 4 Tag stack in + production quality. +- Added workarounds for the nRF52832 anomaly 109 (DMA: DMA access + transfers might be corrupted). +- Added serialization of the ANT S212 SoftDevice v4.0.0 (experimental). +- Added an example showing secure DFU with UART transport layer. +- This release does not support nRF51. +- This release does not support the S332 SoftDevice. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.60.2 + +Supported SoftDevices: +- S132 v4.0.2 +- S140 v5.0.0-2.alpha +- S212 v4.0.0 + +Supported boards: +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840 chip" section) +- Dynastream's D52DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - New 804.15.4 stack library with an example + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - Serialization of the S140 SoftDevice v5.0.0-2.alpha with UART + +The following SDK features are not supported on the new nRF52840 chip yet: + - ANT + - DTM + - ESB and Gazell + - FreeRTOS + - Eddystone + + +*** New features +***************** + +** BLE ** +- Added an experimental BLE Multiperipheral example + (experimental_ble_app_multiperipheral) that uses the proprietary LED + Button Service to show how a peripheral device can manage connections + with multiple peers simultaneously. + +** ANT ** +- Added serialization for S212 v4.0.0. With this solution, an ANT + application can run on any architecture, without the SoftDevice. All + SoftDevice API calls are transported via UART to an nRF52 device that + runs the ANT connectivity application (examples\connectivity\experimental_ant) + and the S212 SoftDevice. The ANT I/O example demonstrates the new + serialization solution (examples\ant\ant_io_demo, see targets: + "ser_s212_uart"). Note that the serialized solution does not support + the new API calls added in S212 v4.0.0. + The SDK folders with the ANT serialization implementation are not + marked as experimental, because the paths would be too long. +- Added a new ANT Frequency Agility example + (examples\ant\experimental\ant_frequency_agility). + +** 804.15.4 ** +- Added a full 802.15.4 stack implementation to the SDK. The library + (components\experimental_802_15_4) is available only for nRF52840 + devices. The MAC layer API is located in + components\experimental_802_15_4\api\MAC. The example application is + located in examples\802_15_4\experimental\wireless_uart. +- Added an experimental Wireless UART example (wireless_uart) that shows + how to use the new 804.15.4 stack. + +** NFC ** +- Added two experimental examples that show NFC pairing (BLE Pairing + Using NFC - experimental_ble_nfc_pairing_reference and + ble_nfc_pairing_reference_c). + +** DFU ** +- Added support for serial/UART and an example for a secure DFU + bootloader using UART (experimental). +- Implemented SoftDevice major version checks for certain upgrade types. +- Implemented a delayed reset after the DFU: After a SoftDevice, + bootloader, or SoftDevice and bootloader update, a timer will start. + If no new update is initiated before its expiration, the device will + look for a valid application and launch it. +- Added a new set of error codes (extended error codes) that the DFU + target may send as a response to the DFU controller to convey the + reason for a failure. + +** Serialization ** +- Added serialization support for the ANT S212 SoftDevice v4.0.0 + (experimental). See the ANT section for details. + +** Drivers and libraries ** +- Added workarounds for the nRF52832 anomaly 109 (DMA: DMA access + transfers might be corrupted). Affected drivers: PWM, SPIM, TWIM, + SPIS, and TWIS. +- Added several new libraries: + - Command line interface (CLI) library: Console that supports + various serial interfaces (UART, RTT, USB CDC ACM). + See the usage example in examples/peripheral/cli. + - GFX library: Graphics library that supports simple operations like + drawing circles, lines, rectangles, or bitmaps and printing + strings. GFX uses an LCD driver interface. Two implementations for + popular TFTs have been added (ILI9341, ST7735). + See the usage example in examples/peripheral/gfx. + - Serial port library: Module for handling UART communication. It + supports multibyte transfers, time-outs, and buffering of data. + The module is a replacement for app_uart. + See the usage example in examples/peripheral/serial. + - SPI transaction manager: Module for managing thread-safe access to + the SPI driver. The module supports scheduling transactions that + consist of multiple transfers. See the usage example in + examples/peripheral/spi_master_using_nrf_spi_mngr. + - Error code to string converter (STRERR): Module for converting + error codes to strings. The module is used by nrf_log. +- Added two drivers for TFT LCDs: ILI9341 and ST7735. + + +*** Changes +************ + +** BLE ** +- Updated all BLE examples to use the nRF Connect PC application + (replacing Master Control Panel). +- Modified all BLE example to have logging enabled by default, to make + testing and debugging the SDK examples more consistent. Note that + logging greatly increases power consumption. Therefore, logging should + be disabled in any final product or when performing power profiling + tests. +- Updated the Eddystone example so that it can be released in production + quality. +- Updated all BLE examples to support the newest SoftDevices S132 v4.0.2 + and S140 v5.0.0-2.alpha. +- Updated the Peer Manager to handle more than eight links. +- Updated all BLE examples to use the GATT module. +- Updated the GATT module to handle Data Length update related events. +- Improved the Alert Notification example application to more clearly + convey the Alert Notification Service. Increased the verbosity on UART + instead of relying only on the LEDs. +- Removed the experimental label from the Running Speed and Cadence + central example application. +- Cleaned up the use of RX/TX in the Nordic UART Service (NUS) to match + the terminology used in external tools (nRF Connect, nRF Toolbox). +- Modified the BLE UART example to enable the use of long ATT_MTU. + +** DFU ** +- Updated the experimental BLE Buttonless DFU Service to use the + RAM-retention register to enter bootloader mode instead of flash + access. +- Updated the experimental BLE Buttonless DFU Service to use the + Secure-DFU UUID (16-bit proprietary Nordic UUID). +- Updated the BLE Buttonless DFU characteristic to use a new + vendor-specific base UUID (0x8EC9xxxx-F315-4F60-9FB8-838830DAEA50). + The UUID changed to 0x8EC90003-F315-4F60-9FB8-838830DAEA50. +- Changed the BLE Buttonless DFU characteristic from notification to + indication. +- Changed the minimum version requirement for nrfutil to v2.2.0. + +** NFC ** +- Updated the NFC Type 4 Tag library so that it can be released in + production quality. The library was moved to components\nfc\t4t_lib. + The example that shows the Type 4 Tag library is located in + examples\nfc\writable_ndef_msg. +- Updated the BLE Heart Rate Collector Example with NFC Pairing and the + HID Keyboard Application with BLE pairing using NFC to use the NFC BLE + Pairing library (nfc_pair_lib). +- Updated the BSP NFC Module so that it can be used without restrictions + together with Type 2 and Type 4 Tag libraries. + +** Serialization ** +- Updated serialization to support the latest BLE SoftDevices S132 + v4.0.2 and S140 v5.0.0-2.alpha. + +** Drivers and libraries ** +- Updated the implementation of app_uart. +- Moved the static configuration of app_timer to sdk_config.h. +- Updated several hardware drivers: + - nrf_drv_power: Added initial support for USB plugging with SoftDevice. + - nrf_drv_pwm: Allowed for playbacks to be started using PPI. + - nrf_drv_spi: Added an abort function. + - nrf_drv_twi: Added a function for checking if the driver is busy. + - nrf_drv_uart: Added a function for checking the receiver state. + - nrf_drv_csense: Extended the driver to perform measurements using + SAADC. COMP is still supported, but it is not recommended for + production (see anomaly 84). + + +*** Bugfixes +************* + +- Fixed several bugs in secure DFU to prevent handling invalid updates. +- Updated secure DFU on nRF52840 to utilize the entire 1 MB of flash, up + from the old (unintended) limitation of 512 KB. +- Fixed a bug where ble_app_hrs_rscs_relay would not dispatch + advertising time-out events to the advertising module. +- Fixed a bug where ble_app_uart would not handle the disconnected event + if it was received before a service discovery was completed. +- Fixed a bug where ble_app_pwr_profiling did not initialize the button + module. +- Fixed a bug where ble_app_proximity would not always trigger "High + Alert" on the AlertLevel characteristic when the link was lost. +- Fixed a bug where ble_app_uart would be blocked if app_uart_put + returned an error. +- Fixed a bug where Peer Manager corrupted FDS data in flash. +- Fixed a bug where FDS records updated with fds_record_update() would + not be garbage collected. +- Fixed an unaligned access error in FDS when using certain compiler + options in GCC. +- Fixed a bug in FDS where a missing swap page went undetected. +- Fixed the tick update method in FreeRTOS. +- Fixed a bug where wake-on-field functionality would not work with Type + 2 and Type 4 Tag libraries. +- Several bugfixes and improvements on drivers: + - nrf_drv_timer: Fixed a bug in NRF_TIMER_IS_BIT_WIDTH_VALID. + - nrf_drv_saadc: Fixed a bug where nrf_drv_saadc_calibrate_offset() + enabled a wrong interrupt. + - nrf_drv_pwm: Fixed inaccurate description of the + NRF_DRV_PWM_FLAG_LOOP flag. + + +*** Known Issues +***************** + +** BLE ** +- If the S132 SoftDevice is configured with 0 Peripheral roles and 0 + Central roles, sd_ble_enable() may corrupt up to 8 bytes above the + returned app_ram_base. For applications having such a configuration, + set the application RAM start to 8 bytes or more above the returned + app_ram_base. + +** DFU ** +- The S140 SoftDevice currently does not support updating the bootloader. +- Secure DFU (serial): + - nrfutil currently does not support sending combined zip images + (SD+APP, SD+BL+APP, BL+SD). Use individually generated zip-images + instead. + - The device will not automatically boot the application after a + SoftDevice update. Reset the device manually. +- Secure DFU (BLE): Updates of SD+BL+APP may time out between the SD+BL + and APP stage on certain Android phones. Investigate the time-out + value with respect to your mobile app and consider increasing it. + + +------------------------------------------------------------------------ + +nRF5 SDK v13.0.0-1.alpha +------------------------ +Release Date: Week 50, 2016 + +This release is an alpha release and should ONLY be used for the +following purposes: +- Exploring and trying out the new Bluetooth 5 features available + with the new SoftDevices. +- Trying out new features on the nRF52840 chip. + +Highlights: +- Updated the BLE ATT_MTU Throughput Example (ble_app_att_mtu_throughput) + to showcase a PHY data rate of 2 Ms/s and coded PHY for long-range + transmission. +- Updated the cryptography library to include a CryptoCell CC310 + backend (API changes compared to SDK 12.2.0). +- Updated the BLE LE Secure Connections Multirole Example + (ble_app_multirole_lesc) to use the CryptoCell CC310 backend of the + cryptography library (available only for nRF52840). +- Added serialization of the new SoftDevices S132 v5.0.0-1.alpha and + S140 v5.0.0-1.alpha. Added USB CDC ACM serial as transport layer. +- Dropped support for nRF51 Series devices. +- Dropped support for RTX. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S140 v5.0.0-1.alpha +- S132 v5.0.0-1.alpha +- S212 v2.0.0 +- S332 v2.0.0 + +Supported boards: +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840" section) +- Dynastream's N5DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +All examples and libraries for the new chip must be treated as +experimental. +Some examples have not been ported to run on nRF52840. Check the +existing example projects to see which targets are supported. + +The following SDK features are supported on the new nRF52840 chip: + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Cryptography library including CryptoCell CC310 backend + - NFC Type 2 Tag and Type 4 Tag + - Secure DFU (only with micro-ecc backend) + - Serialization of the SoftDevices S132 v5.0.0-1.alpha and + S140 v5.0.0-1.alpha with UART and USB CDC ACM transport layers + +The following SDK features are not supported on the new nRF52840 chip yet: + - ANT + - DTM + - ESB and Gazell + - FreeRTOS + - Eddystone + + +*** New features +***************** + +** BLE ** +- Updated the BLE ATT_MTU Throughput Example to demonstrate the use of + Bluetooth 5 features: + - PHY data rate of 2 Ms/s (nRF52832 and nRF52840) + - Coded PHY for long-range transmission (nRF52840 only) + +** NFC ** +- Added a layer of abstraction for NFC OOB pairing, the NFC BLE Pairing + Library (nfc_ble_pair_lib). +- Added a central and a peripheral NFC BLE example that use the new NFC + BLE Pairing Library: + - Heart Rate Collector Application with NFC pairing (ble_app_hrs_nfc_c, + to be used with the Adafruit shield) + - BLE Peripheral example: Heart Rate Application with BLE pairing + using NFC Pairing Library (ble_app_hrs_nfc_pairing_lib) + +** Cryptography ** +- Added a backend to the cryptography library that supports the ARM + CryptoCell 310 hardware-accelerated cryptography engine. +- Updated the LE Secure Connections Multirole Example to showcase how + to use the cryptography library with the CryptoCell CC310 backend + (nRF52840 only). + +** Serialization ** +- Added serialization of the new SoftDevices S132 v5.0.0-1.alpha and + S140 v5.0.0-1.alpha. +- Added the transport layer USB CDC ACM (nRF52840 only). + + +*** Changes +************ + +** Drivers and libraries ** +- Refactored the RNG driver. + +** BLE ** +- Fixed a bug in the Multi-link Example where disconnecting all central + links would disable the app_button module. +- Fixed two bugs in the Buttonless DFU Template Application: + - The example now has writable set on the Control Point characteristic. + - The example is now using the correct part of the flash, enabling + flashing when a bootloader is present. +- Fixed a bug in the ANCS Client Application where NULL-termination of a + received attribute could happen outside its allocated buffer. +- Fixed a bug in the ANCS Client Application where using RFU attribute + IDs could cause illegal memory access. +- Modified the LE Secure Connections Multirole Example to prevent + creation of a second link to the same peer simultaneously. + +** NFC ** +- Fixed a bug in NFC Type 2 and Type 4 Tag HAL where NFC would hang when + the chip was woken up from SYSTEM_OFF and HFXO was started before NFCT + requested it. + +** Serialization ** +- UART and HCI UART transports have been optimized to better utilize + EasyDMA. + + +*** Known Issues +**************** + +** Overall ** +- Updating the MDK requires to manually copy the header and linker files + into the SDK folder (ARM Keil uVision 4, IAR Workbench, ARMGCC). +- When uploading an application to an nRF52 IC using nrfjprog, you must + provide the "--reset/-r" argument or powercycle the board. + +** BLE ** +- Some examples might have excessively verbose logging. +- Examples that use the Peer Manager might assert when deleting bonds, + because advertising is started twice. +- In the Proximity Application, writing "High Alert" to the AlertLevel + characteristic of the Link Loss Service does not trigger a high alert + when the link is lost. +- When an Android device is used as a peripheral, it sends slave + security request with the MITM bit set. The central applications in + the SDK will reject the security request (Pairing Failed) because + they do not support MITM. +- Advertisement intervals in the Eddystone Beacon Application are not + verified. Clients must ensure that the configured advertisement + interval is within the valid range. Note that EID/eTLM configurations + might require advertisement intervals larger than the default value. + +** NFC ** +- NFC Type 2 and Type 4 Tag HAL modules require using TIMER4 on nRF52832. +- Type 2 Tag on nRF52840 chips might fail unpredictably. +- Some mobile phone apps cannot write Type 4 Tag ("NFC Tool" seems to + be okay to use). + + +======================================================================== + +nRF5 SDK v12.2.0 +---------------- +Release Date: Week 49, 2016 + +Highlights: +- Added an NFC Type 4 Tag stack (experimental). +- Replaced the existing Eddystone example with a new implementation. +- Added experimental support for the new nRF52840 chip. See the section + "Scope for the nRF52840" for information about which SDK features are + supported on the new chip. + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S130 v2.0.1 +- S132 v3.0.0 +- S212 v2.0.0 +- S332 v2.0.0 + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10040 +- PCA10056 (limited support; see the "Scope for the nRF52840" section) +- PCA20006 (only for beacon examples) +- Dynastream's N5DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +*** Scope for the nRF52840 chip +******************************** +Support for the new development board PCA10056 has been added. +All examples and libraries for the new chip should be treated as +experimental. + +The following SDK features are supported on the new nRF52840 chip: + - Most BLE, hardware peripheral, and NFC examples (with some + exceptions; see the available example projects for details) + - Peripheral HAL and drivers (both for existing and new peripherals) + - Library supporting CC310 CryptoCell + - NFC Type 2 Tag and Type 4 Tag + +The following SDK features are not supported on the new nRF52840 chip: + - ANT + - Secure DFU + - Serialization + - DTM + - ESB and Gazell + - RTX and FreeRTOS + - Eddystone + + +*** New features +***************** + +** Drivers and libraries ** +- Added a SysTick driver. +- Added a queue module (nrf_queue). +- Added a memory block allocator module (nrf_balloc). +- Added an atomic operations module (nrf_atomic, nRF52 Series only). +- Added an atomic FIFO module (app_atfifo, nRF52 Series only). +- Added a power management module (nrf_pwr_mgmt). +- Added an asynchronous SD card driver using SPI. +- Ported fatfs for nRF5 (external library). + +*** nRF52840 specific updates *** +- Added a USB device stack and the following USB classes: HID, MSC, + CDC ACM, Audio. +- Added a QSPI driver for external memories. +- Added support for 2 UART instances. +- Added support for 4 PWM instances. +- Added support for more GPIO (48 pins). + +** BLE ** +- Integrated the Eddystone project from GitHub, replacing the existing + Eddystone Beacon example. The new implementation follows the + specification at https://github.com/google/eddystone (commit 97225a9 + from Sep 28, 2016). The new Eddystone library and example supports both + nRF51 and nRF52 (experimental). +- Added an example to demonstrate ATT throughput with long ATT_MTU and + DLE (experimental). +- Added a GATT module that encapsulates the long ATT_MTU feature. +- Extended the Apple Notification Center Service (ANCS) Service module + and example application: + - Added 'notification actions' that depend on the app (for example, + marking a new email as read or dialing up a missed call). + - Added functionality to retrieve app attributes, which allows to + get the name of the app that provided a notification. +- Extended the Continuous Glucose Monitoring Service (CGMS) example + application to handle greater, lesser, or equal filtering for the + Record Access control point. +- Updated the BLE examples to no longer attempt to re-initiate bonding + if encryption fails due to a missing or wrong key. + +** NFC ** +- Added support for NFC Type 4 Tag with both read and write NDEF + access (experimental). +- Added support for raw ISO-DEP transmission protocol mode. +- Added Type 4 Tag support to the Adafruit Tag Reader example. + +** Cryptography ** +- Added support for the ARM CryptoCell 310 hardware-accelerated + cryptography engine. +- Added examples to show how to use the hardware-accelerated + cryptography functionality. + + +*** Changes +************ + +** Overall ** +- Changed the default interrupt priorities for nRF52 to be the same as + the SoftDevice event priority. +- Prefixed error codes with "NRF_". +- Fixed a bug in the clock driver where the driver was failing to handle + two requests coming from the same source. +- Removed nRF52 support for RTX. RTX is now supported on nRF51 chips + only. +- Updated the example Secure DFU images. They are now created with the + debug flag enabled. +- Modified the SoftDevice header files nrf_soc.h and nrf_nvic.h to + support PCA10056 (nRF52840). +- Split up the files located in the examples\bsp folder to new locations: + components\libraries\bsp and components\boards. + +** Drivers and libraries ** +- Updated the RNG driver so that it supports the SoftDevice being + enabled and disabled. Removed the function nrf_drv_rng_pool_capacity(). +- Changed the API for function app_button_is_pushed() (located in + app_button.h). +- Extended the app_gpiote API to support more than 32 pins. Removed + unimplemented functions from the API. +- Extended the nrf_gpio API to support more than 32 pins. Removed + functions that referred to 8-bit ports (for example, + nrf_gpio_port_read). +- Removed the function nrf_drv_adc_gpio_to_ain() from the + nrf_drv_adc API. +- Removed the function nrf_drv_comp_gpio_to_ain() from the + nrf_drv_comp API. +- Removed the function nrf_drv_saadc_gpio_to_ain() from the + nrf_drv_saadc API. + +** BLE ** +- Fixed an issue that would cause some central examples to fail when + restarting scanning using a whitelist. +- Updated the Peer Manager modules to return NRF_ERROR_STORAGE_FULL + instead of NRF_ERROR_NO_MEM. +- The field "peer_id" in the Peer Manager structure + "pm_peer_data_bonding_t" has been renamed to "peer_ble_id". +- Fixed an issue where the Database Discovery Module would not + re-initialize properly upon successive discoveries. +- Fixed an issue where the Database Discovery Module would fail to + discover the extended properties descriptor and the characteristic + user description descriptors. +- Fixed an issue where the Apple Notification Center Service (ANCS) + example application could crash if the connecting iPhone disconnected + immediately after connecting. + +** NFC ** +- Modified the Adafruit NFC Shield library to support reading Type 2 and + Type 4 Tags. +- Improved performance of the Adafruit library in Type 2 Tag reader mode + (faster read). +- Added LE Secure Connections OOB values encoding in ble_pair_msg. +- Enabled dynamic update of the TK value in ble_pair_msg. + + +*** Known Issues +**************** + +** Overall ** +- Updating the MDK requires to manually copy the header and linker files + into the SDK folder (ARM Keil uVision 4, IAR Workbench, ARMGCC). +- When uploading an application to an nRF52 IC using nrfjprog, you must + provide the "--reset/-r" argument or powercycle the board. +- RTX is not supported on nRF52 chips. + +** BLE ** +- Some examples might have excessively verbose logging. +- In the Proximity Application, writing "High Alert" to the AlertLevel + characteristic of the Link Loss Service does not trigger a high alert + when the link is lost. +- When an Android device is used as a peripheral, it sends slave + security request with the MITM bit set. The central applications in + the SDK will reject the security request (Pairing Failed) because + they do not support MITM. +- Eddystone Beacon Application: + - Advertisement intervals are not verified. Clients must ensure that + the configured advertisement interval is within the valid range. + Note that EID/eTLM configurations might require advertisement + intervals larger than the default value. + - Caution: On nRF51 devices, eTLM calculation takes around 500 ms + and is performed once per EID slot in the same interrupt level + priority as the 'Unlock' functionality. Therefore, if multiple EID + slots and an eTLM slot are configured, the client might not be able + to unlock a beacon that has an eTLM slot and uses the default + advertisement interval. To resolve this issue, increase the + advertisement interval. +- Buttonless DFU Template Application (experimental): + - The project setup of the example is wrong and does not fit into the + available space below the DFU bootloader. To fix this problem, + change the IROM1 size from 0x61000 to 0x59000. In addition, comment + out the code section that reserves a codepage at 0x7E000 for MBR + parameters. For details, see + https://devzone.nordicsemi.com/question/100609/sdk-12-bootloader-erased-after-programming/ + - To switch to DFU mode, you must write to the DFU control point. + However, this characteristic is set as read only. Add the following + code line to enable the write property: + char_md.char_props.write = 1; + For details, see + https://devzone.nordicsemi.com/question/93414/sdk12-ble_app_buttonless_dfu/#95079 + + +** NFC ** +- NFC Type 2 and Type 4 Tag HAL modules require using TIMER4 on nRF52832. +- Type 2 Tag on nRF52840 chips might fail unpredictably. +- Some mobile phone apps cannot write Type 4 Tag ("NFC Tool" seems to be + okay to use). + + +======================================================================== + +nRF5 SDK v12.1.0 +---------------- +Release Date: Week 40, 2016 + +Highlights: +- Added serialization of the S132 SoftDevice v3.0.0. Serialization of S130 is now deprecated. +- Included the latest MDK v8.9.0 with a crucial workaround for nRF52832 Errata 108: +http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.Rev1.errata/anomaly_832_108.html + +The following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S130 v2.0.1 +- S132 v3.0.0 +- S212 v2.0.0 +- S332 v2.0.0 + +Supported IC revisions: +- nRF51422/nRF51822 IC revision 3 +- nRF52832 IC revision 1 + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10040 +- PCA20006 (only for beacon examples) +- Dynastream's D52 Starter Kit (only for ANT examples) +- Arduino Primo v2.1 (board header only) +For other devices and boards, see the SDK documentation, section "Using the SDK with other boards". + +*** New features +**************** +** Overall ** +- Serialization of the S132 SoftDevice v3.0. + + +*** Changes +*********** + +** Overall ** +- Includes the latest Nordic MDK v8.9.0. +- Small documentation updates. + + +*** Known issues +**************** + +** Overall ** +- Updating the MDK requires to manually copy the header and linker files + into the SDK folder (ARM Keil uVision 4, IAR Workbench, ARMGCC). +- When uploading an application to an nRF52 IC using nrfjprog, you must + provide the "--reset/-r" argument or powercycle the board. + +** BLE ** +- When performing service discoveries after a reconnect, + ble_db_discovery might fail to initialize. Refer to this link for a fix: + https://devzone.nordicsemi.com/question/92452/nrf52-ble_db_discovery-failed-to-initialize-correctly-when-repeats-the-service-discovery/ +- The "UART/Serial Port Emulation over BLE" (ble_app_uart) example + does not compile with nrf_log enabled (missing nrf_log sources) +- Some examples might have excessively verbose logging. +- Performing pairing without bonding will cause examples to assert. To + fix this, make sure the call to pm_peer_rank_highest() during + PM_EVT_CONN_SEC_SUCCEEDED happens only when the procedure is + PM_LINK_SECURED_PROCEDURE_BONDING. +- When an Android device is used as a peripheral, it sends slave + security request with the MITM bit set. The central applications in + the SDK will reject the security request (Pairing Failed) because + they do not support MITM. + +** Secure DFU ** + - nRF Toolbox for iPhone: + - When an error occurs, nRF Toolbox does not automatically + disconnect. You must therefore reset the board manually to + disconnect before you can connect again. + - It is not possible to abort a transfer when the device connection + is lost. + - On resumption, nRF Toolbox does not call execute, which makes it + impossible to resume a transfer. + - When transferring a combined SoftDevice and bootloader image, the + bootloader might not be updated. + - On nRF52 devices, the DFU operation is sometimes reported as + completed, even though the device is not updated. + +** NFC ** +- NFC Type 2 Tag HAL requires using TIMER4 on nRF52832. + +------------------------------------------------------------------------ + +nRF5 SDK v12.0.0 +---------------- +Release Date: Week 35, 2016 + +Highlights: +- Added a secure DFU bootloader example and bootloader libraries. + This is an improved implementation that replaces the legacy DFU. +- Added an implementation of the Continuous Glucose Monitoring + Service (CGMS). +- Added support for the S132 SoftDevice v3.0.0. +- Added support for the S212 and S332 SoftDevices v2.0.0. +- Added a capacitive sensor driver and library (csense). +- Added Gazell support on nRF52 (experimental). +- Added new SDK configuration header files to manage static + configuration of an application. +- Overhauled the log subsystem. +- Removed support for the PCA10036 board and nRF52832 Engineering A + and B MCUs. +- Included a critical MDK update (v8.7.1). +- Added support for the CMSIS DSP library. +- Missing feature: Serialization of the latest S132 SoftDevice v3.0.0 + API (work in progress). + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.18a +- GCC: GCC ARM Embedded 4.9 2015q3 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S130 v2.0.1 +- S132 v3.0.0 +- S212 v2.0.0 +- S332 v2.0.0 + +Supported IC revisions: +- nRF51422/nRF51822 IC revision 3 +- nRF52832 IC revision 1 +- nRF52832 Engineering C + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10040 +- PCA20006 (only for beacon examples) +- Dynastream's D52 Starter Kit (only for ANT examples) +- Arduino Primo v2.1 (board header only) +For other devices and boards see the SDK documentation, section +"Using the SDK with other boards". + + +*** New features +**************** + +** Overall ** +- Added a secure DFU bootloader example and bootloader libraries. This + is an improved implementation that replaces the legacy DFU. The + example includes support for cryptographically signed operations. + +** Drivers and libraries ** +- Added a capacitive sensor driver and library for nRF51 and nRF52 + based systems. +- Added an app_timer profiler to get maximum operation queue usage. +- Reduced RAM usage in app_timer and changed the app_timer_cnt_get + function (see the migration note in the Timer library documentation). +- Added pull-up configuration to the TWIS driver. +- Added an FFT FPU example with the CMSIS DSP library. + +** BLE ** +- Added a Continuous Glucose Monitoring Service (CGMS) implementation, + including an example application (experimental). +- Added a Bond Management Service (BMS) implementation, including an + example application (experimental). +- Expanded APIs to support Privacy 1.2. +- Updated Direct Test Mode (DTM), including support for nRF52. + +** ANT ** +- Added new examples: Continuous Waveform Mode, High Duty Search and + Background Scanning, and Time Synchronization. + +** NFC ** +- Added an NFC BSP module (bsp_nfc) and an example showing the usage of + NFC as a wakeup source. + +** Proprietary ** +- Gazell: Ported examples and library to nRF52 (experimental). + + +*** Changes +*********** + +** Overall ** +- Added a new log system across all SDK sources. Replaced printf and + the old log system. + +** Drivers and libraries ** +- Unified the configuration subsystem and moved configuration to one + file (sdk_config.h). +- Changed the NRF51 and NRF52 ifdefs in drivers to peripheral related + ifdefs. +- Improved the PWM library (app_pwm): SET/CLEAR tasks instead of TOGGLE + in nRF52. +- Updated the TWI driver to de-configure GPIO pins in the uninit + function (power-saving change). +- Unified field names in HAL. +- FreeRTOS fixes: + - Fixed invalid assertion. + - Improved tickless mode. +- Simplified the TWI sensor example. +- Added PCA10031 support to the led_softblink and low_power_pwm + examples. + +** Serialization ** +- No support. + +** BLE ** +- Removed the Device Manager modules. All example applications now use + the Peer Manager. +- Removed the pstorage module. All example applications now use the + fstorage module. + +** ANT ** +- Moved the following examples from experimental to production level: + - Advanced Burst + - Asynchronous Transmitter + - Continuous Scanning Controller + - Debug + - Message Types + - Relay + - Search Sharing + - Search Uplink + +** NFC ** +- Moved BLE OOB Pairing Data encoding to a separate module + (nfc_ble_oob_advdata). +- Modified nfc_t2t_lib and hal_nfc_t2t to conform with Nordic's + coding standard. + + +*** Fixed issues +**************** + +** Drivers and libraries ** +- APP_FIFO: Fixed an issue with app_fifo_write writing one byte even + though it was requested to write zero bytes. +- APP_BUTTON: Memory improvements. +- GPIOTE: Fixed handler pointer checking. +- PDM: Fixed high power usage and unexpected restart after calling + nrf_drv_pdm_stop(). +- QDEC: Fixed QDEC un-initialization sequence. +- SAADC: Added missing channel calibration. +- SAADC: Fixed high power consumption and burst mode (oversampling + without external trigger). +- SPI: Fixed STOPPED interrupt handling. +- SPIS: Fixed registers in get function of the amount of TX and RX done. +- TWI: Fixed misc sending bytes and misleading error codes. +- TWI: Added pin toggling functionality configuration during init (pin + toggling sequence during init may cause issues with some devices). +- UART: Fixed data corruption at 1 Mbaud and race conditions. +- DELAY: Fixed nrf_delay_us(0) case. + +** BLE ** +- Fixed an issue where BLE example applications could assert if Button + 2 was held to start advertising while in a connection. +- Fixed several minor documentation mistakes that could make testing + the BLE examples less clear. + +** ANT ** +- Fixed channel type setup in the following examples: Broadcast, Multi + Channels, and Continuous Scanning Controller. + +** NFC ** +- NDEF Text record: Fixed UTF selection. +- NDEF message size calculation. + + +*** Known issues +**************** + +** Overall ** +- Updating the MDK requires to manually copy the header and linker files + into the SDK folder (ARM Keil uVision 4, IAR Workbench, ARMGCC). +- When uploading an application to an nRF52 IC using nrfjprog, you must + provide the "--reset/-r" argument or powercycle the board. + +** BLE ** +- Some examples might have excessively verbose logging. +- Performing pairing without bonding will cause examples to assert. To + fix this, make sure the call to pm_peer_rank_highest() during + PM_EVT_CONN_SEC_SUCCEEDED happens only when the procedure is + PM_LINK_SECURED_PROCEDURE_BONDING. +- When an Android device is used as a peripheral, it sends slave + security request with the MITM bit set. The central applications in + the SDK will reject the security request (Pairing Failed) because + they do not support MITM. + +** Secure DFU ** + - nRF Toolbox for iPhone: + - When an error occurs, nRF Toolbox does not automatically + disconnect. You must therefore reset the board manually to + disconnect before you can connect again. + - It is not possible to abort a transfer when the device connection + is lost. + - On resumption, nRF Toolbox does not call execute, which makes it + impossible to resume a transfer. + - When transferring a combined SoftDevice and bootloader image, the + bootloader might not be updated. + - On nRF52 devices, the DFU operation is sometimes reported as + completed, even though the device is not updated. + +** NFC ** +- NFC Type 2 Tag HAL requires using TIMER4 on nRF52832. + + +======================================================================== + +nRF5 SDK v11.0.0 +---------------- +Release date: Week 10, 2016 + +Highlights: +- Combined SDK supporting both the nRF51 and the nRF52 Series +- Moved Peer Manager out of experimental +- Moved NFC libraries out of experimental and added support for low + power mode +- Added drivers for all nRF52 peripherals +- Added serialization of the S132 and S130 SoftDevices +- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, S212 v0.9.x, + and S332 v0.9.x +- Replaced the Enhanced ShockBurst library with a new implementation + (based on µESB) +- Included a critical MDK update (v8.5.0) +- Removed support for CMSIS Packs + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.16a +- GCC: GCC ARM Embedded 4.9 2015q1 +- IAR: IAR Workbench 7.30.4 + +Supported SoftDevices: +- S130 v2.0.0 +- S132 v2.0.0 +- S212 v0.9.x +- S332 v0.9.x + +Supported IC revisions: +- nRF51 IC revision 3 +- nRF52 IC revision 1 +- nRF52 Engineering C +- nRF52 Engineering A and Engineering B (see Compatibility) + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10036 (see Compatibility) +- PCA10040 (see Compatibility) +- PCA20006 (only for beacon examples) +For other devices and boards, see the SDK documentation, section +"Using the SDK with other boards". + +Compatibility: +The SoftDevices that are supported in this SDK are not compatible +out-of-the-box with nRF52 Engineering A and Engineering B (the +IC revisions present on all versions of PCA10036 and on PCA10040 +v0.9.0). +However, you can use the latest SoftDevices on Engineering A and B +nRF52 chips for development purposes if you implement the +workaround for anomaly 73 (TIMER: Event lost, see +http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52/dita/nrf52/errata.html). + +*** New features +**************** + +** Drivers and libraries ** +- Added a COMP driver (nRF52 only) + +** BLE ** +- Extended the Peer Manager functionality: + - Added an additional data unit (Peer Rank) that can be used for + tracking which bonds are most (and least) recently used + - Added support for LE Secure Connections in Peer Manager + (experimental) +- Added an example application for LE Secure Connections (experimental, + support for Keil5, IAR, and GCC only) + +** ANT ** +- Added new examples (experimental): + - Advanced Burst + - Asynchronous Transmitter + - Continuous Scanning Controller + - Debug Demo + - IO Demo + - Message Types + - Search Sharing + - Search Uplink +- ANT OTA bootloader application now uses the SoCLibrary API to perform + NVIC operations instead of direct operations +- Added multiprotocol examples for the S332 SoftDevice: + - Heart Rate Monitor Relay Application + - Shared Channels (experimental) + +** Serialization ** +- Added serialization of the S130 and S132 v2.0.0 SoftDevices + +** NFC ** +- Added a generic NDEF message parser that can parse NDEF messages to + the format that is used by the generic NFC NDEF message builder +- Added a module and example for creating NDEF text records +- Added and modified NFC pairing examples (experimental): + - HID Keyboard Application with BLE pairing using NFC (new) + - Heart Rate Application with BLE pairing using NFC (improved user + experience) + +** Proprietary ** +- Added a Low Power Transmitter/Receiver example for ESB + +*** Changes +*********** + +** Overall ** +- Support for CMSIS Packs has been removed. The SDK is delivered as zip + file only. + +** Drivers and libraries ** +- The MSB and LSB macros have been renamed to MSB_32 and LSB_32. Code + using these macros should be changed to use either the 16- or the + 32-bit variant. + +** BLE ** +- Multi-instance handling of Service client modules has been greatly + improved. The client examples now handle service discovery in the main + application context. The main application context must manage which + client instance belongs to which connection link. +- The Multi-link Example has been modified to demonstrate multiple + client instances in a better way. +- The ble_app_multilink_peripheral example has been removed. + ble_app_blinky now acts as the peripheral for ble_app_multilink_central. +- Heart Rate Application with RTX: Support for nRF52 has been removed. +- The Peer Manager is no longer experimental. +- The following BLE examples now use Peer Manager: + - Central: + Running Speed and Cadence Collector (ble_app_rscs_c) + - Central and Peripheral: + BLE Relay (ble_app_hrs_rscs_relay) + BLE LE Secure Connections Multirole (ble_app_multirole_lesc) + - Peripheral: + Alert Notification (ble_app_alert_notification) + Proximity (ble_app_proximity) + Glucose (ble_app_gls) + HID Keyboard Application with BLE pairing using NFC (experimental_ble_app_hids_keyboard_pairing_nfc) +- The behavior of Peer Manager and Device Manager has changed to reject + pairing requests from already bonded peer centrals. +- Several BLE peripheral examples now support the S332 SoftDevice. +- Minor bugfixes in DFU. + +** ANT ** +- The ANT bootloader was aligned to MBR version 2.0.0. +- The following ANT examples now support the S332 SoftDevice + (experimental): + - ANT Bootloader/DFU + - Message Types + +** NFC ** +- The Adafruit Tag Reader Example has been extended to show added NDEF + parsing functionality. +- The NFC Type 2 Tag HAL was improved with a workaround for supporting + low power mode. + +** Proprietary ** +- A new implementation of the Enhanced ShockBurst (ESB) protocol + supporting both nRF51 and nRF52 has been added. + +*** Fixed issues +**************** + +** Drivers and libraries ** +- GPIOTE: Fixed the problem of lost events in low-accuracy sense toggle + mode +- SAADC: Added functionality to use one AIN with multiple channels +- UART: Fixed a glitch on TX pin when initializing the driver +- UART: Fixed the problem that TX bytes were sent in wrong order in + app_uart_fifo + +** BLE ** +- Removed a vulnerability in Peer Manager and Device Manager that would + allow malicious attackers to overwrite the bonding information of a + bonded device + +** ANT ** +- Fixed the handling of send-until-success request types in the ANT + request controller +- Fixed an ant_evt_t structure member alignment bug + +** NFC ** +- Fixed the NFC examples to work when the UART logger is enabled +- Fixed a buffer leakage bug in the module for creating + application/vnd.bluetooth.le.oob records + +*** Known issues +**************** + +** Drivers and libraries ** +- Using the NVIC API directly and not through a SoftDevice causes + problems, especially when NVIC_EnableIRQ or NVIC_DisableIRQ are called + from critical sections. + +** BLE ** +- All BLE examples have been tested only on PCA10028 and PCA10040. +- BLE Examples that use pairing are incompatible with examples in SDK + version 6.1 and earlier that do not use pairing. + +** ANT ** +- Previous versions of the ANT DFU example are incompatible with the ANT + S212/S332 SoftDevices version 0.9.x. + +** NFC ** +- NFCT requires using TIMER4 on nRF52832. + +** FPU ** +- When the FPU is in use, it triggers the FPU_IRQn interrupt when one of + the six exception flags (IDC, IXC, UFC, OFC, DZC, IOC) is set. + The FPU interrupt will always set the pending flag (even if the + interrupt is not enabled), irrespective of whether the user is + interested in the exception bit. + The pending flag then prevents the SoftDevice from going into low + power mode when sd_app_evt_wait() is called. + Therefore, always clear the exception bits and the pending interrupt + before calling sd_app_evt_wait(). See the code below for an example + implementation. + FPU exception bit definition: + http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABBFJEC.html + Example code: + { + // Set bit 7 and bits 4..0 in the mask to one (0x ...00 1001 1111) + #define FPU_EXCEPTION_MASK 0x0000009F + + ... + /* Clear exceptions and PendingIRQ from the FPU unit */ + __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); + (void) __get_FPSCR(); + NVIC_ClearPendingIRQ(FPU_IRQn); + + /* Call SoftDevice Wait For event */ + error_code = sd_app_evt_wait(); + } + + +======================================================================== + +nRF5 SDK v11.0.0-2.alpha +------------------------ +Release date: Week 51, 2015 + +Highlights: +- Common SDK supporting both the nRF51 and the nRF52 Series +- Added support for SoftDevices S130 v2.0.0, S132 v2.0.0, and S212 v0.5.1 +- Permanently removed support for SoftDevices S110 and S120 +- Temporarily removed support for ANTBLE SoftDevices +- Enhanced Peer Manager and FDS modules +- Enhanced DFU module +- Configured nrf_log to use UART by default +- Added HardFault handler +- Added drivers for nRF52 peripherals: nrf_drv_i2s, nrf_drv_pdm, + nrf_drv_pwm +- Enhanced drivers to work for both nRF51 and nRF52: nrf_drv_twi, + nrf_drv_spi, nrf_drv_uart, nrf_drv_timer, nrf_drv_ppi, nrf_drv_clock +- Added FreeRTOS and RTX support for nRF52 +- Added NFC modules: Type 2 Tag parser, generic NDEF message builder, + new NFC records and messages +- Added support for Adafruit PN532 NFC shield to provide NFC Forum + Device (Poller) functionality +- Improved support for NFC: enhanced NFC Type 2 Tag library and + Connection Handover module + +The following toolchains/devices have been used for testing and +verification: +- ARM: MDK-ARM version 5.16a +- GCC: GCC ARM Embedded 4.9 2015q1 +- IAR: IAR Workbench 7.30.4 +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit +- Windows 8.1 + +Supported SoftDevices: +- S130 v2.0.0-7.alpha +- S132 v2.0.0-7.alpha +- S210 v5.0.0 +- S212 v0.5.1.alpha + +Supported boards: +- PCA10028 +- PCA10031 +- PCA10036 +- PCA10040 +- PCA20006 (only for beacon examples) +- Dynastream's N5DK1 (only for ANT examples) + +For other devices and boards, see the SDK documentation, section "Using +the SDK with other boards". + + +Drivers and libraries: + + New features: + - Added driver and example for PWM peripheral (nrf_drv_pwm). + - Added driver and example for I2S peripheral (nrf_drv_i2s). + - Added driver for PDM peripheral (nrf_drv_pdm). + - Enhanced nrf_drv_twi and nrf_drv_spi to support AUTOLOG and + triggering transfers from PPI. + - Added double buffering of RX buffers to nrf_drv_uart. + - Extended nrf_drv_timer to support more compare channels and low + power counter mode in nRF52. + - Extended nrf_drv_ppi API to support forks. + - Added support for FreeRTOS and RTX on nRF52. + - Simplified SPI and SPIS examples. + + Fixed issues: + - In certain cases, FreeRTOS on nRF51 kept interrupts disabled after + context switch (see https://devzone.nordicsemi.com/question/57993/tickless-freertos-in-sdk-100-app_uart). + + Known issues: + - The FreeRTOS nRF51 port has a wrong assertion during system startup. + If you are using assertions, you can safely ignore it. Alternatively, + comment out line 188 in port_cmsis.c. + + Changes: + - Enhanced nrf_drv_clock driver (asynchronous clock management). + + +Serialization: + + - Work in progress; not included in this release. + + +ANT: + + New features: + - Added support for the S212 SoftDevice v0.5.1.alpha. + - Added ANT DFU support for nRF52. + + Known issues: + - When using the ANT OTA Updater v1.2. for nRF52, there is a flash + memory address limitation of 0x40000 (256 KB) for the application. + + +BLE: + + Changes: + - All BLE examples have been tested only on PCA10028 and PCA10040. + - The S13x SoftDevice v2.0.0-7.alpha is configurable, which leads to a + variable RAM setup: + - Added a macro to the softdevice_handler module to check the RAM + configuration against the SoftDevice parameters. + - Added a wrapper function for the sd_enable function to the + softdevice_handler module, which can output the required RAM + start address if the one passed to the SoftDevice is not + correct. + - DFU: + - Added an experimental nRF52 bootloader. + - Updated the SoftDevice initalization according to API changes in + S132 v2.0.0-7.alpha. + - Updated to MBR version v2.0.0-1 alpha. + - Introduced nrf_log as default logging module (UART) in all BLE + examples. + - Peer Manager & FDS have received incremental improvements and bug + fixes. + + Known issues: + - In the HRS/RSCS Relay example, button presses do not have any effect. + - ble_app_cts_c requires an increased UART_TX_BUF_SIZE. The size can be + set in nrf_log.c. + - DTM for nRF52 does not support long packets according to the + Bluetooth 4.2 specification. + - Inconsistent behavior in DFU with devices running Android v6.0.1. + - The BLE and serial DFU examples do not work when using CMSIS Packs. + Use the zip version of the SDK instead. + + +NFC: + + New features: + - Added a Type 2 Tag parser. + - Added a generic NFC NDEF message builder (the builder is used to + implement all specific records and messages). + - Added modules to create Windows LaunchApp records, Android + Application Records, and common application launch messages. Added + an associated example. + - Ported the Adafruit NFC library for the Adafruit PN532 Shield, which + provides NFC Forum Device capabilities. Added an associated example + to read tags. + - Added modules to create application/vnd.bluetooth.le.oob records, + application/vnd.bluetooth.ep.oob records, ac records, Hs records, + and BLE pairing messages. + + Changes: + - Improved the NFC Type 2 Tag library: tested and power-optimized the + library and enhanced it with RTT logger capability. + - Re-implemented NFC URI record and message. Refactored the associated + example. + - Enhanced and re-implemented the NFC Connection Handover solution + (pairing using NFC). + - Re-implemented the BLE NFC pairing example. + + Known issues: + - NFC examples do not work when UART logger is enabled. + + +======================================================================== + +nRF51 SDK v10.0.0 +----------------- +Release date: Week 46, 2015 + +Highlights: + - New BLE Peer Manager (experimental), replacement for the BLE Device + Manager + - FreeRTOS support + - New ANT modules, additional examples, and new and expanded ANT+ + profiles + - Support for Dynastream's N5 Starter Kit + - Three new BLE Services + - Precompiled HEX files + +The following toolchains/devices have been used for testing and +verification: + - ARM: MDK-ARM version 5.14.0.0 and 5.16a + - GCC: GCC ARM Embedded 4.9 2015q1 + - IAR: IAR Workbench 7.30.4 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported SoftDevices: + - S110 v8.0.0 + - S120 v2.1.0 + - S130 v1.0.0 + - S210 v5.0.0 + - S310 v3.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + - Dynastream's N5DK1 (only for ANT examples) + + For other devices and boards, see the SDK documentation, section "Using + the SDK with other boards". + +Changes: + + Drivers and libraries: + New features: + - Ported FreeRTOS to run on nRF51. Added two FreeRTOS examples: one + to run on bare metal and one running a BLE HRS example using the + S110 and S130 SoftDevices. + - Added a TWI transaction manager module for managing access to an + I2C bus. Added an example that uses this module to control two + sensors on the same I2C bus. + - Added an example that shows how to use the TWI driver. + - Added a low-power PWM module (software-controlled low-accuracy + PWM). Added an example that shows how to use this module. + - Added an LED softblink module that uses the low-power PWM. Added + an example that shows how to use this module. + - Ported app_uart to use the UART driver and moved it to the + libraries folder. + - Ported app_gpiote to use the GPIOTE driver. + - Added nrf_log, a logging module that supports printf and that can + use either UART or SEGGER RTT as transport medium. + Fixed issues: + - Mailbox module moved out of serialization. + - Bug fixes in app_timer module. + - App_timer module no longer requires to define the number of + timers used in the application. + - Bug fixes in PWM module. + Changes: + - FIFO library: Extended APIs for multi-byte read and write to the + FIFO. + - Memory Manager module: + - Extended number of block categories to 7 (from 3). + - More RAM-efficient management of memory blocks. + - Added a diagnostic function to help determine the right + configuration needed for the application. + + Serialization: + New features: + - Added a command for resetting the connectivity chip. + + ANT: + New features: + - Added the following new ANT modules: + - ant_encryption + - ant_key_manager + - ant_search_config + - Extended/changed the following existing ANT modules: + - ant_channel_config + - ant_stack_config + - ant_state_indicator + - Refactored the ANT/ANT+ examples and profiles to make them look more + similar to the BLE profiles and examples: + - The following ANT+ profiles have been extracted and extended: + Bicycle Power (ant_bpwr), Bicycle Speed & Cadence (ant_bsc), + Stride Based Speed & Distance (ant_sdm) + - All ANT+ examples have been refactored to use extracted + profiles. + - All ANT+/ANT examples have been refactored to use created + modules. + - Added three new ANT examples: + - ant_scalable + - ant_scalable_encrypted + - ant_scan_and_forward + + BLE: + - Added an experimental module named Peer Manager. This module will + eventually replace the existing Device Manager. The new Peer Manager + improves on the Device Manager in multiple ways, mainly by + supporting concurrent central and peripheral connections. + - Added an experimental flash memory module named Flash Data Storage + (FDS), which greatly reduces the need for time-consuming write and + clear operations. When using FDS, data can be arbitrarily long or + short (within about a page). All pieces of data are tagged with + types, which makes it easy to version data. + - Updated the experimental HRS/RSCS Relay example: + - It now uses the new Peer Manager instead of the Device Manager. + Therefore, it now supports bonding in both central and peripheral + roles. + - It uses the new nrf_log module, which can use SEGGER RTT. + - Removed the app_s130_demo example. + - Added an experimental example supporting the Eddystone beacon + format. + - Added the BLE Connection State module, which keeps track of certain + states of each connection (for example, whether it is encrypted) and + can also keep track of user-defined states. + - Added the Mapped Flags module, which keeps track of flags that are + mapped to keys. It is used by the BLE Connection State module. + - Added ble_gatt_db.h (containing a GATT service structure) and + modified ble_db_discovery module to use it. + BLE Services: + - Updated the Bluetoothds_template application (experimental) to be + compatible with Bluetooth Developer Studio v1.0 and the Nordic + Semiconductor NRF5X v1.1.8 plugin. + - Added three new services: + - Location Navigation Service (experimental) + - Proprietary LED Button Service (experimental) + - Nordic UART Client Service (experimental) + +Fixed issues: + - App_pwm occasionally gives inverted signal. + +Known issues: + - Device Manager is not supported in multi-role S130 operation. + - Device Manager works in peripheral or central only operation on + S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum + connection interval of 11.25 ms. The application cannot handle + connection intervals lower than 11.25 ms and may undergo a system + reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware + update process, consider increasing the connection + interval used by the master. + - The old manual procedure for testing buttonless DFU, as specified in + the documentation, can lead to the DFU process hanging or returning + an error when used with Master Control Panel 3.8 and newer. + - Bootloader binaries (.bin files) generated with the GCC makefile + should not be used. Instead, generate the bootloader bin files using + nrfutils, found on GitHub. + +======================================================================== + +nRF52 SDK v0.9.2 +---------------- +Release date: Week 42, 2015 + +This is an amendment to nRF52 SDK v0.9.1. + +Highlights: + - New targets to enable the two near field communication (NFC) + examples to run on the new PCA10040 development board with + nRF52832 IC rev. Engineering B. + +Libraries: + - Extended the NFC HAL layer of the NFC library to support the NFCT + peripherial for both the chip version delivered with the nRF52 + Preview Development Kit (Engineering A: QFAA-AA0, QFAA-AC0, + CGAA-AA0) and the chip version delivered with the nRF52 Development + Kit (Engineering B: QFAA-BA0, QFAA-BB0, CHAA-AA0, CHAA-AB0). + +Examples: + - Added PCA10040 as target bord for the following examples: + - Heart Rate Example with pairing over NFC + - NFC URL Record Application + +Known issues/workarounds: + - To use the software workarounds implemented for PCA10036 (part + of nRF52 Preview Development Kit), globally define + HAL_NFC_ENGINEERING_A_FTPAN_WORKAROUND in your project. + - The TIMER4 peripheral is used to implement one of the workarounds + for PCA10036. This workaround is not used for PCA10040. + - The ble_app_hrs_pairing_nfc example is unable to wake up from + system off. + +======================================================================== + +nRF52 SDK v0.9.1 +---------------- +Release date: Week 29, 2015 + +This is an amendment to nRF52 SDK v0.9.0. + +Highlights: + - Support for near field communication (NFC) + +Libraries/Services: + - Added a library that supports Type 2 NFC-A tag functionality in + read-only state + - Added a module to generate NFC NDEF messages for BLE pairing over NFC + - Added a module to generate NFC NDEF messages with an URI record type + - Extended the ble_advdata module + +Examples: + - Added ble_app_hrs_pairing_nfc example that demonstrates pairing over + NFC (with S132 SoftDevice) + - Added record_url NFC example that demonstrates exposing a URL record + (without SoftDevice) + +Limitations: + - The current version of the NFC library uses TIMER4. + - The ble_app_hrs_pairing_nfc example has been tested only with Samsung + Galaxy S6. + - If the path to the SDK directory is too long, compilation in Keil fails. + To work around this problem, move the SDK higher in the folder tree + or use shorter folder names. + +======================================================================== + +nRF51 SDK v9.0.0 +---------------- +Release Date: Week 28, 2015 + +Highlights: + - Support for S210 SoftDevice v5.0.0 + - Support for S310 SoftDevice v3.0.0 + - Documentation moved to Infocenter + - DFU Signing using Elliptic Curve Cryptography added as experimental + - Available in the zip file only + - Running Speed and Cadence relay example showing concurrent + central/peripheral functionality of S130 + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.14.0.0 + - GCC: GCC ARM Embedded 4.9 2015q1 + - IAR: IAR Workbench 7.20 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported SoftDevices: + - S110 v8.0.0 + - S120 v2.1.0 + - S130 v1.0.0 + - S210 v5.0.0 + - S310 v3.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section + "Using the SDK with other boards". + +Changes: + + - Flash access module has been refactored (pstorage). + + ANT: + - Both the S310 and the S210 SoftDevices now support an extended + number of ANT channels (16). + + + Libraries: + - Heart Rate Monitor Profile + - ANT stack configuration + - ANT channel configuration + - ANT channel state indicator + - ANT pulse simulator + + Examples: + - The ANT HRM examples have been refactored. + - The Bicycle Power examples (ant_bicycle_pwr) support S310. + + ANT + BLE (S310): + The following examples were added: + - Bluetooth LE and ANT combined heart rate example (ble_ant_app_hrm). + - Experimental ANT Shared Channels (experimental_ant_shared_channel_master_to_master, + experimental_ant_shared_channel_slave). + + BLE: + - Advertising module has a new mode: Low Duty Cycle Directed Advertising. + - Running Speed and Cadence Client added as experimental. + - Bluetooth Developer Studio template added as experimental. + - Heart Rate Sensor example (ble_app_hrs) supports S310. + - Running Speed and Cadence example (ble_app_rscs) supports S310. + - Combined Peripheral and Central example added as experimental. + - DFU Signing using Elliptic Curve Cryptography added as experimental + (using the same elliptic curve and hashing algorithm as Bluetooth + Low Energy 4.2 Secure Connections). + +Fixed issues: + - Pstorage now supports updates of bond split across two pages. + - Advertising module can be set to infinite time-out. + - Corrected clock source in BLE multiactivity beacon example. + - Serialization HCI transport layer: Receiving packet-buffer is not + freed while sending ACK or NACK. + +Known issues: + - Device Manager is not supported in multi-role S130 operation. + - Device Manager works in peripheral or central only operation on + S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum + connection interval of 11.25 ms. The application cannot handle + connection intervals lower than 11.25 ms and may undergo a system + reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware + update process, consider increasing the connection interval used + by the master. + - App_pwm occasionally gives inverted signal. + - The old manual procedure for testing buttonless DFU, as specified in + the documentation, can lead to the DFU process hanging or returning + an error when used with Master Control Panel 3.8 and newer. + +======================================================================== + +nRF52 SDK v0.9.0 +---------------- +Release date: 17.06.2015 + +Highlights: + - Support for PCA10036 board v1.0.0 with nRF52832 QFAAAA + - Support for S132 SoftDevice v1.0.0-3.alpha (hex included) + - Support for S212 SoftDevice v0.2.0-1.alpha + - Support for Keil5 without CMSIS Packs + - Support for GCC + - Same structure as nRF51 SDK v8.1.0 + - New peripheral drivers + - Documentation moved to Infocenter + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 5.14.0.0 + - GCC: GCC ARM Embedded 4.9 2015q1 + - Windows 7 SP1 64-bit + +Supported SoftDevices: + - S132 v1.0.0-3.alpha + - S212 v0.2.0-1.alpha + +Supported boards: + - PCA10036 v1.0.0 + +Examples: + - Most examples are ported from nRF51 SDK v8.1.0 + - BLE examples run with the S132 SoftDevice + - ANT examples run with the S212 SoftDevice + - The following examples are included: + - BLE peripheral examples + - BLE central example + - New BLE combined central and peripheral example + - ANT examples + - HW peripheral examples + - New SAADC example + - New TWI master with TWI slave example + - BLE/serial DFU bootloader + - Direct Test Mode Application + +Drivers: + - Includes all drivers from nRF51 SDK v8.1.0 + - New drivers: + - SPI driver that supports SPI and SPIM + - UART driver that supports UART and UARTE + - SAADC HAL driver + - TWI slave driver + - SAADC driver + +Libraries/Services: + - Same functionality as for nRF51 SDK v8.1.0 + - The following libraries and services are included: + - BLE libraries + - BLE Services + - Transport Services + - Other libraries/components + +Known issues: + - Device might reset when a Bluetooth link layer procedure and flash operation happens in parallel. + - Inconsistent behavior with Nexus devices running Android v5.1.1, for example: + - DFU fails + - Link loss might reset the nRF52 device + (such behavior might occur with other devices as well) + - After a power cycle, a UART lockup between Segger J-Link and nRF52 might occur + - Before a serial DFU operation or DTM can be executed, "nrfjprog --reset" must be run + +======================================================================== + +nRF51 SDK v. 8.1.1 +------------------ +This is a supplement to the nRF51 SDK v8.1.0 release notes. +This release does not include any code changes compared to nRF51 SDK v8.1.0., except for a minor addition that is described in the "Changes" section. + +Fixed issues: + + - Project does not compile if nrf_drv_ppi is used together with SoftDevice S110, S120 or S210. + Issue exists only in CMSIS PACK release. + +Changes: + - Released new SoftDevice packs: nRF_SoftDevice_S110.8.0.1, nRF_SoftDevice_S120.2.0.1 and + nRF_SoftDevice_S210.4.0.1-5 with updated nrf_sd_def.h. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 1.0.0 + - S210 4.0.1 + +======================================================================== + +nRF51 SDK v8.1.0 +---------------- + +Highlights: + - Support for SoftDevice S130 v1.0.0 + - Serialization supporting SoftDevice S110, S120, and S130 + - ANCS updated and no longer in experimental state + - GCC updated to new version: ARMGCC 4.9 q1-2015 + - DFU example now has support for IAR and GCC + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM version 4.72.10, 5.13.0.0, 5.14.0.0 + - GCC: gcc-arm-embedded 4.9 2015q1 + - IAR: IAR Embedded Workbench for ARM version 7.20.2 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices: + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 1.0.0 + - S210 4.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + ANT + BLE (dual stack): + - Not included in this release due to conflicting interface between SoftDevice S310 and S110. Use SDK v7.2.0 for S310 support. + - S310 support will be reintroduced in a future release. + BLE: + - SoftDevices: + - Support for S130 v1.0.0. + - Serialization: + - Fully serialized S110, S120, and S130 API. + - Modules/Services: + - New button module (bsp_btn_ble) that enables functionality such as disconnect, turn off whitelist, go to sleep. + - Advertising module now supports scan response data + - Examples: + - ANCS example is no longer in experimental state. + Proprietary: + - IAR support for proprietary examples. + +Peripheral drivers & libraries: + - New peripheral drivers: TWI, SWI, and GPIOTE. + - New PWM driver. PWM example updated to use the driver. + +Fixed issues: + - NRFFOSDK-2044: Fixed issue in app_gpiote. + - NRFFOSDK-3855: Fixed issue in Current Time Service. + +Known issues: + - Device Manager is not supported in multirole S130 operation. + - Device Manager works in peripheral or central only operation on S130. This must be decided at compile time. + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time. + + - BLE: + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v8.0.0 +---------------- + +Highlights: + - Support for the latest S110, S120, and S130 SoftDevices. (S310 is not supported.) + - SoftDevices included in the SDK. + - Greatly increased driver and HAL coverage. + - New service client and profile example: Current Time Service/Time Profile. + - IAR support for most examples. + +The following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.10, 5.13.0.0, 5.14.0.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: IAR Embedded Workbench for ARM version 7.20.2 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices: + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + +Supported SoftDevices: + - S110 8.0.0 + - S120 2.0.0 + - S130 0.9.0-1.alpha + - S210 4.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + Toolchain/IDE: + - The nRF51 SDK now supports the following toolchains in most examples: + - Keil 5.14 (with packs) + - Keil 5.14 (without packs) + - Keil 4.72.10 + - ARM GCC 4.7 2013q1 + - IAR 7.20.2 + - The supported SoftDevices are now included in the SDK and can be flashed directly from + Keil, as a separate target. + + ANT + BLE (dual stack): + - Removed support for the S310 SoftDevice for BLE API compatibility reasons. For support, + use SDK v7.2.0. + + BLE: + - SoftDevices: + - The SDK now supports the S110 SoftDevice v8.0.0. + - The SDK now supports the S120 SoftDevice v2.0.0. + - The SDK now supports the S130 SoftDevice v0.9.0-1.alpha. + - Serialization: + - Serialization support has been removed. For support, use SDK v7.2.0 with appropriate + SoftDevices. + - Modules/Services: + - Added a new advertising module (ble_advertising) that provides automatic handling of + directed/fast/slow advertising, with and without whitelist. + - Nordic UART Service (ble_nus), detached from the UART over BLE Example. + - Added Current Time Service Client (ble_cts_c). + - Service Changed characteristic has been implemented for DFU, so that the indication is + sent when transitioning between application and bootloader. + - Implemented a mechanism for sharing of IRK and LTK from application to bootloader. + This allows for whitelist advertising and reconnection in DFU mode using existing + keys. + - Examples: + - The UART over BLE Example is no longer experimental. + - Added a Time Profile (ble_app_cts_c) example using the Current Time Service Client + implementation. + + Drivers/Libraries: + - Added hardware abstraction layer for the following hardware peripherals: + - ADC (Analog-to-digital converter) + - CLOCK (Clock management) + - LPCOMP (Low power comparator) + - PPI (Programmable Peripheral Interconnect) + - QDEC (Quadrature decoder) + - RNG (Random number generator) + - RTC (Real time counter) + - TIMER (Timer/counter) + - WDT (Watchdog timer) + - Added drivers for the following peripherals: + - CLOCK (Clock management) + - LPCOMP (Low power comparator) + - PPI (Programmable Peripheral Interconnect) + - QDEC (Quadrature decoder) + - RNG (Random number generator) + - RTC (Real time counter) + - TIMER (Timer/counter) + - WDT (Watchdog timer) + - Added modules: + - app_simple_timer (Simple timer based on TIMER1) + + Hardware Examples: + - Added: + - adc_simple (NRF_ADC) + - clock (NRF_DRV_CLOCK) + - lpcomp (NRF_DRV_LPCOMP) + - qdec (NRF_DRV_QDEC) + - simple_timer (APP_SIMPLE_TIMER) + - wdt (NRF_DRV_WDT) + - Modified: + - ppi (NRF_DRV_PPI) + - rng (NRF_DRV_RNG) + - rtc (NRF_DRV_RTC) + - timer (NRF_DRV_TIMER) + +Fixed issues: + - Fixed pstorage issue where different applications could write to the same page. + +Known issues: + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval used by the master. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + - BLE: + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v7.2.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12, 5.13 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Supported devices + - This SDK is optimized for IC revision 3. + For details, see the "nRF51 Series Compatibility Matrix" document (ATTN-51) available on + www.nordicsemi.com. + + Note 1: To run the ANT examples, you must use an nRF51422 device. + Note 2: Some of the examples using the SoftDevice will not fit on the 128 kB variant of the + chip. + Note 3: Some of the serialization examples are too big to be compiled using the free version + of Keil. + +Supported SoftDevices: + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 2.0.1 + +Supported boards: + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other devices and boards, see the SDK documentation, section "Using the SDK with other + boards", or use SDK v6.x.x. + +Changes: + - ANT: + - ANT-FS client example: Added callback to allow applications to execute custom code while + waiting for the burst to complete + - Major rework on ANT DFU example + - Added new ANT hub-2-hub/shared channel example + - Added S310 target support for DTM example + - BLE DFU is now supported for S310 + +Fixed issues: + - ANT: + - ANT-FS: Fixed bug with transfer sequence number error causing download failures + - ANT-FS: Fixed bug where upon exhaustion of m_retry, the link time-out has been mistakenly + disabled by a burst transfer + - Fixed issue in linker script for S310 + - Fixed memory corruption issue by using dedicated buffers for ANT and BLE stack events + respectively on S310 + - Fixed an issue where the ANT OTA Updater application v0.8 would not support hex files + with code size larger than 65535 bytes + +Known issues: + - SEGGER J-Link software has some issues with Keil. + See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for details. + - Keil 5.13 may issue a warning about missing packs even when all Nordic Semiconductor packs are + correctly installed. + - The DFU over BLE example has been tested to work with a minimum connection interval of + 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may + undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider + increasing the connection interval used by the master. + + - ANT: + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + - BLE: + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not + support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power + optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 + examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and + a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing + examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two + pages. + + - Proprietary: + - Temperature example does not give sane output values. This is a hardware-related issue + described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box + with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy + Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and + channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the + nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v7.1.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Tested with devices: + - nRF51422 QFACAB + + For others devices, use SDK 6.x.x. + +Supported SoftDevices: + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 2.0.0 + +Supported boards: + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other boards, use SDK V6.x.x. + +Changes: + - Experimental support for over-the-air firmware update using the ANT radio protocol + - New experimental example ANT relay demo + - Support for S310 ANT+BLE version 2.0.0 + - Re-introduce Device Firmware Update via UART + - BLE DFU single bank support for bootloader+softdevice update + +Fixed issues: + - NRFFOSDK-3119 Fixed issue in app_timer where issuing start/stop from interrupt context caused long delays + +Known issues: + + - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master + + ANT + - The OTA Updater application v.0.8 does not support hex files with code size larger than 65535 bytes. + - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + BLE + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. + + Proprietary: + - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 7.0.1 +------------------ +This is a supplement to the nRF51 SDK v7.0.0 release notes. +This release does not include any code changes compared to nRF51 SDK v7.0.0, except for a minor addition that is described in the "Changes" section. + +Fixed issues: + + - Replaced DeviceFamilyPack v1.1.3, which has a wrong URL, with DeviceFamilyPack v1.1.4. + - Added a version field to Pack examples descriptions (NordicSemiconductor.nRF_Examples.pdsc). + - Added missing Nordic Semiconductor nRF51 MDK installer to the repository distribution (nRF51_SDK_x.x.x_xxxxxxx.zip). + - Added missing message sequence charts to the documentation. + - Changed incorrect description of supported SoftDevices in the release notes (see below for the correct list of supported SoftDevices). + +Changes: + + - Added all the register and bitfields for the SPIM peripheral (present in the nRF51802 device) to the HAL header files and replaced the pack nRF_Drivers v1.0.0 with nRF_Drivers v1.1.0. + +Supported SoftDevices: + + - S110 7.1.0 + - S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + +nRF51 SDK v7.0.0 +---------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.12 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: no support in this release + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - Windows 8.1 + +Tested with devices: + + - nRF51422 QFACAB + + For others devices, use SDK 6.x.x. + +Supported SoftDevices: + + - S110 7.1.0 + - S120 1.0.0 S120 1.0.1 + - S130 0.5.0-1.alpha + - S210 4.0.1 + - S310 1.0.0 + +Supported boards: + + - PCA10028 + - PCA10031 + - S110 connectivity support for Wavetek WT51822 + + For other boards, use SDK V6.x.x. + + + +Changes: + + - New folder structure + - Moved from installer to CMSIS pack format + - Added support for PCA100028 and PCA10031 + - Deprecated support for previous boards + - Added support for RTX tickless + + ANT + - Changed the ANT examples to support S210 SoftDevice v4.0.1 + - Added experimental Background Scanning example + + ANT + BLE (Dual stack) + - Removed support for S310 SoftDevice (for support, use SDK v6.x.x) + + BLE + - DFU: Added experimental mechanism to exchange encryption keys between application and BootLoader + - DFU: Added identification of firmware versions in the init packet + - Added experimental BLE nRF UART example + - Added experimental ANCS example + - Added experimental example demonstrating usage of S130 SoftDevice + - Added HRS example with RTX + + Proprietary + - Deprecated the following examples (for support, use SDK v6.x.x): + * ADNS2080 Mouse Sensor Driver Application + * Cherry8x16 Keyboard Application + * Button Debouncer Example + * nRF6350 Radio Configuration Example + * PWM Analyzer Example + * Motor Control Example + * TWI Master Example + + +Fixed issues: + + - NRFFOSDK-362: Reset button won't work after programming without cycling the target power + - NRFFOETT-205: The nRF51822 installer will not run if no C:\ drive exists - No installer + - NRFFOSDK-236: When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear - No installer + - NRFFOSDK-363: Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + +Known issues: + + - SEGGER J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. The application cannot handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during the firmware update process, consider increasing the connection interval used by the master + + ANT + - NRFFOSDK-366: ANT-FS host: download sometimes fails when downloading a large file + - NRFFOSDK-755: HRM TX buttons example may report wrong total elapsed time + + BLE + - NRFFOSDK-3135: S120 examples: RAM is limited to 16 kB, because S120 V1.0.1 does not support utilizing the whole flash on the QFACAB chip + - NRFFOSDK-119: Only the ble_app_proximity_low_power and ble_app_hrs applications are power optimized + - S120 examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if the peer loses the bond and a rebonding occurs, flash clear fails and a DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - A few APIs of the Device Manager are not implemented. Also, documentation providing examples of how the API can be used is missing. + - NRFFOSDK-2824: Device Manager (pstorage) does not support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Temperature example does not give sane output values. This is a hardware-related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit the gzll_params.h file used in the nRF24Lxx projects or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 6.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x/5.11.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 7.0.0 + - S120 1.0.0 + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - Added Keil 5 uvprojx files for most example projects. + - Extended GCC support, most examples now supplied with Makefiles. + + ANT + - None. + + ANT + BLE (Dual stack) + - None. + + BLE + - Device firmware upgrade with support for OTA update of SoftDevice, app and bootloader is no longer in experimental status. + - Buttonless bootloader mode, enter bootloader mode via over-the-air command (see ble_app_hrs example, using ble_app_hrs_dfu.uvproj project). + - Device manager (BLE bond handling) for S110 and S120 are no longer in experimental status. + - db_discovery module (for GATT database discovery) for S120 is no longer in experimental status. + - New reliable transport layer for S110 SoftDevice serialization. + - Example ble_app_hrs_c (heart rate collector) for S120 is no longer in experimental status. + - Example ble_app_multilink_central for S120 is no longer in experimental status. + - Example ble_app_multilink_peripheral for S110 is no longer in experimental status. + - Experimental examples ble_app_ancs and ble_app_multiactivity have been deprecated from this release. + - Experimental example ble_app_uart for pca10001 has been deprecated from this release. + + Proprietary + - None. + +Fixed issues: + - NRFFOSDK-2884: Fixed issue in app_button module (function app_button_is_pushed). + - NRFFOSDK-1341: Added missing characteristic in Blood Glucose application. + - NRFFOSDK-2859: Removed redundant code in Blood Glucose application. + - NRFFOSDK-2557: Fixed some doxygen documentation errors. + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 6.0.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x/5.11.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 7.0.0 + - S120 1.0.0 + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - Added partial support for Keil 5 uvprojx files. + + ANT + - None + + ANT + BLE (Dual stack) + + BLE + - New module device manager replaces bond manager for storing persistent data + - Experimental device manager support for s120 (BLE central) + - S110 serialization solution has been reworked + - 100% s110 BLE APIs are now serialized + - S110 support for application concurrent multiprotocol radio access + - Pstorage module: Added API for doing range updates + - Experimental: Device firmware upgrade now supports updating both SoftDevice and bootloader for s110 + + Proprietary + - Enhanced ShockBurst: Added nrf_esb_reuse_pid() function to API, giving "reuse payload" functionality. + - Gazell: Added "suspend" mode enabling sharing of radio and PPI. + - Gazell: HW resources are released when Gazell is being disabled or entering suspend mode. + - Gazell: HW resources are reconfigured when Gazell is being enabled or exiting from suspend mode. + +Fixed issues: + + - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. + - SDK documentation has been splitted into 4 seperate documents with a common index page. + + ANT + - None + + ANT + BLE (Dual stack) + - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behaviour. + + BLE + + Proprietary + - Enhanced ShockBurst/Gazell: Received packets in Host/PRX mode with CRC error can no longer return ACK to device. + - NRFFOSDK-2470: app_timer - Fixed issue where starting and stopping the timer repeatedly caused errors in the module + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firmware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + - NRFFOSDK-2824: Device manager (pstorage) doesn't support update of bond split across two pages. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.10.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAG0 + - nRF51822 QFAAGC + - nRF51822 QFAAFA + - nRF51422 QFAAE0 + + For others devices, use SDK 4.x.x + +Supported SoftDevices: + + - S110 6.0.0 + - S120 1.0.0-1.alpha + - S210 3.0.0 + - S310 1.0.0 + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + - PCA10003 v3.0.0 + + +Changes: + + - app_button module: Detect both push and release, instead of just push + - Persistent storage (pstorage) module: + - Support for writing to used memory regions with the new update API. + - Support for clearing single blocks. + - Added get_status API to identify pending flash operations. + + ANT + - None + + ANT + BLE (Dual stack) + - Support for s310 SoftDevice added. + - Heart rate monitor example project support added. + - Added Device Firmware Update (DFU) example for s310. + BLE + - New experimental device manager module for managing bonds on s120. + - Beacon example added. It is available at nrf51822\Board\nrf6310\s110\ble_app_beacon + and nrf51822\Board\pca10001\s110\ble_app_beacon. + - Multiple GATT clients: The Database Discovery module available in + nrf51822\Board\nrf6310\s120\experimental\common folder can now be used to + discover two GATT services at the peer. + - Serialized s110 advertisement example has been removed. + - HID Keyboard application modified to send upper case letters on pressing Button 2. + + Proprietary + - None + +Fixed issues: + + ANT + - None + + ANT + BLE (Dual stack) + - None + + BLE + - NRFFOSDK-1897: Glucose: Fixed bug where authentication was not initiated when connecting to already bonded master. + - NRFFOSDK-2318: Glucose Feature values had incorrect values for 'General Device Fault Supported', 'Time fault Supported', and 'Multiple Bond Supported'. This has been fixed. + - ANCS: The advertising interval of the Apple Notification Center Client example application is reduced to 25 ms. Previously it was 250 ms which made it hard to discover from the peer device. + - NRFFOSDK-2357: Blood Pressure application changed to check if indication is enabled before attempting to send an indication to the peer + - NRFFOSDK-2336: HID Keyboard application fixed to send the correct Input Report bytes when in Boot Mode. + - Fixed issue in bond manager related to clearing of whitelist on deleting all bonds. + - NRFFOSDK-2162: New pstorage get_status API used to allow for flash access to be completed before system off. + + Proprietary + - NRFFOETT-644 - Gazell / ESB: Fixed some documentation issues. + +Known issues: + + - NRFFOSDK-2542 - SoftDevice related documentation for S110, S120 and S310 BLE stack is not consistent. When looking up SoftDevice application interface or message sequence charts, it is possible that one is looking at incorrect interface. Recommendation hence is to look at SoftDevice headers to ensure correct appplication interface. This is also applicable for Serialization library references. This will be fixed in next release. + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + ANT + BLE (Dual stack) + - S310 Heart Rate Relay Example: Bonding does not always function as expected. If bonding is enabled using compiler flag it is recommended to perform service discovery before bonding to minimize chances of unexpected behavior. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - S120 Examples: Flash clear operation may fail when connected. Impact of this in the S120 examples is that if peer loses the bond and a re-bonding occurs, flash clear fails, and DM_EVT_DEVICE_CONTEXT_STORED event is notified with a failure. + - Device manager is an experimental module and has a few APIs unimplemented. Also documentation providing examples of how API can be used is missing. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 5.0.5.x + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: Embedded Workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAGC (For others, use SDK 4.x.x) + - nRF51822 QFAAFA (For others, use SDK 4.x.x) + - nRF51422 QFAADA (For others, use SDK 4.x.x) + +Supported SoftDevices: + + - S110 6.0.0 + - S120 0.8.0-2.alpha + - S210 3.0.0-3.beta + - S310 1.0.0-2.alpha + + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 and 2.2.0 + + +Changes: + + - Moved and renamed SoftDevice header folders: + from nrf51822/Include/ble/softdevice to nrf51822/Include/s110 + from nrf51422/Include/ble/softdevice to nrf51422/Include/s210 + - Added SoftDevice headers for s120 and s310 at: + nrf51822/Include/s120 + nrf51422/Include/s310 + - Moved ANT examples from nrf51422/Board//ant to nrf51422/Board//s210 + - Moved s110 SoftDevice examples from nrf51822/Board//ble to nrf51822/Board//s110 + - Added folder for s310 examples in nrf51422/Board//s310 + - Added folder for s120 SoftDevice examples in nrf51822/Board//s120 + + ANT + - The flash layout settings of all ANT examples have been adapted to suit the new flash layout of S210 SoftDevice. + + + BLE + - Added experimental Multilink (up to 8) Central example which uses s120 SoftDevice. + - Added experimental Heart Rate collector example which uses s120 SoftDevice. + - Added prototype iBeacon example. + + Proprietary + +Fixed issues: + + - NRFFOETT-671: Added support for creating new nRF51 projects in Keil 5. + + ANT + - NRFFOETT-438: The API documentation of S210 SoftDevice is now correctly structured in the SDK documentation. + BLE + + Proprietary + +Known issues: + + - When flashing from Keil 4, a pop-up might appear stating "Cannot Load Flash Device Description !". + Solution: + - Write new flash algorithm settings to the uvopt file. + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Utilities". + Press "Settings" button to see flashing algorithms. + Verify that "nRF51xxx" is in the list of flashing algorithms, if not add it by pressing the "Add" button. + Exit and save settings by pressing "OK". This is also important to do if you did find the "nRF51xxx" in the list of flashing algorithms. + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 5.0.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.1.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +Tested with devices: + + - nRF51822 QFAAGC (For others, use SDK 4.x.x) + - nRF51822 QFAAFA (For others, use SDK 4.x.x) + - nRF51422 QFAADA (For others, use SDK 4.x.x) + +Supported SoftDevices: + + - S110 6.0.0-3 Beta + - Expected to be Compatible with SoftDevice S110 V6.0.0 production version + +Supported boards: + + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.1.0 and 2.2.0 + - PCA10001 v2.1.0 and 2.2.0 + - PCA10004 v2.1.0 + - PCA10005 v2.1.0 + + NOTE: The ANT examples in this release will only work on nRF51422 QFAADA engineering samples. + Currently no official boards/kits exist that work with these examples. + + +Changes: + + - Added pstorage module for handling asynchronous non-volatile memory (flash) access via SoftDevice API + - Existing BLE event handler has been extended into the new SoftDevice handler module. The new SoftDevice handler module allows for fetching SoC, BLE and ANT events + - Restructured documentation + + + ANT + + BLE + - Changes for support of S110 V6.0.0-3 Beta + - Added Apple Notification Center in experimental + + Proprietary + - SPI slave driver and example code added + - Include new ESB library which uses the same peripherals as the S110 SoftDevice + +Fixed issues: + + ANT + + BLE + + Proprietary + +Known issues: + + - Creating a blank project with Keil V5.0 it is not possible to choose the nRF51 series. + Solution: + Start new projects by making a copy of any existing keil project from the SDK + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-2162 - Heart Rate application for PCA10001 possible inconsistent system attributes on power cycle. It is possible that the system attributes on power cycle are not consistent with the ones updated during previous connection. + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.2 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.72.1.0 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - N51822 QFAACA on PCA10004 module on nRF6310 motherboard + - N51822 QFAAFA on PCA10005 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - Windows 8.0/8.1 + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1. + +- Supported boards in nRF51 SDK v. 4.4.2: + - PCA10000 v1.0 (Only for use with Master Emulator) + - PCA10000 v2.0.0 + - PCA10001 v1.0 through v2.1.0 + - PCA10003 v1.0 through v2.0.0 + - PCA10004 v1.0 through v2.0.0 + - PCA10005 v1.0 through v2.1.0 + - PCA10006 v1.0 through v2.0.0 + - PCA10007 v1.0 through v2.0.0 + - PCA10014 v1.0 + - PCA10018 v1.0.0 through v1.1.0 + +Changes: + + ANT + None + + BLE + - Removed ble_dfu_send_hex.exe from device_firmware_update experimental folder. Similar feature is now available in latest Master Control Panel application. + + Proprietary + None + +Fixed issues: + + - NRFFOSDK-1750 - Added PAN-11 workaround in PPI, PWM, and Simple PWM motor control examples. + - NRFFOSDK-1633 - Added PAN-56 workaround in TWI master driver. + + ANT + None + + BLE + - NRFFOSDK-1025 - The field max_len in rep_char_add signature in ble_hids.c has been corrected to uint16_t. + - NRFFOSDK-1921 - In case IRK is distrubuted by a peer using public address whitelist is updated for both IRK and address. + - NRFFOSDK-1899 - System attributes re-initialized on rebonding. + - NRFFOSDK-1900 - Removed false detection of DIV collisions. + - NRFFOSDK-1993 - Increased buffer in hci_mem_pool_internal.h fix the serialization examples. + Proprietary + None + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.1 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.71.2 + - GCC: gcc-arm-embedded 4.7 2013q1 + - IAR: embedded workbench for ARM 6.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8.1 Preview. + +Changes: + + - DFU documentation improved. + + ANT + None + + BLE + - NRFFOSDK-1759: Example IAR application for Heart Rate Service added. + - NRFFOSDK-1271: Speed and Cadence Control Point added to Cycling Speed and Cadence Service. + + Proprietary + - ESB: Improved tolerance to delayed interrupts. + + +Fixed issues: + + - NRFFOSDK-1592: Risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution, is now fixed. + + ANT + None + + BLE + - NRFFOETT-399: An IRK is added to the bond manager's whitelist only if the address type of the master is 'resolvable'. + - NRFFOETT-552: DTM application is now implementing PCN_083 + - NRFFOSDK-1828: Key refresh was triggering a link failure when re-bonding to a master. This is now fixed. + - NRFFOETT-571: Premature disconnection scenario handling added to bond manager. Previously this was resulting in system attributes of a master to be cleared. + + Proprietary + - ESB: The nrf_esb_tx_failed() callback function was never called when dynamic acknowledgement was used. This is now fixed. + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.4.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.71.2 + - GCC: gcc-arm-embedded 4.7 2013q1 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.1 + - The BLE example applications for HID Keyboard and HID Mouse have been tested with HID host running on Windows 8. + +Changes: + + - Device Firmware Update example released as part of the main SDK. + - Added support for image transfer over BLE. + - HCI Transport Layer used for serial transfer. + - Note: This example is implemented to work on nRF6310 motherboard because it uses Button 7 to enter bootloader mode on reset. + This is because Button 0 and Button 1 are used by other SDK applications as wakeup buttons. + If this example is to be changed to work for evaluation kit board, then this should be taken into consideration. + - PC application examples for performing firmware updates using HCI and BLE added in nrf6310\device_firmware_updates\experimental folder. + + - UICR Configuration example added to the SDK. It can be found in nrf6310\uicr_config_example folder. + + ANT + None + + BLE + - NRFFOETT-507: ble_app_dtm missing bytes on UART fixed. + - NRFFOSDK-73 : HID keyboard application will now send one key press per notification. + + + Proprietary + None + +Fixed issues: + + ANT + None + + BLE + - NRFFOSDK-1432: Buffer overflow issue in ble_bondmngr_sys_attr_store() function fixed. + - NRFFOETT-339: CCCD values (System Atributes) are now restored on reconnection to a known master only after the link is encrypted. + + Proprietary + None + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + - NRFFOSDK-1774: During SDK installation, chosing custom install location for SDK examples will create Start Menu shortcuts that point to Keil installation location. + - NRFFOSDK-1592: There is a risk of losing timer interrupts when the resolution of the timer is very high, e.g. 1 ms resolution. + - The DFU over BLE example has been tested to work with a minimum connection interval of 11.25 ms. + This application will not be able to handle connection intervals lower than 11.25 ms and may undergo a system reset in the middle of a firware update. + Workaround: If you face unexpected disconnects during firmware update process, consider increasing the connection interval used by the master. + + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - NRFFOSDK-1769: Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.3.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - GCC: gcc-arm-embedded 4.7 2013q1 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.2.0 + +Changes: + + - Supported GCC toolchain switched from CodeSourcery to gcc-arm-embedded. + - New gcc startup file, linker scripts, and makefiles. + - Updated CMSIS header files in Include/gcc to the latest revision (3.20). + - Makefile target "all" now runs "clean" and "debug" targets instead of incremental "release" target. + - nrf.h requires projects to have a define for a chip to enable some needed workarounds. + - SDK examples now support PCA10000 v2.0.0. To make the examples work on the older PCA10000 v1.0, the UART pins need to be remapped in the pca10000.h header file. + For v1.0 + #define RX_PIN_NUMBER 3 + #define TX_PIN_NUMBER 1 + #define CTS_PIN_NUMBER 2 + #define RTS_PIN_NUMBER 0 + For v2.0.0 + #define RX_PIN_NUMBER 11 + #define TX_PIN_NUMBER 9 + #define CTS_PIN_NUMBER 10 + #define RTS_PIN_NUMBER 8 + + ANT + - ANT examples have been updated to support the newest UART API. + BLE + - HCI Transport Layer from Bluetooth Specification v4.0 introduced for BLE S110 Serialized Applications. + - BLE S110 Serialization Examples released as part of the main SDK. + - Updated serialized ble_app_advertising and ble_app_hrs to use app_scheduler. + - Connection Parameter update module : Added possibility to request different connection parameters multiple times. A new event, BLE_CONN_PARAMS_EVT_SUCCEEDED has been created. Event handler implementation needs to take this into account, especially if they were implemented to trigger a disconnect regardless of the type of event. + - Added Makefile and Eclipse project file for ble_app_hrs. + - Changed hard coded flash pages to be FICR CODESIZE dependent. + + Proprietary + - Gazell: + - Added Gazell Pairing Host source code and board example. Backwards compatible with nRF24L Gazell Pairing Device and Host modules. + - Added function nrf_gzll_set_auto_disable(uint32_t num_ticks), to disable Gazell after a number of timeslots. + - Added function nrf_gzll_get_tick_count(). + - Gazell Pairing Device now uses nrf_gzll_get_tick_count() in order to implement a delay. This reduces current consumption. + - Default sync_lifetime value has been increased to 3*channel_table_size*number_of_timeslots_per_channel. This improves performance in high-interference environments. Current users who are satisfied with the performance may wish to maintain the minimum value of 1*channel_table_size*number_of_timeslots_per_channel, in order to avoid any slight increase in current consumption. + - Enhanced ShockBurst: + - ESB PTX now calls nrf_esb_tx_success() callback instead of nrf_esb_tx_failed() for NOACK packets. + - Fix in nrf_esb_set_mode() + - Information concerning backwards compatibility with nRF24L devices has been moved to the User Guide. + +Fixed issues: + + - Examples doing flash writes were not waiting for writes to finish. + + ANT + - NRFFOSDK-1312 - Changed ANTFS_TRANSMIT_POWER define in antfs.h from 0 to 3. The define previously had an incorrect definition which set the power value to -20dBm instead of 0dBm even though the comment indicated 0dBm. + + BLE + - NRFFOETT-402 - DFU Bootloader application in experimental project now sets stack pointer correctly before executing reset vector of application. + + Proprietary + - NRFFOETT-301 - Radio example uses obsolete RADIO_TXPOWER_TXPOWER_Neg40dBm definition. + - Fixed issue in TWI HW driver. Event was not cleared before waiting it to get cleared. + - Floating point ABI used by Makefiles was incorrect. Now using mabi-float=soft. + - Gazell/ESB: Fixed set_mode() functionality. + - Gazell GCC board examples startup and run correctly with the GCC libraries. + - A Gazell Device nows stop the RSSI measurement when no ACK is received, improving the base current consumption. + +Known issues: + + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYSTEM_OFF before flashing a new application. + + ANT + - NRFFOETT-438 - Documentation on S210 SoftDevice API wrongly structured. All SoftDevice functions appear as SVCALL in the Doxygen page. + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOETT-399 - The bond manager will use distrubted IRK in its whitelist regardless of the type of central's address and should actually use the irk if distributed and if the central's address is not public, and not random_static and not random_private_non_resovable. + - NRFFOSDK-1432 - A buffer overflow has been discovered in the BLE bond manager upon system attributes store. Workaround, define BLE_BONDMNGR_MAX_BONDED_MASTERS in ble_bondmngr_cfg.h to be 1 higher than the number of bond required by the applicaiton. + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - Not all examples have makefiles, nor have they been tested with the new toolchain. Expect minor compilation issues. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.1.0 + +Changes: + + ANT + + BLE + - NRFFOSDK-623 - BLE S110 DFU Bootloader prototype added to experimental folder. + - NRFFOSDK-996 - Delete of individual bonds in Bond Manager. API extension. + Validity check of stored bond added to Bond Manager API. + - NRFFOSDK-745 - Extended BLE S110 Serialized API. + Added serialized Heartrate example to exprimental folder. + + Proprietary + +Fixed issues: + + - NRFFOSDK-1015 - nRFgo Display lock up after a reset + + ANT + + BLE + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed. + + Proprietary + +Known issues: + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.1.0 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10003 evaluation kit board + - N51822 QFAACA on PCA10004/5 module on nRF6310 motherboard + - Windows XP SP3 32 bit + - Windows 7 SP1 64 bit + - BLE SoftDevice Version : s110_nrf51822_5.0.0 + +Changes: + - nRF51 device variant removed from KEIL device database and replaced with nRF51 series specific devices. + - Added nrf6310_experimental folder to the nRF51 SDK which contains examples and modules under development. + - Experimental version of the SoftDevice S110 serialization API with examples. + - Removed obsolete Master Emulator firmware from the release (nrf51822\Board\pca10000\ble\master_emulator\MEFW_nRF51822_firmware.hex). + - Renamed twi_sw_master_example to twi_master_example + ANT + + BLE + - Updated SoftDevice S110 specific documentation to include message sequence charts. + Proprietary + +Fixed issues: + - NRFFOETT-257 - twi_master_clear_bus() functionality fix done. + - NRFFOSDK-953 - twi_hw_master.c functionality fix done. + ANT + + BLE + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press both button 0 and button 1. + + Proprietary + +Known issues: + - If you have an existing KEIL project target set to use device variant "nRF51", a pop-up might appear stating that you have to "update your device selection". + Solution: + Press ALT+F7 to open "Options for Target" dialog. + Select "Options for Target" -> "Device". + Choose "Nordic nRF51 Series Devices" from the Database list. + Select the variant of the nRF51 chip that is used for the KEIL project target. + + + - When using J-Link software prior to version 4.66, a warning might appear when entering "Options for Target" -> "Debug" -> "Settings". The warning indicates that the device is unknown to the specific version of the J-Link software. + Solution: Upgrade J-Link software to version 4.66 or later. + + - Segger J-Link software has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines, J-Link CDC installer fails producing an error message saying it could not find JLinkCDCDriver_x86.msi. + Solution: Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled J-Link OB CDC driver installation dialog appears, the error message "Failed to install driver (Timeout occurred)" might appear . Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power. + - NRFFOSDK-363 - Flashing software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + Solution: Wake-up the current application from SYTEM_OFF before flashing a new application. + + ANT + - NRFFOSDK-366 - ANT-FS host: download sometimes fails when downloading a large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized. + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application. + (If the bonding information is not erased manually - by pressing button 1 during start-up - the new application might assert. ) + - NRFFOSDK-486 - All applications using the bond manager will assert when the maximum number of bonded masters is passed. See proximity application documentation. + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.0.1 +------------------ + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10006 module on nRF6310 motherboard + - N51822 QFAACA on PCA10001 evaluation kit board + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + - BLE SoftDevice Version : s110_nrf51822_4.0.0-2.beta + +Changes: + - Adressed poor search functionality in the documentation by upgrading used Doxygen version and adding a CHM version of the documentation. + Proprietary + - ESB/Gazell: A hard PLL rampdown is now implemented which shortens the TX to RX switching time to match nRF24L devices. + +Fixed issues: + - NRFFOSDK-801 - Project memory layout was incorrect for S110 4.0.0 targets. + - NRFFOETT-249 - gcc_nrf51_s110.ld had wrong SoftDevice size. + + ANT + + BLE + - NRFFOSDK-807 - Made changes to the default assert handler. + - NRFFOSDK-800 - Bug when switching between BLE and Gazell mode on buttons presses fixed. + - NRFFOETT-225 - DTM didn't work with Tescom TC3000C and R&S CBT. + - NRFFOETT-262 - Evaluation kit BLE examples had button pin pullup resistors disabled. + - NRFFOSDK-804 - Excluded ble_sps.c and ble_sps.h from release as they have not been fully implemented. + + Proprietary + - ESB/Gazell: The peripherals are no longer prepared for use by the nrf_esb_init() and nrf_gzll_init() functions. This is performed in the SystemInit() function. + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51 SDK installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + + ANT + - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. + - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application + + Proprietary: + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v. 4.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51422 QFAACA on PCA10006 module on nRF6310 motherboard + - N51822 QFAACA on PCA10001 evaluation kit board + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + +Changes: + - NRFFOSDK-192 - Interrupt driven low power UART module added. + - NRFFOSDK-543 - Set of common modules used by nRF51xxx examples added. + + ANT + - NRFFOSDK-312 - adapt to renaming of SoftDevice S210 V2.0.0 APIs + + BLE + - NRFFOSDK-55 - adapt to renaming of SoftDevice S110 V4.0.0 APIs + + +Fixed issues: + - NRFFOSDK-563 - nRF51 SDK installer - Keil CDB not installing correctly on PC's running Win7 w/Asian Locales (prim: Japanese/Chinese). + + ANT + - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec + + BLE + - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. API ble_bondmngr_sys_attr_store to save system attributes while in a connection is now available. + + + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - NRFFOETT-205 - The nRF51822 installer will not run if no C:\ drive exists + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + + ANT + - NRFFOSDK-366 - ANT-FS host: download some times fails when downloading large file. + - NRFFOSDK-755 - HRM TX buttons example may report wrong total elapsed time. + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed - See proximity application documentation. + - NRFFOSDK-758 - Button 1 does not wake up Bluetooth examples applications. To erase bonding information from system-off mode, press on both button 0 and button 1. + - NRFFOSDK-759 - Unable to switch to BLE mode from gazell mode in Multiprotocol application + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. + + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the + nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + + - Gazell does not support "Low Power Host mode" (Host mode 1). + +======================================================================== + +nRF51 SDK v3.0.0 +----------------- +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + +Changes: + + - Merged nRF514 and nRF518 SDKs + + - system_nrf51.c: GPIOTE peripheral turned on during system init. + + ANT + - Added ANT bicycle power-only sensor example + - Added ANT combined bicycle speed and cadence sensor example + + BLE + - Added Direct Test Mode (DTM) source code + - Added Glucose Meter service and example + - Added Health Thermometer service and example + - Added Blood Pressure service and example + - Added Proximity example for evaluation board + - Bond manager and flash module modified to write bonding information in flash while in a connection + +Fixed issues: + BLE + -NRFFOSDK-120 - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection + The bonding information are now written while in a connection but not the system attributes information. + + ANT + - Fixed incorrect event time generation in ANT HRM Tx example + - NRFFOSDK-469 - ANT - bicycle power rx: doxygen architecture picture defect + + - NRFFOSDK-470 - ANT - bicycle power tx: doxygen architecture picture defect + + Proprietary: + - twi_hw_master example : Fixed deadlock when stop condition was not issued. (NRFFOETT-167) + + - Bugfix: Polarity of on-air "no_ack" bit inverted to comply with legacy nRF24L01 + hardware ESB. + + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + + - NRFFOSDK-236 - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. + + - NRFFOSDK-362 - Reset button won't work after programming without cycling the target power + + - NRFFOSDK-363 - Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode + (implies to wake-up the current application from SYTEM_OFF before flashing a new application) + ANT + - ARCH-506 - ANT-FS host; download could fail when downloading large files. + + - NRFFOSDK-484 - HRM TX background pages are not following 65th packet rule according to spec + + BLE + - NRFFOSDK-119 - Only the "....\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\","....\sdk\nrf5822\Board\pca10001\ble\ble_app_proximity\ ", and "....\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ " applications are power optimized + + - NRFFOSDK-361 - System attributes are stored in flash only after disconnect. + + - NRFFOSDK-472 - Bonding information in flash are not erased during programming of a new application + If the bonding information are not erased manually - by pressing button 1 during start-up - the new application might assert. + + - NRFFOSDK-486 - All applications using bond manager will assert when the maximum number of bonded masters is passed + For more information, see proximity application documentation. + + + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. + + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + The legacy examples need to add the following in order to work with the + nRF51 examples: + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx devices. The timeslot periods and channel tables require adjustment. + + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + + - Gazell does not support "Low Power Host mode" (Host mode 1). + +Notification ANT: + - This is last release that will support N51422 QFAACA (ANT). Next release will contain API changes. + + + + + + +======================================================== +Old release notes from before SDK merge +======================================================== + + +nRF518 SDK v2.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: + - ARM: MDK-ARM Version 4.60 + - N51822 QFAACA on PCA10000 evaluation kit USB dongle + - N51822 QFAACA on PCA10001 evaluation kit board + - N51822 QFAACA on PCA10004 module on nRF6310 motherboard + - Windows XP SP3 32-bit + - Windows 7 SP1 64-bit + + Bluetooth: + - Bluetooth Low Energy SoftDevice S110_nRF51822_2.0.0_alpha1 + + Gazell / ESB libraries on-air compatible with the following SDKs for legacy nRF24Lxx devices: + - nRFgo SDK 2.3.0 + - nRFready Desktop 1.2.3 + +Changes: + + Bluetooth: + - Adapted examples for updated S110 API (S110_nRF51822_2.0.0_alpha1). + - Added Find Me (Immediate Alert Service as client) to Proximity Application. + - Added Alert Notification (client) service and example. + - Added Cycling Speed and Cadence service and example. + - Added Running Speed and Cadence service and example. + - Bond Manager modified to add Whitelist handling and CRC verification of flash. + - Bond Manager usage added to all examples except for power profiling application. + - Use of Whitelist added to Proximity, HID Mouse and HID Keyboard examples. + - Use of directed advertisement added to HID Mouse and HID Keyboard examples. + - Timer Module refactored. + + Proprietary: + - Added nRF24L series address conversion functions to radio_example. + - Added support for GCC to nRF51 Code Examples, ESB and Gazell examples. + - Examples no longer use deprecated PERPOWER register. + - Disabled "Download to flash" and "Verify Code Download" in JLink debug Download Options. + - All SDK release notes are now in this file. + - Added hardware flow control option to simple_uart. + - Fixed compilation problems with Keil ARM MDK v4.60 and ram retention, temperature and blinky examples. + - debouncer_example, ppi_example and timer_example now explicitly set timer bitmode. + - keil_arm_uv4.lnt include folder changed from C:\Keil\ARM\RV31\INC to C:\Keil\ARM\ARMCC\INC. + - Corrected location of SFR files in UV projects. + + - ESB: ESB PRX transceiver operations are shorted, removing continuous wave transmission and improving speed and current consumption. + - ESB: PRX starts listening immediately after sending an ACK, no longer waiting for the next timeslot. + - ESB: The NOACK bit is changed to an ACK bit to ensure compatibility with L01 radios. The L01 product specification is incorrect, only devices using dynamic ack will see this. + - ESB: esb_is_enabled function added. + - ESB: Disabling CRC checking on PRX/Host side works correctly + - ESB: Added support for controlling the XOSC outside the ESB library + + - Gazell: Added support for controlling the XOSC outside the Gazell library + - GZP: No longer deletes pairing data on gzp_init. Added functions to check if device has pairing data and delete all pairing info from flash. + - GZP: gzp_desktop_emulator example requires only one key press to pair and has been tested to work on SoftDevice. + - GZP: nrf_nvmc_write_bytes correctly iterates through bytes. + +Fixed issues: + - Examples use deprecated PERPOWER register. + + Proprietary: + - When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation. + - Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). + + Bluetooth: + - The buttons on the evaluation board are not debounced. + +Known issues: + - Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. + - On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. + - When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. (DRGN-1807) + - Reset button won't work after programing without cycling the target power. (DRGN-1885) + - Flashing a software using SEGGER is possible only when NOT in SYSTEM_OFF mode (implies to wake-up the current application with a button press for example before flashing a new application).(DRGN-1925) + + Bluetooth: + - Only the ..\sdk\nrf5822\Board\nrf6310\ble\ble_app_pwr_profiling\ and ..\sdk\nrf5822\Board\pca10001\ble\ble_app_hrs\ applications are power optimized.(DRGN-1914) + - ble_bondmngr_store_bonded_masters function from the bond manager cannot be used when advertising nor when in a connection (DRGN-1915) + (flash erase/write prevents the CPU from running which means the stack will not be able to run properly.) + If ble_bondmngr_store_bonded_masters function is called while advertising or in a connection, the behavior is UNDEFINED. + + Proprietary: + - ESB/Gazell: Calling nrf_esb_init() or nrf_gzll_init() will disable usage of the GPIOTE peripheral. In order to use the GPIOTE peripheral, the workaround in PAN 22 must be performed after calling these functions. + - Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. + - Temperature example does not give sane output values. This is hardware related issue described in PAN_028 and will be fixed in future silicon. + + - The nRF24Lxx ESB examples found in the legacy nRFready + SDKs do not work out of the box with the nRF51 ESB examples. This is due to: + - The legacy examples do not use "payload in ACK". + - The legacy examples use RF channel 2 (not 10 as the nRF51 examples). + - The examples do not use dynamic payload length. + + The legacy examples need to add the following in order to work with the + nRF51 examples: + + hal_nrf_setup_dynamic_payload(0xFF); + hal_nrf_enable_dynamic_payload(true); + hal_nrf_enable_ack_payload(true); + hal_nrf_set_rf_channel(10); + + In addition, the legacy PTX example must add code for handling the + payloads received in ACK. + + - The Gazell Link Layer examples are not fully "out of the box" compatible + with the legacy Gazell examples provided in the nRFgo SDK for nRF24Lxx + devices. The timeslot periods and channel tables require adjustment. + - Timeslot period: Edit gzll_params.h file used in the nRF24Lxx projects, + or use the nrf_gzll_set_timeslot_period() function in the nRF51 projects + (nRF51 Gazell timeslot period = 0.5*GZLL_RX_PERIOD). + - Channel table: Edit gzll_params.h file used in the nRF24Lxx projects, + or use the nrf_gzll_set_channel_table() function in the nRF51 projects. + - Gazell does not support "Low Power Host mode" (Host mode 1). + + + + + + + +nRF518 SDK v1.1.1 +----------------- + +Changes: +- Master Control Panel updated to version 3.1.1. Includes fix for issue where pca10000 master emulator devices did not get detected. + +Known issues: +- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. +- When using Keil ARM MDK v4.60 the ram retention, temperature and blinky examples might fail during compilation and leave an error message like this: + C3900U: Unrecognized option '--asm'. + C3900U: Unrecognized option '--interleave'. + To fix this Click Alt+F7, choose "Listing" tab. Uncheck "C Compiler Listing" +- Previous issues from v1.1.0 does still apply + + + + + + + +nRF518 SDK v1.1.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on PCA10004 module on nRF6310 motherboard +- N51822 QFAACA on PCA10000 USB dongle +- N51822 QFAACA on PCA10001 board +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } + +Bluetooth: + - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. + + + + + +nRF518 SDK v1.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on nRF2752 module on nRF6310 motherboard +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit +Bluetooth: + - S110 SoftDevice v1.0.0 + - J-Link ARM v4.52b or higher + +This release contains the following: +Bluetooth: + - Complete source code needed for writing applications on top of S110 SoftDevice (BLE Stack) + - Template application that can be used as a starting point to develop custom applications. + - Example application for Heart Rate Service + - Example application for Proximity profile + - Example application for HID Mouse + - Example application for HID Keyboard + - Power profiling application + - Example application using Heart Rate Service for Evaluation Board (PCA10001) + - Multiprotocol application that implements the Heart Rate profile in Bluetooth mode and the Gazell 'device' mode. + - Documentation + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- Gazell and ESB examples point to wrong SFR file (should be SFD\Nordic\nRF51\nRF51822.sfr). +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } +- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. +- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. + +Bluetooth: + - The button on the evaluation board are not debounced in hardware and the application implementing for it does not debounce the button presses either (using software mechanisms). So there will be additional increments/decrements of heart rate measurement while pressing the buttons. + + + + +nRF514 SDK v.1.2.0 +------------------ + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.60 +- N51422 QFAACA on PCA10004 module on nRF6310 motherboard +- N51422 QFAACA on PCA10006 module on nRF6310 motherboard +- N51822 QFAACA on nRF2752 module on nRF6310 motherboard +- N51822 QFAACA on PCA10001 evaluation kit board +- Windows XP SP3 32-bit +- Windows 7 SP1 64-bit + +Changes: +- Added Bicycle Power minimal slave example. +- Added Stride and Distance Monitor minimal slave and master example. +- Removed deprecated PERPOWER register from examples and header files. + +Known issues: +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- On some Windows XP machines JLink CDC installer fails with error message saying it could not find JLinkCDCDriver_x86.msi. + - Try running the installer C:\Program Files\SEGGER\JLinkARM_V\USBDriver\JLinkCDCInstaller_V1.2b.exe manually. +- When the bundled JLink OB CDC driver installation dialog appears, it might pop up an error saying "Failed to install driver (Timeout occurred)". Ignore it. +- Flashing a software using SEGGER is NOT possible when the device is in SYSTEM_OFF mode (implies to wake-up the current application from SYTEM_OFF before flashing a new application) +- Reset button won't work after programming with Keil without cycling the target power. On the other hand if nrfjprog with -p (pin reset) is used to program the device, reset button will work. +- Using -p option in nrfjprog too heavily might block JLink. This block can be resolved by re-cycling the JLink power. + + +nRF514 SDK v1.1.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51422 QFAACA on PCA10001 module +- N51422 QFAACA on a PCA10005 modulea on nRF6310 motherboard + +Known issues: +- When having an application which starts up by putting the chip in SystemOff mode, and wakeup source is not configured correctly, the device cannot be programmed. + Workaround: Use nrfjprog with "recover" option to wipe the application keeping the application in SystemOff mode. +- For PCA10003 examples using UART, the terminal program on the PC has to release the COM port when PCA10003 is power cycled. It is not possible for the PCA10003 to keep a connection up when performing a power cycle. + Workaround: Close terminal program for each time you want to perform a power recycle + +Changes: +- Added examples for PCA10003 Evaluation kit. +- Added nrfjprog.exe - Nordic Semiconductor command line nRF51 programming tool using JLink dll's. +- Added custom system_nrf51422.c in templates folder for handling reset after flashing and turning all peripherals on (except GPIOTE) as described in PAN028. +- Removed references to depricated PERPOWER register in ANT code examples. +- Added compiler flag to the ANT examples, to easier being able to run examples without any UART. +- Modified simple_uart_config() parameters. Added new parameters for flow control +- Added include/boards folder for handling examples targeted for different boards +- Fixed bug in timer_example +- Fixed bug in spi_example + + +nRF514 SDK v1.0.0 +----------------- + +Following toolchains/devices have been used for testing and verification: +- ARM: MDK-ARM Version 4.54 +- N51822 QFAACA on nRF2754 module on nRF6310 motherboard +- Tested on Windows 7 64-bit + +Known issues: +- Examples use depracated PERPOWER register. Future silicon will power up peripherals after reset and PERPOWER register will be removed. +- Using Keil versions 4.53 and older will not work unless you change configuration in jlinksettings.ini. See User Guide for more details. +- Temperature example does not give sane output values. This is hardware related issue described in +- Segger JLink has some issues with Keil. See http://www.segger.com/IDE_Integration_Keil.html#knownproblems for more details. +- Reset button wont work after programing without cycling the target power. Workaround is to update system_nrf51.c with + void SystemInit (void) + { + /* Switch ON both RAM banks */ + NRF_POWER->RESET = POWER_RESET_RESET_Enabled; + NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) | + (POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos); + } +- Spi master function spi_master_init() sends two dummy bytes. This will be removed in a future release. +- timer_example nrf_timer_delay_ms() will not give expected results using parameter values over 65 ms. + +Changes: +- First public release + diff --git a/HAL_Driver/sdk/external/fprintf/nrf_fprintf.c b/HAL_Driver/sdk/external/fprintf/nrf_fprintf.c new file mode 100644 index 0000000..e8a8e30 --- /dev/null +++ b/HAL_Driver/sdk/external/fprintf/nrf_fprintf.c @@ -0,0 +1,85 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_FPRINTF) +#include + +#include "nrf_assert.h" +#include "nrf_fprintf_format.h" + +void nrf_fprintf_buffer_flush(nrf_fprintf_ctx_t * const p_ctx) +{ + ASSERT(p_ctx != NULL); + + if (p_ctx->io_buffer_cnt == 0) + { + return; + } + + p_ctx->fwrite(p_ctx->p_user_ctx, + p_ctx->p_io_buffer, + p_ctx->io_buffer_cnt); + p_ctx->io_buffer_cnt = 0; +} + +void nrf_fprintf(nrf_fprintf_ctx_t * const p_ctx, + char const * p_fmt, + ...) +{ + ASSERT(p_ctx != NULL); + ASSERT(p_ctx->fwrite != NULL); + ASSERT(p_ctx->p_io_buffer != NULL); + ASSERT(p_ctx->io_buffer_size > 0); + + if (p_fmt == NULL) + { + return; + } + + va_list args = {0}; + va_start(args, p_fmt); + + nrf_fprintf_fmt(p_ctx, p_fmt, &args); + + va_end(args); +} + +#endif // NRF_MODULE_ENABLED(NRF_FPRINTF) + diff --git a/HAL_Driver/sdk/external/fprintf/nrf_fprintf.h b/HAL_Driver/sdk/external/fprintf/nrf_fprintf.h new file mode 100644 index 0000000..8c2c200 --- /dev/null +++ b/HAL_Driver/sdk/external/fprintf/nrf_fprintf.h @@ -0,0 +1,114 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_FPRINTF_H__ +#define NRF_FPRINTF_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (* nrf_fprintf_fwrite)(void const * p_user_ctx, char const * p_str, size_t length); + +/** + * @brief fprintf context + */ +typedef struct nrf_fprintf_ctx +{ + char * const p_io_buffer; ///< Pointer to IO buffer. + size_t const io_buffer_size; ///< IO buffer size. + size_t io_buffer_cnt; ///< IO buffer usage. + bool auto_flush; ///< Auto flush configurator. + + void const * const p_user_ctx; ///< Pointer to user data to be passed to the fwrite funciton. + + nrf_fprintf_fwrite fwrite; ///< Pointer to function sending data stream. +} nrf_fprintf_ctx_t; + + +/** + * @brief Macro for defining nrf_fprintf instance. + * + * @param name Instance name. + * @param _p_user_ctx Pointer to user data. + * @param _p_io_buffer Pointer to IO buffer + * @param _io_buffer_size Size of IO buffer. + * @param _auto_flush Indicator if IO buffer shall be automatically flush. + * @param _fwrite Pointer to function sending data stream. + * */ +#define NRF_FPRINTF_DEF(name, _p_user_ctx, _p_io_buffer, _io_buffer_size, _auto_flush, _fwrite) \ + static nrf_fprintf_ctx_t name = \ + { \ + .p_io_buffer = _p_io_buffer, \ + .io_buffer_size = _io_buffer_size, \ + .io_buffer_cnt = 0, \ + .auto_flush = _auto_flush, \ + .p_user_ctx = _p_user_ctx, \ + .fwrite = _fwrite \ + } + +/** + * @brief fprintf like function which send formated data stream to output specified by user + * @ref nrf_fprintf_ctx_t + * + * @param p_ctx fprintf context. + * @param p_fmt Format string. + * @param ... List of parameters to print. + * */ +void nrf_fprintf(nrf_fprintf_ctx_t * const p_ctx, + char const * p_fmt, + ...); + +/** + * @brief function flushing data stored in io_buffer @ref nrf_fprintf_ctx_t + * + * @param p_ctx fprintf context + */ +void nrf_fprintf_buffer_flush(nrf_fprintf_ctx_t * const p_ctx); + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_FPRINTF_H__ */ + diff --git a/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.c b/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.c new file mode 100644 index 0000000..76cf94a --- /dev/null +++ b/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.c @@ -0,0 +1,516 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.14d * +* * +*********************************************************************/ + +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(NRF_FPRINTF) + +#include + +#include "nrf_assert.h" +#include "nrf_fprintf.h" +#include "nrf_fprintf_format.h" + +#define NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) +#define NRF_CLI_FORMAT_FLAG_PAD_ZERO (1u << 1) +#define NRF_CLI_FORMAT_FLAG_PRINT_SIGN (1u << 2) + +static void buffer_add(nrf_fprintf_ctx_t * const p_ctx, char c) +{ +#if NRF_MODULE_ENABLED(NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF) + if (c == '\n') + { + buffer_add(p_ctx, '\r'); + } +#endif + p_ctx->p_io_buffer[p_ctx->io_buffer_cnt++] = c; + + if (p_ctx->io_buffer_cnt >= p_ctx->io_buffer_size) + { + nrf_fprintf_buffer_flush(p_ctx); + } +} + +static void string_print(nrf_fprintf_ctx_t * const p_ctx, + char const * p_str, + uint32_t FieldWidth, + uint32_t FormatFlags) +{ + uint32_t Width = 0; + char c; + + if ((FormatFlags & NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) == NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) + { + while ((c = *p_str) != '\0') + { + p_str++; + Width++; + buffer_add(p_ctx, c); + } + + while ((FieldWidth > Width) && (FieldWidth > 0)) + { + FieldWidth--; + buffer_add(p_ctx, ' '); + } + } + else + { + if (p_str != 0) + { + Width = strlen(p_str); + } + + while ((FieldWidth > Width) && (FieldWidth > 0)) + { + FieldWidth--; + buffer_add(p_ctx, ' '); + } + + while ((c = *p_str) != '\0') + { + p_str++; + Width++; + buffer_add(p_ctx, c); + } + } +} + +static void unsigned_print(nrf_fprintf_ctx_t * const p_ctx, + uint32_t v, + uint32_t Base, + uint32_t NumDigits, + uint32_t FieldWidth, + uint32_t FormatFlags) +{ + static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + 'A', 'B', 'C', 'D', 'E', 'F' }; + uint32_t Div; + uint32_t Value; + uint32_t Width; + char c; + + Value = v; + // + // Get actual field width + // + Width = 1u; + while (Value >= Base) + { + Value = (Value / Base); + Width++; + } + if (NumDigits > Width) + { + Width = NumDigits; + } + // + // Print leading chars if necessary + // + if ((FormatFlags & NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) == 0u) + { + if (FieldWidth != 0u) + { + if (((FormatFlags & NRF_CLI_FORMAT_FLAG_PAD_ZERO) == NRF_CLI_FORMAT_FLAG_PAD_ZERO) && + (NumDigits == 0u)) + { + c = '0'; + } + else + { + c = ' '; + } + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + buffer_add(p_ctx, c); + } + } + } + + Value = 1; + /* + * Compute Digit. + * Loop until Digit has the value of the highest digit required. + * Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + */ + while (1) + { + /* User specified a min number of digits to print? => Make sure we loop at least that + * often, before checking anything else (> 1 check avoids problems with NumDigits + * being signed / unsigned) + */ + if (NumDigits > 1u) + { + NumDigits--; + } + else + { + Div = v / Value; + // Is our divider big enough to extract the highest digit from value? => Done + if (Div < Base) + { + break; + } + } + Value *= Base; + } + // + // Output digits + // + do + { + Div = v / Value; + v -= Div * Value; + buffer_add(p_ctx, _aV2C[Div]); + Value /= Base; + } while (Value); + // + // Print trailing spaces if necessary + // + if ((FormatFlags & NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) == NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + buffer_add(p_ctx, ' '); + } + } + } +} + +static void int_print(nrf_fprintf_ctx_t * const p_ctx, + int32_t v, + uint32_t Base, + uint32_t NumDigits, + uint32_t FieldWidth, + uint32_t FormatFlags) +{ + uint32_t Width; + int32_t Number; + + Number = (v < 0) ? -v : v; + + // + // Get actual field width + // + Width = 1u; + while (Number >= (int32_t)Base) + { + Number = (Number / (int32_t)Base); + Width++; + } + if (NumDigits > Width) + { + Width = NumDigits; + } + if ((FieldWidth > 0u) && ((v < 0) || + ((FormatFlags & NRF_CLI_FORMAT_FLAG_PRINT_SIGN) == NRF_CLI_FORMAT_FLAG_PRINT_SIGN))) + { + FieldWidth--; + } + // + // Print leading spaces if necessary + // + if ((((FormatFlags & NRF_CLI_FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && + ((FormatFlags & NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + buffer_add(p_ctx, ' '); + } + } + } + // + // Print sign if necessary + // + if (v < 0) + { + v = -v; + buffer_add(p_ctx, '-'); + } + else if ((FormatFlags & NRF_CLI_FORMAT_FLAG_PRINT_SIGN) == NRF_CLI_FORMAT_FLAG_PRINT_SIGN) + { + buffer_add(p_ctx, '+'); + } + else + { + /* do nothing */ + } + // + // Print leading zeros if necessary + // + if (((FormatFlags & NRF_CLI_FORMAT_FLAG_PAD_ZERO) == NRF_CLI_FORMAT_FLAG_PAD_ZERO) && + ((FormatFlags & NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) + { + if (FieldWidth != 0u) + { + while ((FieldWidth != 0u) && (Width < FieldWidth)) + { + FieldWidth--; + buffer_add(p_ctx, '0'); + } + } + } + // + // Print number without sign + // + unsigned_print(p_ctx, (uint32_t)v, Base, NumDigits, FieldWidth, FormatFlags); +} + +void nrf_fprintf_fmt(nrf_fprintf_ctx_t * const p_ctx, + char const * p_fmt, + va_list * p_args) +{ + ASSERT(p_ctx != NULL); + + ASSERT(p_ctx->fwrite != NULL); + ASSERT(p_ctx->p_io_buffer != NULL); + ASSERT(p_ctx->io_buffer_size > 0); + + if (p_fmt == NULL) + { + return; + } + + char c; + int32_t v; + uint32_t NumDigits; + uint32_t FormatFlags; + uint32_t FieldWidth; + + do + { + c = *p_fmt; + p_fmt++; + + if (c == 0u) + { + break; + } + if (c == '%') + { + // + // Filter out flags + // + FormatFlags = 0u; + v = 1; + + do + { + c = *p_fmt; + switch (c) + { + case '-': + FormatFlags |= NRF_CLI_FORMAT_FLAG_LEFT_JUSTIFY; + p_fmt++; + break; + case '0': + FormatFlags |= NRF_CLI_FORMAT_FLAG_PAD_ZERO; + p_fmt++; + break; + case '+': + FormatFlags |= NRF_CLI_FORMAT_FLAG_PRINT_SIGN; + p_fmt++; + break; + default: + v = 0; + break; + } + } while (v); + + // + // filter out field width + // + FieldWidth = 0u; + do + { + if (c == '*') + { + /*lint -save -e64 -e56*/ + FieldWidth += va_arg(*p_args, unsigned); + /*lint -restore*/ + p_fmt++; + break; + } + c = *p_fmt; + if ((c < '0') || (c > '9')) + { + break; + } + p_fmt++; + FieldWidth = (FieldWidth * 10u) + (c - '0'); + } while (1); + + // + // Filter out precision (number of digits to display) + // + NumDigits = 0u; + c = *p_fmt; + if (c == '.') + { + p_fmt++; + do + { + c = *p_fmt; + if ((c < '0') || (c > '9')) + { + break; + } + p_fmt++; + NumDigits = NumDigits * 10u + (c - '0'); + } while (1); + } + // + // Filter out length modifier + // + c = *p_fmt; + do + { + if ((c == 'l') || (c == 'h')) + { + p_fmt++; + c = *p_fmt; + } + else + { + break; + } + } while (1); + // + // Handle specifiers + // + /*lint -save -e64*/ + switch (c) + { + case 'c': + { + char c0; + v = va_arg(*p_args, int32_t); + c0 = (char)v; + buffer_add(p_ctx, c0); + break; + } + case 'd': + case 'i': + v = va_arg(*p_args, int32_t); + int_print(p_ctx, + v, + 10u, + NumDigits, + FieldWidth, + FormatFlags); + break; + case 'u': + v = va_arg(*p_args, int32_t); + unsigned_print(p_ctx, + (uint32_t)v, + 10u, + NumDigits, + FieldWidth, + FormatFlags); + break; + case 'x': + case 'X': + v = va_arg(*p_args, int32_t); + unsigned_print(p_ctx, + (uint32_t)v, + 16u, + NumDigits, + FieldWidth, + FormatFlags); + break; + case 's': + { + char const * p_s = va_arg(*p_args, const char *); + string_print(p_ctx, p_s, FieldWidth, FormatFlags); + break; + } + case 'p': + v = va_arg(*p_args, int32_t); + buffer_add(p_ctx, '0'); + buffer_add(p_ctx, 'x'); + unsigned_print(p_ctx, (uint32_t)v, 16u, 8u, 8u, 0); + break; + case '%': + buffer_add(p_ctx, '%'); + break; + default: + break; + } + /*lint -restore*/ + p_fmt++; + } + else + { + buffer_add(p_ctx, c); + } + } while (*p_fmt != '\0'); + + if (p_ctx->auto_flush) + { + nrf_fprintf_buffer_flush(p_ctx); + } +} + +#endif // NRF_MODULE_ENABLED(NRF_FPRINTF) + diff --git a/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.h b/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.h new file mode 100644 index 0000000..1fae503 --- /dev/null +++ b/HAL_Driver/sdk/external/fprintf/nrf_fprintf_format.h @@ -0,0 +1,86 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.14d * +* * +*********************************************************************/ + +#ifndef NRF_FPRINTF_FORMAT_H__ +#define NRF_FPRINTF_FORMAT_H__ + +#include +#include "nrf_fprintf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Printf like function which sends formated data stream to output. + * + * @param nrf_fprintf_ctx_t Print context. + * @param p_fmt Format string. + * @param p_args List of parameters to print. + * */ +void nrf_fprintf_fmt(nrf_fprintf_ctx_t * const p_ctx, + char const * p_fmt, + va_list * p_args); + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_FPRINTF_FORMAT_H__ */ + diff --git a/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.c b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.c new file mode 100644 index 0000000..ad0ebb4 --- /dev/null +++ b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.c @@ -0,0 +1,1744 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.18a * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 6852 $ + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + + Effective buffer size: SizeOfBuffer - 1 + + WrOff == RdOff: Buffer is empty + WrOff == (RdOff - 1): Buffer is full + WrOff > RdOff: Free space includes wrap-around + WrOff < RdOff: Used space includes wrap-around + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + Buffer full and wrap-around after next byte + + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_BUFFER_SECTION + #if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION + #endif +#endif + +#ifndef SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGNMENT 0 +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 +#endif + +#ifndef SEGGER_RTT_MEMCPY + #ifdef MEMCPY + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) + #else + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) + #endif +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#if (defined __ICCARM__) || (defined __ICCRX__) + #define RTT_PRAGMA(P) _Pragma(#P) +#endif + +#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT + #if (defined __GNUC__) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #elif (defined __ICCARM__) || (defined __ICCRX__) + #define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #else + #error "Alignment not supported for this compiler." + #endif +#else + #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#endif + +#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) + #if (defined __GNUC__) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var + #elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var + #else + #error "Section placement not supported for this compiler." + #endif +#else + #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#endif + + +#if SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#else + #define SEGGER_RTT_CB_ALIGN(Var) Var +#endif + +#if SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#else + #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#endif + + +#if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#else + #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#endif + +#if defined(SEGGER_RTT_BUFFER_SECTION) + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#else + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ +// +// RTT Control Block and allocate buffers for channel 0 +// +SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); + +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); +SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); + +static char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* May only be called via INIT() to avoid overriding settings. +* +*/ +#define INIT() do { \ + if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); } \ + } while (0) +static void _DoInit(void) { + SEGGER_RTT_CB* p; + // + // Initialize control block + // + p = &_SEGGER_RTT; + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = sizeof(_acUpBuffer); + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = sizeof(_acDownBuffer); + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string in three steps to make sure "SEGGER RTT" is not found + // in initializer memory (usually flash) by J-Link + // + strcpy(&p->acID[7], "RTT"); + strcpy(&p->acID[0], "SEGGER"); + p->acID[6] = ' '; +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + NumBytesWritten += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + while (NumBytesToWrite--) { + *pDst++ = *pBuffer++; + }; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; +#endif + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + pRing->WrOff = WrOff; + } while (NumBytes); + // + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + } else { + // + // We reach the end of the buffer, so need to wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + NumBytesAtOnce = Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + pDst = pRing->pBuffer; + NumBytesAtOnce = NumBytes - Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + pRing->WrOff = NumBytes - Rem; +#else + NumBytesAtOnce = Rem; + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + SEGGER_RTT_MEMCPY(pRing->pBuffer, pData + Rem, NumBytesAtOnce); + pRing->WrOff = NumBytesAtOnce; +#endif + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + const char* pSrc; +#endif + // + INIT(); + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pSrc = pRing->pBuffer + RdOff; + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + // + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteWithOverwriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block. +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* and overwrites data if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, data is overwritten. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* connection reads RTT data. +*/ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) { + Avail = pRing->SizeOfBuffer - 1u; + } else if ( pRing->WrOff < pRing->RdOff) { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } else { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; + } + if (NumBytes > Avail) { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do { + if (Avail > NumBytes) { + // + // Last round + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + pRing->WrOff; + Avail = NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + pRing->WrOff += Avail; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, NumBytes); + pRing->WrOff += NumBytes; +#endif + break; + } else { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + pRing->WrOff; + NumBytes -= Avail; + while (Avail--) { + *pDst++ = *pData++; + }; + pRing->WrOff = 0; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, Avail); + pData += Avail; + pRing->WrOff = 0; + NumBytes -= Avail; +#endif + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + char* pDst; +#endif + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + // + // Handle the most common cases fastest. + // Which is: + // RdOff <= WrOff -> Space until wrap around is free. + // AND + // WrOff + NumBytes < SizeOfBuffer -> No Wrap around necessary. + // + // OR + // + // RdOff > WrOff -> Space until RdOff - 1 is free. + // AND + // WrOff + NumBytes < RdOff -> Data fits into buffer + // + if (RdOff <= WrOff) { + // + // Get space until WrOff will be at wrap around. + // + Avail = pRing->SizeOfBuffer - 1u - WrOff ; + if (Avail >= NumBytes) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + return 1; + } + // + // If data did not fit into space until wrap around calculate complete space in buffer. + // + Avail += RdOff; + // + // If there is still no space for the whole of this output, don't bother. + // + if (Avail >= NumBytes) { + // + // OK, we have enough space in buffer. Copy in one or 2 chunks + // + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + if (Rem > NumBytes) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + } else { + // + // We reach the end of the buffer, so need to wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + NumBytes -= Rem; + WrOff = NumBytes; + do { + *pDst++ = *pData++; + } while (--Rem); + pDst = pRing->pBuffer; + do { + *pDst++ = *pData++; + } while (--NumBytes); + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, Rem); + SEGGER_RTT_MEMCPY(pRing->pBuffer, pData + Rem, NumBytes - Rem); + pRing->WrOff = NumBytes - Rem; +#endif + } + return 1; + } + } else { + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + return 1; + } + } + // + // If we reach this point no data has been written + // + return 0; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Call the non-locking write function + // + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkipNoLock +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* SEGGER_RTT_PutCharSkipNoLock does not lock the application and +* skips the byte, if it does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ + +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkip +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +*/ + +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + + /********************************************************************* +* +* SEGGER_RTT_PutChar +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ + +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Wait for free space if mode is set to blocking + // + if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + while (WrOff == pRing->RdOff) { + ; + } + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pRing->pBuffer[pRing->WrOff] = c; + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + unsigned RdOff; + int r; + + INIT(); + RdOff = _SEGGER_RTT.aDown[0].RdOff; + if (RdOff != _SEGGER_RTT.aDown[0].WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + + INIT(); + SEGGER_RTT_LOCK(); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. +* < 0 - Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 O.K. +* < 0 Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + if (BufferIndex > 0u) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = (char*)pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsUpBuffer +* +* Function description +* Run-time configuration of specific up-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsDownBuffer +* +* Function description +* Run-time configuration of specific Down-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* Flags Flags to set for the buffer. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(); + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + _DoInit(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +*/ +int SEGGER_RTT_SetTerminal (char TerminalId) { + char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + int r; + // + INIT(); + // + r = 0; + ac[0] = 0xFFU; + if ((unsigned char)TerminalId < (unsigned char)sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[(unsigned char)TerminalId]; + pRing = &_SEGGER_RTT.aUp[0]; // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[0]; + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = STRLEN(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } else { + Status = -1; + } + return Status; +} + + +/*************************** End of file ****************************/ diff --git a/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.h b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.h new file mode 100644 index 0000000..a8d9a7f --- /dev/null +++ b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT.h @@ -0,0 +1,251 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.18a * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +Revision: $Rev: 6849 $ +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +#ifdef __cplusplus + extern "C" { +#endif +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (char TerminalId); +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); +#ifdef __cplusplus + } +#endif + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0U) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1U) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2U) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3U) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "" // Reset to default colors +#define RTT_CTRL_CLEAR "" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "" +#define RTT_CTRL_TEXT_RED "" +#define RTT_CTRL_TEXT_GREEN "" +#define RTT_CTRL_TEXT_YELLOW "" +#define RTT_CTRL_TEXT_BLUE "" +#define RTT_CTRL_TEXT_MAGENTA "" +#define RTT_CTRL_TEXT_CYAN "" +#define RTT_CTRL_TEXT_WHITE "" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "" +#define RTT_CTRL_TEXT_BRIGHT_RED "" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "" + +#define RTT_CTRL_BG_BLACK "" +#define RTT_CTRL_BG_RED "" +#define RTT_CTRL_BG_GREEN "" +#define RTT_CTRL_BG_YELLOW "" +#define RTT_CTRL_BG_BLUE "" +#define RTT_CTRL_BG_MAGENTA "" +#define RTT_CTRL_BG_CYAN "" +#define RTT_CTRL_BG_WHITE "" + +#define RTT_CTRL_BG_BRIGHT_BLACK "" +#define RTT_CTRL_BG_BRIGHT_RED "" +#define RTT_CTRL_BG_BRIGHT_GREEN "" +#define RTT_CTRL_BG_BRIGHT_YELLOW "" +#define RTT_CTRL_BG_BRIGHT_BLUE "" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "" +#define RTT_CTRL_BG_BRIGHT_CYAN "" +#define RTT_CTRL_BG_BRIGHT_WHITE "" + + +#endif + +/*************************** End of file ****************************/ diff --git a/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Conf.h b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..79caffe --- /dev/null +++ b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Conf.h @@ -0,0 +1,328 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.18a * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 7020 $ + +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#include "nordic_common.h" +#include "app_util_platform.h" +#include "sdk_config.h" + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS) // Max. number of down-buffers (H->T) available on this target (Default: 3) + +#define BUFFER_SIZE_UP (SEGGER_RTT_CONFIG_BUFFER_SIZE_UP) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#define BUFFER_SIZE_DOWN (SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) + +#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) + +#define USE_RTT_ASM (0) // Use assembler version of SEGGER_RTT.c when 1 + +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_CONFIG_DEFAULT_MODE // Mode for pre-initialized terminal channel (buffer 0) + + +#define SEGGER_RTT_LOCK() CRITICAL_REGION_ENTER() +#define SEGGER_RTT_UNLOCK() CRITICAL_REGION_EXIT() + +/********************************************************************* +* +* RTT memcpy configuration +* +* memcpy() is good for large amounts of data, +* but the overhead is big for small amounts, which are usually stored via RTT. +* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. +* +* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. +* This is may be required with memory access restrictions, +* such as on Cortex-A devices with MMU. +*/ +#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// + +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) + +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#ifndef SEGGER_RTT_LOCK +#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__) + #ifdef __ARM_ARCH_6M__ + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (LockState) \ + : \ + ); \ + } + + #elif defined(__ARM_ARCH_7A__) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (LockState) \ + : \ + : "r1" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (LockState) \ + : "r0", "r1" \ + ); \ + } +#else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ + } + #elif ((defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || (defined (__ARM7M__) && (__CORE__ == __ARM7M__))) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR RX +*/ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long LockState; \ + LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ + } +#endif + +/********************************************************************* +* +* RTT lock configuration for KEIL ARM +*/ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char PRIMASK __asm( "primask"); \ + LockState = PRIMASK; \ + PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + register unsigned char BASEPRI __asm( "basepri"); \ + LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for TI ARM +*/ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int LockState; \ + LockState = OS_GetBASEPRI(); \ + OS_SetBASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() OS_SetBASEPRI(LockState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif // #ifndef SEGGER_RTT_LOCK +#endif +/*************************** End of file ****************************/ diff --git a/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Syscalls_GCC.c b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Syscalls_GCC.c new file mode 100644 index 0000000..3a89001 --- /dev/null +++ b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_Syscalls_GCC.c @@ -0,0 +1,139 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.18a * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_Syscalls_GCC.c +Purpose : Low-level functions for using printf() via RTT in GCC. + To use RTT for printf output, include this file in your + application. +Revision: $Rev: 4351 $ +---------------------------------------------------------------------- +*/ +#include "sdk_config.h" +#if !defined(RETARGET_ENABLED) || RETARGET_ENABLED == 0 +#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 +#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) + +#include // required for _write_r +#include "SEGGER_RTT.h" + + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ +// +// If necessary define the _reent struct +// to match the one passed by the used standard library. +// +struct _reent; + +/********************************************************************* +* +* Function prototypes +* +********************************************************************** +*/ +int _write(int file, char *ptr, int len); +_ssize_t _write_r _PARAMS ((struct _reent *, int, const void *, size_t)); + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _write() +* +* Function description +* Low-level write function. +* libc subroutines will use this system routine for output to all files, +* including stdout. +* Write data via RTT. +*/ +int _write(int file, char *ptr, int len) { + (void) file; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; +} + +/********************************************************************* +* +* _write_r() +* +* Function description +* Low-level reentrant write function. +* libc subroutines will use this system routine for output to all files, +* including stdout. +* Write data via RTT. +*/ +_ssize_t _write_r _PARAMS((struct _reent *r, int file, const void *ptr, size_t len)) { + (void) file; /* Not used, avoid warning */ + (void) r; /* Not used, avoid warning */ + SEGGER_RTT_Write(0, ptr, len); + return len; +} + +#endif // #if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM) +#endif // defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1 +#endif // !defined(RETARGET_ENABLED) || RETARGET_ENABLED == 0 +/****** End Of File *************************************************/ diff --git a/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_printf.c b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_printf.c new file mode 100644 index 0000000..82d4269 --- /dev/null +++ b/HAL_Driver/sdk/external/segger_rtt/SEGGER_RTT_printf.c @@ -0,0 +1,515 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH & Co. KG * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2017 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the RTT protocol and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* o Redistributions in binary form must reproduce the above * +* copyright notice, this list of conditions and the following * +* disclaimer in the documentation and/or other materials provided * +* with the distribution. * +* * +* o Neither the name of SEGGER Microcontroller GmbH & Co. KG * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 6.18a * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_printf.c +Purpose : Replacement for printf to write formatted data via RTT +Revision: $Rev: 4351 $ +---------------------------------------------------------------------- +*/ +#include "SEGGER_RTT.h" +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64) +#endif + +#include +#include + + +#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) +#define FORMAT_FLAG_PAD_ZERO (1u << 1) +#define FORMAT_FLAG_PRINT_SIGN (1u << 2) +#define FORMAT_FLAG_ALTERNATE (1u << 3) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +typedef struct { + char* pBuffer; + unsigned BufferSize; + unsigned Cnt; + + int ReturnValue; + + unsigned RTTBufferIndex; +} SEGGER_RTT_PRINTF_DESC; + +/********************************************************************* +* +* Function prototypes +* +********************************************************************** +*/ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +/********************************************************************* +* +* Static code +* +********************************************************************** +*/ +/********************************************************************* +* +* _StoreChar +*/ +static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) { + unsigned Cnt; + + Cnt = p->Cnt; + if ((Cnt + 1u) <= p->BufferSize) { + *(p->pBuffer + Cnt) = c; + p->Cnt = Cnt + 1u; + p->ReturnValue++; + } + // + // Write part of string, when the buffer is full + // + if (p->Cnt == p->BufferSize) { + if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) { + p->ReturnValue = -1; + } else { + p->Cnt = 0u; + } + } +} + +/********************************************************************* +* +* _PrintUnsigned +*/ +static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + unsigned Div; + unsigned Digit; + unsigned Number; + unsigned Width; + char c; + + Number = v; + Digit = 1u; + // + // Get actual field width + // + Width = 1u; + while (Number >= Base) { + Number = (Number / Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + // + // Print leading chars if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) { + if (FieldWidth != 0u) { + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) { + c = '0'; + } else { + c = ' '; + } + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, c); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Compute Digit. + // Loop until Digit has the value of the highest digit required. + // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + // + while (1) { + if (NumDigits > 1u) { // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned) + NumDigits--; + } else { + Div = v / Digit; + if (Div < Base) { // Is our divider big enough to extract the highest digit from value? => Done + break; + } + } + Digit *= Base; + } + // + // Output digits + // + do { + Div = v / Digit; + v -= Div * Digit; + _StoreChar(pBufferDesc, _aV2C[Div]); + if (pBufferDesc->ReturnValue < 0) { + break; + } + Digit /= Base; + } while (Digit); + // + // Print trailing spaces if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + } +} + +/********************************************************************* +* +* _PrintInt +*/ +static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + unsigned Width; + int Number; + + Number = (v < 0) ? -v : v; + + // + // Get actual field width + // + Width = 1u; + while (Number >= (int)Base) { + Number = (Number / (int)Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) { + FieldWidth--; + } + + // + // Print leading spaces if necessary + // + if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + // + // Print sign if necessary + // + if (pBufferDesc->ReturnValue >= 0) { + if (v < 0) { + v = -v; + _StoreChar(pBufferDesc, '-'); + } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) { + _StoreChar(pBufferDesc, '+'); + } else { + + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print leading zeros if necessary + // + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, '0'); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print number without sign + // + _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); + } + } + } +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_vprintf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string +* pParamList Pointer to the list of arguments for the format string +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +*/ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) { + char c; + SEGGER_RTT_PRINTF_DESC BufferDesc; + int v; + unsigned NumDigits; + unsigned FormatFlags; + unsigned FieldWidth; + char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE]; + + BufferDesc.pBuffer = acBuffer; + BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE; + BufferDesc.Cnt = 0u; + BufferDesc.RTTBufferIndex = BufferIndex; + BufferDesc.ReturnValue = 0; + + do { + c = *sFormat; + sFormat++; + if (c == 0u) { + break; + } + if (c == '%') { + // + // Filter out flags + // + FormatFlags = 0u; + v = 1; + do { + c = *sFormat; + switch (c) { + case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break; + case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO; sFormat++; break; + case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN; sFormat++; break; + case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE; sFormat++; break; + default: v = 0; break; + } + } while (v); + // + // filter out field with + // + FieldWidth = 0u; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0'); + } while (1); + + // + // Filter out precision (number of digits to display) + // + NumDigits = 0u; + c = *sFormat; + if (c == '.') { + sFormat++; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + NumDigits = NumDigits * 10u + ((unsigned)c - '0'); + } while (1); + } + // + // Filter out length modifier + // + c = *sFormat; + do { + if ((c == 'l') || (c == 'h')) { + sFormat++; + c = *sFormat; + } else { + break; + } + } while (1); + // + // Handle specifiers + // + switch (c) { + case 'c': { + char c0; + v = va_arg(*pParamList, int); + c0 = (char)v; + _StoreChar(&BufferDesc, c0); + break; + } + case 'd': + v = va_arg(*pParamList, int); + _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'u': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'x': + case 'X': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags); + break; + case 's': + { + const char * s = va_arg(*pParamList, const char *); + do { + c = *s; + s++; + if (c == '\0') { + break; + } + _StoreChar(&BufferDesc, c); + } while (BufferDesc.ReturnValue >= 0); + } + break; + case 'p': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u); + break; + case '%': + _StoreChar(&BufferDesc, '%'); + break; + default: + break; + } + sFormat++; + } else { + _StoreChar(&BufferDesc, c); + } + } while (BufferDesc.ReturnValue >= 0); + + if (BufferDesc.ReturnValue > 0) { + // + // Write remaining data, if any + // + if (BufferDesc.Cnt != 0u) { + SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt); + } + BufferDesc.ReturnValue += (int)BufferDesc.Cnt; + } + return BufferDesc.ReturnValue; +} + +/********************************************************************* +* +* SEGGER_RTT_printf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string, followed by the arguments for conversion +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +* +* Notes +* (1) Conversion specifications have following syntax: +* %[flags][FieldWidth][.Precision]ConversionSpecifier +* (2) Supported flags: +* -: Left justify within the field width +* +: Always print sign extension for signed conversions +* 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision +* Supported conversion specifiers: +* c: Print the argument as one char +* d: Print the argument as a signed integer +* u: Print the argument as an unsigned integer +* x: Print the argument as an hexadecimal integer +* s: Print the string pointed to by the argument +* p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.) +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) { + int r; + va_list ParamList; + + va_start(ParamList, sFormat); + r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList); + va_end(ParamList); + return r; +} +/*************************** End of file ****************************/ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/apply_old_config.h b/HAL_Driver/sdk/integration/nrfx/legacy/apply_old_config.h new file mode 100644 index 0000000..8af10c1 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/apply_old_config.h @@ -0,0 +1,1391 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + +#ifndef APPLY_OLD_CONFIG_H__ +#define APPLY_OLD_CONFIG_H__ + +//------------------------------------------------------------------------------ +// Peripheral Resource Sharing (PRS) + +#if defined(PERIPHERAL_RESOURCE_SHARING_ENABLED) + +#define NRFX_PRS_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED +#define NRFX_PRS_BOX_0_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED +#define NRFX_PRS_BOX_1_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED +#define NRFX_PRS_BOX_2_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED +#define NRFX_PRS_BOX_3_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED +#define NRFX_PRS_BOX_4_ENABLED PERIPHERAL_RESOURCE_SHARING_ENABLED + +#if defined(COMMON_CONFIG_LOG_ENABLED) +#undef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED COMMON_CONFIG_LOG_ENABLED +#endif +#if defined(COMMON_CONFIG_LOG_LEVEL) +#undef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL COMMON_CONFIG_LOG_LEVEL +#endif +#if defined(COMMON_CONFIG_INFO_COLOR) +#undef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR COMMON_CONFIG_INFO_COLOR +#endif +#if defined(COMMON_CONFIG_DEBUG_COLOR) +#undef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR COMMON_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(PERIPHERAL_RESOURCE_SHARING_ENABLED) + +//------------------------------------------------------------------------------ +// CLOCK + +#if defined(NRF_CLOCK_ENABLED) + +#if defined(CLOCK_CONFIG_LF_CAL_ENABLED) && defined(CLOCK_CONFIG_LF_SRC) +#if (CLOCK_CONFIG_LF_SRC == CLOCK_LFCLKSRC_SRC_RC) +#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 1 +#endif +#endif + +#undef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED NRF_CLOCK_ENABLED + +#if defined(CLOCK_CONFIG_LF_SRC) +#undef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC CLOCK_CONFIG_LF_SRC +#endif +#if defined(CLOCK_CONFIG_IRQ_PRIORITY) +#undef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY CLOCK_CONFIG_IRQ_PRIORITY +#endif + +#if defined(CLOCK_CONFIG_LOG_ENABLED) +#undef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED CLOCK_CONFIG_LOG_ENABLED +#endif +#if defined(CLOCK_CONFIG_LOG_LEVEL) +#undef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL CLOCK_CONFIG_LOG_LEVEL +#endif +#if defined(CLOCK_CONFIG_INFO_COLOR) +#undef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR CLOCK_CONFIG_INFO_COLOR +#endif +#if defined(CLOCK_CONFIG_DEBUG_COLOR) +#undef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR CLOCK_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(NRF_CLOCK_ENABLED) + +//------------------------------------------------------------------------------ +// COMP + +#if defined(COMP_ENABLED) + +#undef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED COMP_ENABLED + +#if defined(COMP_CONFIG_REF) +#undef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF COMP_CONFIG_REF +#endif +#if defined(COMP_CONFIG_MAIN_MODE) +#undef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE COMP_CONFIG_MAIN_MODE +#endif +#if defined(COMP_CONFIG_SPEED_MODE) +#undef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE COMP_CONFIG_SPEED_MODE +#endif +#if defined(COMP_CONFIG_HYST) +#undef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST COMP_CONFIG_HYST +#endif +#if defined(COMP_CONFIG_ISOURCE) +#undef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE COMP_CONFIG_ISOURCE +#endif +#if defined(COMP_CONFIG_INPUT) +#undef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT COMP_CONFIG_INPUT +#endif +#if defined(COMP_CONFIG_IRQ_PRIORITY) +#undef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY COMP_CONFIG_IRQ_PRIORITY +#endif + +#if defined(COMP_CONFIG_LOG_ENABLED) +#undef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED COMP_CONFIG_LOG_ENABLED +#endif +#if defined(COMP_CONFIG_LOG_LEVEL) +#undef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL COMP_CONFIG_LOG_LEVEL +#endif +#if defined(COMP_CONFIG_INFO_COLOR) +#undef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR COMP_CONFIG_INFO_COLOR +#endif +#if defined(COMP_CONFIG_DEBUG_COLOR) +#undef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR COMP_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(COMP_ENABLED) + +//------------------------------------------------------------------------------ +// GPIOTE + +#if defined(GPIOTE_ENABLED) + +#undef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED GPIOTE_ENABLED + +#if defined(GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS) +#undef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#endif + +#if defined(GPIOTE_CONFIG_IRQ_PRIORITY) +#undef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY GPIOTE_CONFIG_IRQ_PRIORITY +#endif + +#if defined(GPIOTE_CONFIG_LOG_ENABLED) +#undef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED GPIOTE_CONFIG_LOG_ENABLED +#endif +#if defined(GPIOTE_CONFIG_LOG_LEVEL) +#undef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL GPIOTE_CONFIG_LOG_LEVEL +#endif +#if defined(GPIOTE_CONFIG_INFO_COLOR) +#undef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR GPIOTE_CONFIG_INFO_COLOR +#endif +#if defined(GPIOTE_CONFIG_DEBUG_COLOR) +#undef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR GPIOTE_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(GPIOTE_ENABLED) + +//------------------------------------------------------------------------------ +// I2S + +#if defined(I2S_ENABLED) + +#undef NRFX_I2S_ENABLED +#define NRFX_I2S_ENABLED I2S_ENABLED + +#if defined(I2S_CONFIG_SCK_PIN) +#undef NRFX_I2S_CONFIG_SCK_PIN +#define NRFX_I2S_CONFIG_SCK_PIN I2S_CONFIG_SCK_PIN +#endif +#if defined(I2S_CONFIG_LRCK_PIN) +#undef NRFX_I2S_CONFIG_LRCK_PIN +#define NRFX_I2S_CONFIG_LRCK_PIN I2S_CONFIG_LRCK_PIN +#endif +#if defined(I2S_CONFIG_MCK_PIN) +#undef NRFX_I2S_CONFIG_MCK_PIN +#define NRFX_I2S_CONFIG_MCK_PIN I2S_CONFIG_MCK_PIN +#endif +#if defined(I2S_CONFIG_SDOUT_PIN) +#undef NRFX_I2S_CONFIG_SDOUT_PIN +#define NRFX_I2S_CONFIG_SDOUT_PIN I2S_CONFIG_SDOUT_PIN +#endif +#if defined(I2S_CONFIG_SDIN_PIN) +#undef NRFX_I2S_CONFIG_SDIN_PIN +#define NRFX_I2S_CONFIG_SDIN_PIN I2S_CONFIG_SDIN_PIN +#endif + +#if defined(I2S_CONFIG_MASTER) +#undef NRFX_I2S_CONFIG_MASTER +#define NRFX_I2S_CONFIG_MASTER I2S_CONFIG_MASTER +#endif +#if defined(I2S_CONFIG_FORMAT) +#undef NRFX_I2S_CONFIG_FORMAT +#define NRFX_I2S_CONFIG_FORMAT I2S_CONFIG_FORMAT +#endif +#if defined(I2S_CONFIG_ALIGN) +#undef NRFX_I2S_CONFIG_ALIGN +#define NRFX_I2S_CONFIG_ALIGN I2S_CONFIG_ALIGN +#endif +#if defined(I2S_CONFIG_SWIDTH) +#undef NRFX_I2S_CONFIG_SWIDTH +#define NRFX_I2S_CONFIG_SWIDTH I2S_CONFIG_SWIDTH +#endif +#if defined(I2S_CONFIG_CHANNELS) +#undef NRFX_I2S_CONFIG_CHANNELS +#define NRFX_I2S_CONFIG_CHANNELS I2S_CONFIG_CHANNELS +#endif +#if defined(I2S_CONFIG_MCK_SETUP) +#undef NRFX_I2S_CONFIG_MCK_SETUP +#define NRFX_I2S_CONFIG_MCK_SETUP I2S_CONFIG_MCK_SETUP +#endif +#if defined(I2S_CONFIG_RATIO) +#undef NRFX_I2S_CONFIG_RATIO +#define NRFX_I2S_CONFIG_RATIO I2S_CONFIG_RATIO +#endif +#if defined(I2S_CONFIG_IRQ_PRIORITY) +#undef NRFX_I2S_CONFIG_IRQ_PRIORITY +#define NRFX_I2S_CONFIG_IRQ_PRIORITY I2S_CONFIG_IRQ_PRIORITY +#endif + +#if defined(I2S_CONFIG_LOG_ENABLED) +#undef NRFX_I2S_CONFIG_LOG_ENABLED +#define NRFX_I2S_CONFIG_LOG_ENABLED I2S_CONFIG_LOG_ENABLED +#endif +#if defined(I2S_CONFIG_LOG_LEVEL) +#undef NRFX_I2S_CONFIG_LOG_LEVEL +#define NRFX_I2S_CONFIG_LOG_LEVEL I2S_CONFIG_LOG_LEVEL +#endif +#if defined(I2S_CONFIG_INFO_COLOR) +#undef NRFX_I2S_CONFIG_INFO_COLOR +#define NRFX_I2S_CONFIG_INFO_COLOR I2S_CONFIG_INFO_COLOR +#endif +#if defined(I2S_CONFIG_DEBUG_COLOR) +#undef NRFX_I2S_CONFIG_DEBUG_COLOR +#define NRFX_I2S_CONFIG_DEBUG_COLOR I2S_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(I2S_ENABLED) + +//------------------------------------------------------------------------------ +// LPCOMP + +#if defined(LPCOMP_ENABLED) + +#undef NRFX_LPCOMP_ENABLED +#define NRFX_LPCOMP_ENABLED LPCOMP_ENABLED + +#if defined(LPCOMP_CONFIG_REFERENCE) +#undef NRFX_LPCOMP_CONFIG_REFERENCE +#define NRFX_LPCOMP_CONFIG_REFERENCE LPCOMP_CONFIG_REFERENCE +#endif +#if defined(LPCOMP_CONFIG_DETECTION) +#undef NRFX_LPCOMP_CONFIG_DETECTION +#define NRFX_LPCOMP_CONFIG_DETECTION LPCOMP_CONFIG_DETECTION +#endif +#if defined(LPCOMP_CONFIG_INPUT) +#undef NRFX_LPCOMP_CONFIG_INPUT +#define NRFX_LPCOMP_CONFIG_INPUT LPCOMP_CONFIG_INPUT +#endif +#if defined(LPCOMP_CONFIG_HYST) +#undef NRFX_LPCOMP_CONFIG_HYST +#define NRFX_LPCOMP_CONFIG_HYST LPCOMP_CONFIG_HYST +#endif +#if defined(LPCOMP_CONFIG_IRQ_PRIORITY) +#undef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY +#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY LPCOMP_CONFIG_IRQ_PRIORITY +#endif + +#if defined(LPCOMP_CONFIG_LOG_ENABLED) +#undef NRFX_LPCOMP_CONFIG_LOG_ENABLED +#define NRFX_LPCOMP_CONFIG_LOG_ENABLED LPCOMP_CONFIG_LOG_ENABLED +#endif +#if defined(LPCOMP_CONFIG_LOG_LEVEL) +#undef NRFX_LPCOMP_CONFIG_LOG_LEVEL +#define NRFX_LPCOMP_CONFIG_LOG_LEVEL LPCOMP_CONFIG_LOG_LEVEL +#endif +#if defined(LPCOMP_CONFIG_INFO_COLOR) +#undef NRFX_LPCOMP_CONFIG_INFO_COLOR +#define NRFX_LPCOMP_CONFIG_INFO_COLOR LPCOMP_CONFIG_INFO_COLOR +#endif +#if defined(LPCOMP_CONFIG_DEBUG_COLOR) +#undef NRFX_LPCOMP_CONFIG_DEBUG_COLOR +#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR LPCOMP_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(LPCOMP_ENABLED) + +//------------------------------------------------------------------------------ +// PDM + +#if defined(PDM_ENABLED) + +#undef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED PDM_ENABLED + +#if defined(PDM_CONFIG_MODE) +#undef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE PDM_CONFIG_MODE +#endif +#if defined(PDM_CONFIG_EDGE) +#undef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE PDM_CONFIG_EDGE +#endif +#if defined(PDM_CONFIG_CLOCK_FREQ) +#undef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ PDM_CONFIG_CLOCK_FREQ +#endif +#if defined(PDM_CONFIG_IRQ_PRIORITY) +#undef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY PDM_CONFIG_IRQ_PRIORITY +#endif + +#if defined(PDM_CONFIG_LOG_ENABLED) +#undef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED PDM_CONFIG_LOG_ENABLED +#endif +#if defined(PDM_CONFIG_LOG_LEVEL) +#undef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL PDM_CONFIG_LOG_LEVEL +#endif +#if defined(PDM_CONFIG_INFO_COLOR) +#undef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR PDM_CONFIG_INFO_COLOR +#endif +#if defined(PDM_CONFIG_DEBUG_COLOR) +#undef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR PDM_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(PDM_ENABLED) + +//------------------------------------------------------------------------------ +// POWER + +#if defined(POWER_ENABLED) + +#undef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED POWER_ENABLED + +#if defined(POWER_CONFIG_IRQ_PRIORITY) +#undef NRFX_POWER_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_CONFIG_IRQ_PRIORITY POWER_CONFIG_IRQ_PRIORITY +#endif + +#if defined(POWER_CONFIG_DEFAULT_DCDCEN) +#undef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN POWER_CONFIG_DEFAULT_DCDCEN +#endif +#if defined(POWER_CONFIG_DEFAULT_DCDCENHV) +#undef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV POWER_CONFIG_DEFAULT_DCDCENHV +#endif + +#endif // defined(POWER_ENABLED) + +//------------------------------------------------------------------------------ +// PPI + +#if defined(PPI_ENABLED) + +#undef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED PPI_ENABLED + +#if defined(PPI_CONFIG_LOG_ENABLED) +#undef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED PPI_CONFIG_LOG_ENABLED +#endif +#if defined(PPI_CONFIG_LOG_LEVEL) +#undef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL PPI_CONFIG_LOG_LEVEL +#endif +#if defined(PPI_CONFIG_INFO_COLOR) +#undef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR PPI_CONFIG_INFO_COLOR +#endif +#if defined(PPI_CONFIG_DEBUG_COLOR) +#undef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR PPI_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(PPI_ENABLED) + +//------------------------------------------------------------------------------ +// PWM + +#if defined(PWM_ENABLED) + +#undef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED PWM_ENABLED + +#if defined(PWM0_ENABLED) +#undef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED PWM0_ENABLED +#endif +#if defined(PWM1_ENABLED) +#undef NRFX_PWM1_ENABLED +#define NRFX_PWM1_ENABLED PWM1_ENABLED +#endif +#if defined(PWM2_ENABLED) +#undef NRFX_PWM2_ENABLED +#define NRFX_PWM2_ENABLED PWM2_ENABLED +#endif +#if defined(PWM3_ENABLED) +#undef NRFX_PWM3_ENABLED +#define NRFX_PWM3_ENABLED PWM3_ENABLED +#endif + +#if defined(PWM_DEFAULT_CONFIG_OUT0_PIN) +#undef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN PWM_DEFAULT_CONFIG_OUT0_PIN +#endif +#if defined(PWM_DEFAULT_CONFIG_OUT1_PIN) +#undef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN PWM_DEFAULT_CONFIG_OUT1_PIN +#endif +#if defined(PWM_DEFAULT_CONFIG_OUT2_PIN) +#undef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN PWM_DEFAULT_CONFIG_OUT2_PIN +#endif +#if defined(PWM_DEFAULT_CONFIG_OUT3_PIN) +#undef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN PWM_DEFAULT_CONFIG_OUT3_PIN +#endif +#if defined(PWM_DEFAULT_CONFIG_BASE_CLOCK) +#undef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK PWM_DEFAULT_CONFIG_BASE_CLOCK +#endif +#if defined(PWM_DEFAULT_CONFIG_COUNT_MODE) +#undef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE PWM_DEFAULT_CONFIG_COUNT_MODE +#endif +#if defined(PWM_DEFAULT_CONFIG_TOP_VALUE) +#undef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE PWM_DEFAULT_CONFIG_TOP_VALUE +#endif +#if defined(PWM_DEFAULT_CONFIG_LOAD_MODE) +#undef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE PWM_DEFAULT_CONFIG_LOAD_MODE +#endif +#if defined(PWM_DEFAULT_CONFIG_STEP_MODE) +#undef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE PWM_DEFAULT_CONFIG_STEP_MODE +#endif +#if defined(PWM_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(PWM_CONFIG_LOG_ENABLED) +#undef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED PWM_CONFIG_LOG_ENABLED +#endif +#if defined(PWM_CONFIG_LOG_LEVEL) +#undef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL PWM_CONFIG_LOG_LEVEL +#endif +#if defined(PWM_CONFIG_INFO_COLOR) +#undef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR PWM_CONFIG_INFO_COLOR +#endif +#if defined(PWM_CONFIG_DEBUG_COLOR) +#undef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR PWM_CONFIG_DEBUG_COLOR +#endif + +#if defined(PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) +#undef NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#define NRFX_PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#endif +#if defined(PWM_NRF52_ANOMALY_109_EGU_INSTANCE) +#undef NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE +#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE PWM_NRF52_ANOMALY_109_EGU_INSTANCE +#endif + +#endif // defined(PWM_ENABLED) + +//------------------------------------------------------------------------------ +// QDEC + +#if defined(QDEC_ENABLED) + +#undef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED QDEC_ENABLED + +#if defined(QDEC_CONFIG_REPORTPER) +#undef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER QDEC_CONFIG_REPORTPER +#endif +#if defined(QDEC_CONFIG_SAMPLEPER) +#undef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER QDEC_CONFIG_SAMPLEPER +#endif +#if defined(QDEC_CONFIG_PIO_A) +#undef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A QDEC_CONFIG_PIO_A +#endif +#if defined(QDEC_CONFIG_PIO_B) +#undef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B QDEC_CONFIG_PIO_B +#endif +#if defined(QDEC_CONFIG_PIO_LED) +#undef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED QDEC_CONFIG_PIO_LED +#endif +#if defined(QDEC_CONFIG_LEDPRE) +#undef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE QDEC_CONFIG_LEDPRE +#endif +#if defined(QDEC_CONFIG_LEDPOL) +#undef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL QDEC_CONFIG_LEDPOL +#endif +#if defined(QDEC_CONFIG_DBFEN) +#undef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN QDEC_CONFIG_DBFEN +#endif +#if defined(QDEC_CONFIG_SAMPLE_INTEN) +#undef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN QDEC_CONFIG_SAMPLE_INTEN +#endif +#if defined(QDEC_CONFIG_IRQ_PRIORITY) +#undef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY QDEC_CONFIG_IRQ_PRIORITY +#endif + +#if defined(QDEC_CONFIG_LOG_ENABLED) +#undef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED QDEC_CONFIG_LOG_ENABLED +#endif +#if defined(QDEC_CONFIG_LOG_LEVEL) +#undef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL QDEC_CONFIG_LOG_LEVEL +#endif +#if defined(QDEC_CONFIG_INFO_COLOR) +#undef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR QDEC_CONFIG_INFO_COLOR +#endif +#if defined(QDEC_CONFIG_DEBUG_COLOR) +#undef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR QDEC_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(QDEC_ENABLED) + +//------------------------------------------------------------------------------ +// QSPI + +#if defined(QSPI_ENABLED) + +#undef NRFX_QSPI_ENABLED +#define NRFX_QSPI_ENABLED QSPI_ENABLED + +#if defined(QSPI_CONFIG_SCK_DELAY) +#undef NRFX_QSPI_CONFIG_SCK_DELAY +#define NRFX_QSPI_CONFIG_SCK_DELAY QSPI_CONFIG_SCK_DELAY +#endif +#if defined(QSPI_CONFIG_XIP_OFFSET) +#undef NRFX_QSPI_CONFIG_XIP_OFFSET +#define NRFX_QSPI_CONFIG_XIP_OFFSET QSPI_CONFIG_XIP_OFFSET +#endif +#if defined(QSPI_CONFIG_READOC) +#undef NRFX_QSPI_CONFIG_READOC +#define NRFX_QSPI_CONFIG_READOC QSPI_CONFIG_READOC +#endif +#if defined(QSPI_CONFIG_WRITEOC) +#undef NRFX_QSPI_CONFIG_WRITEOC +#define NRFX_QSPI_CONFIG_WRITEOC QSPI_CONFIG_WRITEOC +#endif +#if defined(QSPI_CONFIG_ADDRMODE) +#undef NRFX_QSPI_CONFIG_ADDRMODE +#define NRFX_QSPI_CONFIG_ADDRMODE QSPI_CONFIG_ADDRMODE +#endif +#if defined(QSPI_CONFIG_MODE) +#undef NRFX_QSPI_CONFIG_MODE +#define NRFX_QSPI_CONFIG_MODE QSPI_CONFIG_MODE +#endif +#if defined(QSPI_CONFIG_FREQUENCY) +#undef NRFX_QSPI_CONFIG_FREQUENCY +#define NRFX_QSPI_CONFIG_FREQUENCY QSPI_CONFIG_FREQUENCY +#endif +#if defined(QSPI_CONFIG_IRQ_PRIORITY) +#undef NRFX_QSPI_CONFIG_IRQ_PRIORITY +#define NRFX_QSPI_CONFIG_IRQ_PRIORITY QSPI_CONFIG_IRQ_PRIORITY +#endif + +#if defined(QSPI_PIN_SCK) +#undef NRFX_QSPI_PIN_SCK +#define NRFX_QSPI_PIN_SCK QSPI_PIN_SCK +#endif +#if defined(QSPI_PIN_CSN) +#undef NRFX_QSPI_PIN_CSN +#define NRFX_QSPI_PIN_CSN QSPI_PIN_CSN +#endif +#if defined(QSPI_PIN_IO0) +#undef NRFX_QSPI_PIN_IO0 +#define NRFX_QSPI_PIN_IO0 QSPI_PIN_IO0 +#endif +#if defined(QSPI_PIN_IO0) +#undef NRFX_QSPI_PIN_IO0 +#define NRFX_QSPI_PIN_IO0 QSPI_PIN_IO0 +#endif +#if defined(QSPI_PIN_IO1) +#undef NRFX_QSPI_PIN_IO1 +#define NRFX_QSPI_PIN_IO1 QSPI_PIN_IO1 +#endif +#if defined(QSPI_PIN_IO2) +#undef NRFX_QSPI_PIN_IO2 +#define NRFX_QSPI_PIN_IO2 QSPI_PIN_IO2 +#endif +#if defined(QSPI_PIN_IO3) +#undef NRFX_QSPI_PIN_IO3 +#define NRFX_QSPI_PIN_IO3 QSPI_PIN_IO3 +#endif + +#endif // defined(QSPI_ENABLED) + +//------------------------------------------------------------------------------ +// RNG + +#if defined(RNG_ENABLED) + +#undef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED RNG_ENABLED + +#if defined(RNG_CONFIG_ERROR_CORRECTION) +#undef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION RNG_CONFIG_ERROR_CORRECTION +#endif + +#if defined(RNG_CONFIG_IRQ_PRIORITY) +#undef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY RNG_CONFIG_IRQ_PRIORITY +#endif + +#if defined(RNG_CONFIG_LOG_ENABLED) +#undef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED RNG_CONFIG_LOG_ENABLED +#endif +#if defined(RNG_CONFIG_LOG_LEVEL) +#undef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL RNG_CONFIG_LOG_LEVEL +#endif +#if defined(RNG_CONFIG_INFO_COLOR) +#undef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR RNG_CONFIG_INFO_COLOR +#endif +#if defined(RNG_CONFIG_DEBUG_COLOR) +#undef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR RNG_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(RNG_ENABLED) + +//------------------------------------------------------------------------------ +// RTC + +#if defined(RTC_ENABLED) + +#undef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED RTC_ENABLED + +#if defined(RTC0_ENABLED) +#undef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED RTC0_ENABLED +#endif +#if defined(RTC1_ENABLED) +#undef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED RTC1_ENABLED +#endif +#if defined(RTC2_ENABLED) +#undef NRFX_RTC2_ENABLED +#define NRFX_RTC2_ENABLED RTC2_ENABLED +#endif + +#if defined(RTC_DEFAULT_CONFIG_FREQUENCY) +#undef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY RTC_DEFAULT_CONFIG_FREQUENCY +#endif +#if defined(RTC_DEFAULT_CONFIG_RELIABLE) +#undef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE RTC_DEFAULT_CONFIG_RELIABLE +#endif +#if defined(RTC_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(NRF_MAXIMUM_LATENCY_US) +#undef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US NRF_MAXIMUM_LATENCY_US +#endif + +#if defined(RTC_CONFIG_LOG_ENABLED) +#undef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED RTC_CONFIG_LOG_ENABLED +#endif +#if defined(RTC_CONFIG_LOG_LEVEL) +#undef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL RTC_CONFIG_LOG_LEVEL +#endif +#if defined(RTC_CONFIG_INFO_COLOR) +#undef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR RTC_CONFIG_INFO_COLOR +#endif +#if defined(RTC_CONFIG_DEBUG_COLOR) +#undef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR RTC_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(RTC_ENABLED) + +//------------------------------------------------------------------------------ +// SAADC + +#if defined(SAADC_ENABLED) + +#undef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED SAADC_ENABLED + +#if defined(SAADC_CONFIG_RESOLUTION) +#undef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION SAADC_CONFIG_RESOLUTION +#endif +#if defined(SAADC_CONFIG_OVERSAMPLE) +#undef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE SAADC_CONFIG_OVERSAMPLE +#endif +#if defined(SAADC_CONFIG_LP_MODE) +#undef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE SAADC_CONFIG_LP_MODE +#endif +#if defined(SAADC_CONFIG_IRQ_PRIORITY) +#undef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY SAADC_CONFIG_IRQ_PRIORITY +#endif + +#if defined(SAADC_CONFIG_LOG_ENABLED) +#undef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED SAADC_CONFIG_LOG_ENABLED +#endif +#if defined(SAADC_CONFIG_LOG_LEVEL) +#undef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL SAADC_CONFIG_LOG_LEVEL +#endif +#if defined(SAADC_CONFIG_INFO_COLOR) +#undef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR SAADC_CONFIG_INFO_COLOR +#endif +#if defined(SAADC_CONFIG_DEBUG_COLOR) +#undef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR SAADC_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(SAADC_ENABLED) + +//------------------------------------------------------------------------------ +// SPI + +#if defined(SPI_ENABLED) + +#undef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED \ + (SPI_ENABLED && (NRFX_SPI0_ENABLED || NRFX_SPI1_ENABLED || NRFX_SPI2_ENABLED)) +#undef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED \ + (SPI_ENABLED && (NRFX_SPIM0_ENABLED || NRFX_SPIM1_ENABLED || NRFX_SPIM2_ENABLED)) + +#if defined(SPI_PRESENT) && !defined(SPIM_PRESENT) + +#undef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED SPI0_ENABLED +#undef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 + +#undef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED SPI1_ENABLED +#undef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 + +#undef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED SPI2_ENABLED +#undef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED 0 + +#elif !defined(SPI_PRESENT) && defined(SPIM_PRESENT) + +#undef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 0 +#undef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED SPI0_ENABLED + +#undef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 0 +#undef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED SPI1_ENABLED + +#undef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED 0 +#undef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED SPI2_ENABLED + +#else // -> defined(SPI_PRESENT) && defined(SPIM_PRESENT) + +#undef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED (SPI0_ENABLED && !SPI0_USE_EASY_DMA) +#undef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED (SPI0_ENABLED && SPI0_USE_EASY_DMA) + +#undef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED (SPI1_ENABLED && !SPI1_USE_EASY_DMA) +#undef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED (SPI1_ENABLED && SPI1_USE_EASY_DMA) + +#undef NRFX_SPI2_ENABLED +#define NRFX_SPI2_ENABLED (SPI2_ENABLED && !SPI2_USE_EASY_DMA) +#undef NRFX_SPIM2_ENABLED +#define NRFX_SPIM2_ENABLED (SPI2_ENABLED && SPI2_USE_EASY_DMA) + +#endif // -> defined(SPI_PRESENT) && defined(SPIM_PRESENT) + +#if defined(NRF_SPI_DRV_MISO_PULLUP_CFG) +#undef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG NRF_SPI_DRV_MISO_PULLUP_CFG +#undef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG NRF_SPI_DRV_MISO_PULLUP_CFG +#endif + +#if defined(SPI_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#undef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(SPI_CONFIG_LOG_ENABLED) +#undef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED SPI_CONFIG_LOG_ENABLED +#undef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED SPI_CONFIG_LOG_ENABLED +#endif +#if defined(SPI_CONFIG_LOG_LEVEL) +#undef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL SPI_CONFIG_LOG_LEVEL +#undef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL SPI_CONFIG_LOG_LEVEL +#endif +#if defined(SPI_CONFIG_INFO_COLOR) +#undef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR SPI_CONFIG_INFO_COLOR +#undef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR SPI_CONFIG_INFO_COLOR +#endif +#if defined(SPI_CONFIG_DEBUG_COLOR) +#undef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR +#undef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR +#endif + +#if defined(SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) +#undef NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#define NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#endif + +#endif // defined(SPI_ENABLED) + +//------------------------------------------------------------------------------ +// SPIS + +#if defined(SPIS_ENABLED) + +#undef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED SPIS_ENABLED + +#if defined(SPIS0_ENABLED) +#undef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED SPIS0_ENABLED +#endif +#if defined(SPIS1_ENABLED) +#undef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED SPIS1_ENABLED +#endif +#if defined(SPIS2_ENABLED) +#undef NRFX_SPIS2_ENABLED +#define NRFX_SPIS2_ENABLED SPIS2_ENABLED +#endif + +#if defined(SPIS_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#endif +#if defined(SPIS_DEFAULT_MODE) +#undef NRFX_SPIS_DEFAULT_MODE +#define NRFX_SPIS_DEFAULT_MODE SPIS_DEFAULT_MODE +#endif +#if defined(SPIS_DEFAULT_BIT_ORDER) +#undef NRFX_SPIS_DEFAULT_BIT_ORDER +#define NRFX_SPIS_DEFAULT_BIT_ORDER SPIS_DEFAULT_BIT_ORDER +#endif +#if defined(SPIS_DEFAULT_DEF) +#undef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF SPIS_DEFAULT_DEF +#endif +#if defined(SPIS_DEFAULT_ORC) +#undef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC SPIS_DEFAULT_ORC +#endif + +#if defined(SPIS_CONFIG_LOG_ENABLED) +#undef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED SPIS_CONFIG_LOG_ENABLED +#endif +#if defined(SPIS_CONFIG_LOG_LEVEL) +#undef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL SPIS_CONFIG_LOG_LEVEL +#endif +#if defined(SPIS_CONFIG_INFO_COLOR) +#undef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR SPIS_CONFIG_INFO_COLOR +#endif +#if defined(SPIS_CONFIG_DEBUG_COLOR) +#undef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR SPIS_CONFIG_DEBUG_COLOR +#endif + +#if defined(SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED) +#undef NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#endif + +#endif // defined(SPIS_ENABLED) + +//------------------------------------------------------------------------------ +// SWI + +#if defined(SWI_DISABLE0) +#undef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 1 +#endif +#if defined(SWI_DISABLE1) +#undef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 1 +#endif +#if defined(SWI_DISABLE2) +#undef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 1 +#endif +#if defined(SWI_DISABLE3) +#undef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 1 +#endif +#if defined(SWI_DISABLE4) +#undef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 1 +#endif +#if defined(SWI_DISABLE5) +#undef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 1 +#endif + +#if defined(EGU_ENABLED) +#undef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED EGU_ENABLED +#endif + +#if defined(SWI_CONFIG_LOG_ENABLED) +#undef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED SWI_CONFIG_LOG_ENABLED +#endif +#if defined(SWI_CONFIG_LOG_LEVEL) +#undef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL SWI_CONFIG_LOG_LEVEL +#endif +#if defined(SWI_CONFIG_INFO_COLOR) +#undef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR SWI_CONFIG_INFO_COLOR +#endif +#if defined(SWI_CONFIG_DEBUG_COLOR) +#undef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR SWI_CONFIG_DEBUG_COLOR +#endif + +//------------------------------------------------------------------------------ +// SysTick + +#if defined(SYSTICK_ENABLED) + +#undef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED SYSTICK_ENABLED + +#endif // defined(SYSTICK_ENABLED) + +//------------------------------------------------------------------------------ +// TIMER + +#if defined(TIMER_ENABLED) + +#undef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED TIMER_ENABLED + +#if defined(TIMER0_ENABLED) +#undef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED TIMER0_ENABLED +#endif +#if defined(TIMER1_ENABLED) +#undef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED TIMER1_ENABLED +#endif +#if defined(TIMER2_ENABLED) +#undef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED TIMER2_ENABLED +#endif +#if defined(TIMER3_ENABLED) +#undef NRFX_TIMER3_ENABLED +#define NRFX_TIMER3_ENABLED TIMER3_ENABLED +#endif +#if defined(TIMER4_ENABLED) +#undef NRFX_TIMER4_ENABLED +#define NRFX_TIMER4_ENABLED TIMER4_ENABLED +#endif + +#if defined(TIMER_DEFAULT_CONFIG_FREQUENCY) +#undef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY TIMER_DEFAULT_CONFIG_FREQUENCY +#endif +#if defined(TIMER_DEFAULT_CONFIG_MODE) +#undef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE TIMER_DEFAULT_CONFIG_MODE +#endif +#if defined(TIMER_DEFAULT_CONFIG_BIT_WIDTH) +#undef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH TIMER_DEFAULT_CONFIG_BIT_WIDTH +#endif +#if defined(TIMER_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(TIMER_CONFIG_LOG_ENABLED) +#undef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED TIMER_CONFIG_LOG_ENABLED +#endif +#if defined(TIMER_CONFIG_LOG_LEVEL) +#undef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL TIMER_CONFIG_LOG_LEVEL +#endif +#if defined(TIMER_CONFIG_INFO_COLOR) +#undef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR TIMER_CONFIG_INFO_COLOR +#endif +#if defined(TIMER_CONFIG_DEBUG_COLOR) +#undef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR TIMER_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(TIMER_ENABLED) + +//------------------------------------------------------------------------------ +// TWI +#define TWI_ONLY ( defined(TWI_PRESENT) && !defined(TWIM_PRESENT)) +#define TWIM_ONLY (!defined(TWI_PRESENT) && defined(TWIM_PRESENT)) +#define TWI_AND_TWIM ( defined(TWI_PRESENT) && defined(TWIM_PRESENT)) + +#if defined(TWI_ENABLED) + +#undef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED (TWI_ENABLED && (NRFX_TWI0_ENABLED || NRFX_TWI1_ENABLED)) +#undef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED (TWI_ENABLED && (NRFX_TWIM0_ENABLED || NRFX_TWIM1_ENABLED)) + +#if defined(TWI_PRESENT) && !defined(TWIM_PRESENT) + +#undef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED TWI0_ENABLED +#undef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 + +#undef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED TWI1_ENABLED +#undef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED 0 + +#elif !defined(TWI_PRESENT) && defined(TWIM_PRESENT) + +#undef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#undef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED TWI0_ENABLED + +#undef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED 0 +#undef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED TWI1_ENABLED + +#else // -> defined(TWI_PRESENT) && defined(TWIM_PRESENT) + +#undef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED (TWI0_ENABLED && !TWI0_USE_EASY_DMA) +#undef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED (TWI0_ENABLED && TWI0_USE_EASY_DMA) + +#undef NRFX_TWI1_ENABLED +#define NRFX_TWI1_ENABLED (TWI1_ENABLED && !TWI1_USE_EASY_DMA) +#undef NRFX_TWIM1_ENABLED +#define NRFX_TWIM1_ENABLED (TWI1_ENABLED && TWI1_USE_EASY_DMA) + +#endif // -> defined(TWI_PRESENT) && defined(TWIM_PRESENT) + +#if defined(TWI_DEFAULT_CONFIG_FREQUENCY) +#undef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY TWI_DEFAULT_CONFIG_FREQUENCY +#undef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY TWI_DEFAULT_CONFIG_FREQUENCY +#endif +#if defined(TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT) +#undef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#undef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#endif +#if defined(TWI_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#undef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(TWI_CONFIG_LOG_ENABLED) +#undef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED TWI_CONFIG_LOG_ENABLED +#undef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED TWI_CONFIG_LOG_ENABLED +#endif +#if defined(TWI_CONFIG_LOG_LEVEL) +#undef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL TWI_CONFIG_LOG_LEVEL +#undef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL TWI_CONFIG_LOG_LEVEL +#endif +#if defined(TWI_CONFIG_INFO_COLOR) +#undef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR TWI_CONFIG_INFO_COLOR +#undef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR TWI_CONFIG_INFO_COLOR +#endif +#if defined(TWI_CONFIG_DEBUG_COLOR) +#undef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR TWI_CONFIG_DEBUG_COLOR +#undef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR TWI_CONFIG_DEBUG_COLOR +#endif + +#if defined(TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) +#undef NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#define NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED +#endif + +#endif // defined(TWI_ENABLED) + +//------------------------------------------------------------------------------ +// TWIS + +#if defined(TWIS_ENABLED) + +#undef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED TWIS_ENABLED + +#if defined(TWIS0_ENABLED) +#undef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED TWIS0_ENABLED +#endif +#if defined(TWIS1_ENABLED) +#undef NRFX_TWIS1_ENABLED +#define NRFX_TWIS1_ENABLED TWIS1_ENABLED +#endif + +#if defined(TWIS_ASSUME_INIT_AFTER_RESET_ONLY) +#undef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#endif +#if defined(TWIS_NO_SYNC_MODE) +#undef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE TWIS_NO_SYNC_MODE +#endif + +#if defined(TWIS_DEFAULT_CONFIG_ADDR0) +#undef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 TWIS_DEFAULT_CONFIG_ADDR0 +#endif +#if defined(TWIS_DEFAULT_CONFIG_ADDR1) +#undef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 TWIS_DEFAULT_CONFIG_ADDR1 +#endif +#if defined(TWIS_DEFAULT_CONFIG_SCL_PULL) +#undef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL TWIS_DEFAULT_CONFIG_SCL_PULL +#endif +#if defined(TWIS_DEFAULT_CONFIG_SDA_PULL) +#undef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL TWIS_DEFAULT_CONFIG_SDA_PULL +#endif +#if defined(TWIS_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(TWIS_CONFIG_LOG_ENABLED) +#undef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED TWIS_CONFIG_LOG_ENABLED +#endif +#if defined(TWIS_CONFIG_LOG_LEVEL) +#undef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL TWIS_CONFIG_LOG_LEVEL +#endif +#if defined(TWIS_CONFIG_INFO_COLOR) +#undef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR TWIS_CONFIG_INFO_COLOR +#endif +#if defined(TWIS_CONFIG_DEBUG_COLOR) +#undef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR TWIS_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(TWIS_ENABLED) + +//------------------------------------------------------------------------------ +// UART + +#if defined(UART_ENABLED) + +#undef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED (UART_ENABLED && NRFX_UART0_ENABLED) +#undef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED (UART_ENABLED && (NRFX_UARTE0_ENABLED || NRFX_UARTE1_ENABLED)) + +#if defined(UART0_ENABLED) +#undef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED (UART0_ENABLED && UART_LEGACY_SUPPORT) +#undef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED (UART0_ENABLED && UART_EASY_DMA_SUPPORT) +#endif +#if defined(UART1_ENABLED) +#undef NRFX_UARTE1_ENABLED +#define NRFX_UARTE1_ENABLED (UART1_ENABLED && UART_EASY_DMA_SUPPORT) +#endif + +#if defined(UART_DEFAULT_CONFIG_HWFC) +#undef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC UART_DEFAULT_CONFIG_HWFC +#undef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC UART_DEFAULT_CONFIG_HWFC +#endif +#if defined(UART_DEFAULT_CONFIG_PARITY) +#undef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY UART_DEFAULT_CONFIG_PARITY +#undef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY UART_DEFAULT_CONFIG_PARITY +#endif +#if defined(UART_DEFAULT_CONFIG_BAUDRATE) +#undef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE +#undef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE +#endif +#if defined(UART_DEFAULT_CONFIG_IRQ_PRIORITY) +#undef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY UART_DEFAULT_CONFIG_IRQ_PRIORITY +#undef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY UART_DEFAULT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(UART_CONFIG_LOG_ENABLED) +#undef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED UART_CONFIG_LOG_ENABLED +#undef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED UART_CONFIG_LOG_ENABLED +#endif +#if defined(UART_CONFIG_LOG_LEVEL) +#undef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL UART_CONFIG_LOG_LEVEL +#undef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL UART_CONFIG_LOG_LEVEL +#endif +#if defined(UART_CONFIG_INFO_COLOR) +#undef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR UART_CONFIG_INFO_COLOR +#undef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR UART_CONFIG_INFO_COLOR +#endif +#if defined(UART_CONFIG_DEBUG_COLOR) +#undef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR UART_CONFIG_DEBUG_COLOR +#undef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR UART_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(UART_ENABLED) + +//------------------------------------------------------------------------------ +// WDT + +#if defined(WDT_ENABLED) + +#undef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED WDT_ENABLED + +#if defined(WDT_CONFIG_BEHAVIOUR) +#undef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR WDT_CONFIG_BEHAVIOUR +#endif +#if defined(WDT_CONFIG_RELOAD_VALUE) +#undef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE WDT_CONFIG_RELOAD_VALUE +#endif +#if defined(WDT_CONFIG_IRQ_PRIORITY) +#undef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY WDT_CONFIG_IRQ_PRIORITY +#endif + +#if defined(WDT_CONFIG_LOG_ENABLED) +#undef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED WDT_CONFIG_LOG_ENABLED +#endif +#if defined(WDT_CONFIG_LOG_LEVEL) +#undef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL WDT_CONFIG_LOG_LEVEL +#endif +#if defined(WDT_CONFIG_INFO_COLOR) +#undef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR WDT_CONFIG_INFO_COLOR +#endif +#if defined(WDT_CONFIG_DEBUG_COLOR) +#undef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR WDT_CONFIG_DEBUG_COLOR +#endif + +#endif // defined(WDT_ENABLED) + +#endif // APPLY_OLD_CONFIG_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h new file mode 100644 index 0000000..13abfb6 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_gpiote.h @@ -0,0 +1,139 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#ifndef NRF_DRV_GPIOTE_H__ +#define NRF_DRV_GPIOTE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_drv_gpiote GPIOTE driver - legacy layer + * @{ + * @ingroup nrf_gpiote + * @brief Layer providing compatibility with the former API. + */ + +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_gpiote_in_config_t nrf_drv_gpiote_in_config_t; +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_gpiote_pin_t nrf_drv_gpiote_pin_t; +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_gpiote_out_config_t nrf_drv_gpiote_out_config_t; +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_gpiote_evt_handler_t nrf_drv_gpiote_evt_handler_t; + +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_IN_SENSE_LOTOHI NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_IN_SENSE_HITOLO NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_IN_SENSE_TOGGLE NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_OUT_SIMPLE NRFX_GPIOTE_CONFIG_OUT_SIMPLE +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_OUT_TASK_LOW NRFX_GPIOTE_CONFIG_OUT_TASK_LOW +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_OUT_TASK_HIGH NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH +/** @brief Macro for forwarding the new implementation. */ +#define GPIOTE_CONFIG_OUT_TASK_TOGGLE NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE + +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_init nrfx_gpiote_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_is_init nrfx_gpiote_is_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_uninit nrfx_gpiote_uninit +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_init nrfx_gpiote_out_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_uninit nrfx_gpiote_out_uninit +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_set nrfx_gpiote_out_set +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_clear nrfx_gpiote_out_clear +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_toggle nrfx_gpiote_out_toggle +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_task_enable nrfx_gpiote_out_task_enable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_task_disable nrfx_gpiote_out_task_disable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_task_addr_get nrfx_gpiote_out_task_addr_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_init nrfx_gpiote_in_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_uninit nrfx_gpiote_in_uninit +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_event_enable nrfx_gpiote_in_event_enable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_event_disable nrfx_gpiote_in_event_disable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_is_set nrfx_gpiote_in_is_set +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_in_event_addr_get nrfx_gpiote_in_event_addr_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_set_task_addr_get nrfx_gpiote_set_task_addr_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_clr_task_addr_get nrfx_gpiote_clr_task_addr_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_task_force nrfx_gpiote_out_task_force +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_out_task_trigger nrfx_gpiote_out_task_trigger +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_set_task_trigger nrfx_gpiote_set_task_trigger +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_gpiote_clr_task_trigger nrfx_gpiote_clr_task_trigger + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif //NRF_DRV_GPIOTE_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.c b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.c new file mode 100644 index 0000000..35c3f1c --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.c @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nrf_drv_spi.h" + +#ifdef SPIM_PRESENT +#define INSTANCE_COUNT SPIM_COUNT +#else +#define INSTANCE_COUNT SPI_COUNT +#endif + +static nrf_drv_spi_evt_handler_t m_handlers[INSTANCE_COUNT]; +static void * m_contexts[INSTANCE_COUNT]; + +#ifdef SPIM_PRESENT +static void spim_evt_handler(nrfx_spim_evt_t const * p_event, + void * p_context) +{ + uint32_t inst_idx = (uint32_t)p_context; + nrf_drv_spi_evt_t const event = + { + .type = (nrf_drv_spi_evt_type_t)p_event->type, + .data = + { + .done = + { + .p_tx_buffer = p_event->xfer_desc.p_tx_buffer, + .tx_length = p_event->xfer_desc.tx_length, + .p_rx_buffer = p_event->xfer_desc.p_rx_buffer, + .rx_length = p_event->xfer_desc.rx_length, + } + } + }; + m_handlers[inst_idx](&event, m_contexts[inst_idx]); +} +#endif // SPIM_PRESENT + +#ifdef SPI_PRESENT +static void spi_evt_handler(nrfx_spi_evt_t const * p_event, + void * p_context) +{ + uint32_t inst_idx = (uint32_t)p_context; + nrf_drv_spi_evt_t const event = + { + .type = (nrf_drv_spi_evt_type_t)p_event->type, + .data = + { + .done = + { + .p_tx_buffer = p_event->xfer_desc.p_tx_buffer, + .tx_length = p_event->xfer_desc.tx_length, + .p_rx_buffer = p_event->xfer_desc.p_rx_buffer, + .rx_length = p_event->xfer_desc.rx_length, + } + } + }; + m_handlers[inst_idx](&event, m_contexts[inst_idx]); +} +#endif // SPI_PRESENT + +ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance, + nrf_drv_spi_config_t const * p_config, + nrf_drv_spi_evt_handler_t handler, + void * p_context) +{ + uint32_t inst_idx = p_instance->inst_idx; + m_handlers[inst_idx] = handler; + m_contexts[inst_idx] = p_context; + + ret_code_t result = 0; + if (NRF_DRV_SPI_USE_SPIM) + { +#ifdef SPIM_PRESENT + nrfx_spim_config_t config_spim = NRFX_SPIM_DEFAULT_CONFIG; + config_spim.sck_pin = p_config->sck_pin; + config_spim.mosi_pin = p_config->mosi_pin; + config_spim.miso_pin = p_config->miso_pin; + config_spim.ss_pin = p_config->ss_pin; + config_spim.irq_priority = p_config->irq_priority; + config_spim.orc = p_config->orc; + config_spim.frequency = (nrf_spim_frequency_t)p_config->frequency; + config_spim.mode = (nrf_spim_mode_t)p_config->mode; + config_spim.bit_order = (nrf_spim_bit_order_t)p_config->bit_order; + result = nrfx_spim_init(&p_instance->u.spim, + &config_spim, + handler ? spim_evt_handler : NULL, + (void *)inst_idx); +#endif + } + else if (NRF_DRV_SPI_USE_SPI) + { + result = nrfx_spi_init(&p_instance->u.spi, + (nrfx_spi_config_t const *)p_config, + handler ? spi_evt_handler : NULL, + (void *)inst_idx); + } + return result; +} diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.h b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.h new file mode 100644 index 0000000..3495a21 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_spi.h @@ -0,0 +1,615 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_SPI_H__ +#define NRF_DRV_SPI_H__ + +#include +#ifdef SPIM_PRESENT + #include +#else + // Compilers (at least the smart ones) will remove the SPIM related code + // (blocks starting with "if (NRF_DRV_SPI_USE_SPIM)") when it is not used, + // but to perform the compilation they need the following definitions. + #define nrfx_spim_init(...) 0 + #define nrfx_spim_uninit(...) + #define nrfx_spim_start_task_get(...) 0 + #define nrfx_spim_end_event_get(...) 0 + #define nrfx_spim_abort(...) +#endif + +#ifdef SPI_PRESENT + #include +#else + // Compilers (at least the smart ones) will remove the SPI related code + // (blocks starting with "if (NRF_DRV_SPI_USE_SPI)") when it is not used, + // but to perform the compilation they need the following definitions. + #define nrfx_spi_init(...) 0 + #define nrfx_spi_uninit(...) + #define nrfx_spi_start_task_get(...) 0 + #define nrfx_spi_end_event_get(...) 0 + #define nrfx_spi_abort(...) + + // This part is for old modules that use directly SPI HAL definitions + // (to make them compilable for chips that have only SPIM). + #define NRF_SPI_FREQ_125K NRF_SPIM_FREQ_125K + #define NRF_SPI_FREQ_250K NRF_SPIM_FREQ_250K + #define NRF_SPI_FREQ_500K NRF_SPIM_FREQ_500K + #define NRF_SPI_FREQ_1M NRF_SPIM_FREQ_1M + #define NRF_SPI_FREQ_2M NRF_SPIM_FREQ_2M + #define NRF_SPI_FREQ_4M NRF_SPIM_FREQ_4M + #define NRF_SPI_FREQ_8M NRF_SPIM_FREQ_8M + #define NRF_SPI_MODE_0 NRF_SPIM_MODE_0 + #define NRF_SPI_MODE_1 NRF_SPIM_MODE_1 + #define NRF_SPI_MODE_2 NRF_SPIM_MODE_2 + #define NRF_SPI_MODE_3 NRF_SPIM_MODE_3 + #define NRF_SPI_BIT_ORDER_MSB_FIRST NRF_SPIM_BIT_ORDER_MSB_FIRST + #define NRF_SPI_BIT_ORDER_LSB_FIRST NRF_SPIM_BIT_ORDER_LSB_FIRST +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_drv_spi SPI master driver + * @{ + * @ingroup nrf_spi + * @brief Layer providing compatibility with the former API. + */ + +/** + * @brief SPI master driver instance data structure. + */ +typedef struct +{ + uint8_t inst_idx; + union + { +#ifdef SPIM_PRESENT + nrfx_spim_t spim; +#endif +#ifdef SPI_PRESENT + nrfx_spi_t spi; +#endif + } u; + bool use_easy_dma; +} nrf_drv_spi_t; + +/** + * @brief Macro for creating an SPI master driver instance. + */ +#define NRF_DRV_SPI_INSTANCE(id) NRF_DRV_SPI_INSTANCE_(id) +#define NRF_DRV_SPI_INSTANCE_(id) NRF_DRV_SPI_INSTANCE_ ## id +#if NRFX_CHECK(NRFX_SPIM0_ENABLED) + #define NRF_DRV_SPI_INSTANCE_0 \ + { 0, { .spim = NRFX_SPIM_INSTANCE(0) }, true } +#elif NRFX_CHECK(NRFX_SPI0_ENABLED) + #define NRF_DRV_SPI_INSTANCE_0 \ + { 0, { .spi = NRFX_SPI_INSTANCE(0) }, false } +#endif +#if NRFX_CHECK(NRFX_SPIM1_ENABLED) + #define NRF_DRV_SPI_INSTANCE_1 \ + { 1, { .spim = NRFX_SPIM_INSTANCE(1) }, true } +#elif NRFX_CHECK(NRFX_SPI1_ENABLED) + #define NRF_DRV_SPI_INSTANCE_1 \ + { 1, { .spi = NRFX_SPI_INSTANCE(1) }, false } +#endif +#if NRFX_CHECK(NRFX_SPIM2_ENABLED) + #define NRF_DRV_SPI_INSTANCE_2 \ + { 2, { .spim = NRFX_SPIM_INSTANCE(2) }, true } +#elif NRFX_CHECK(NRFX_SPI2_ENABLED) + #define NRF_DRV_SPI_INSTANCE_2 \ + { 2, { .spi = NRFX_SPI_INSTANCE(2) }, false } +#endif + +/** + * @brief This value can be provided instead of a pin number for signals MOSI, + * MISO, and Slave Select to specify that the given signal is not used and + * therefore does not need to be connected to a pin. + */ +#define NRF_DRV_SPI_PIN_NOT_USED 0xFF + +/** + * @brief SPI data rates. + */ +typedef enum +{ + NRF_DRV_SPI_FREQ_125K = NRF_SPI_FREQ_125K, ///< 125 kbps. + NRF_DRV_SPI_FREQ_250K = NRF_SPI_FREQ_250K, ///< 250 kbps. + NRF_DRV_SPI_FREQ_500K = NRF_SPI_FREQ_500K, ///< 500 kbps. + NRF_DRV_SPI_FREQ_1M = NRF_SPI_FREQ_1M, ///< 1 Mbps. + NRF_DRV_SPI_FREQ_2M = NRF_SPI_FREQ_2M, ///< 2 Mbps. + NRF_DRV_SPI_FREQ_4M = NRF_SPI_FREQ_4M, ///< 4 Mbps. + NRF_DRV_SPI_FREQ_8M = NRF_SPI_FREQ_8M ///< 8 Mbps. +} nrf_drv_spi_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_DRV_SPI_MODE_0 = NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_DRV_SPI_MODE_1 = NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_DRV_SPI_MODE_2 = NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_DRV_SPI_MODE_3 = NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_drv_spi_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_DRV_SPI_BIT_ORDER_MSB_FIRST = NRF_SPI_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first. + NRF_DRV_SPI_BIT_ORDER_LSB_FIRST = NRF_SPI_BIT_ORDER_LSB_FIRST ///< Least significant bit shifted out first. +} nrf_drv_spi_bit_order_t; + +/** + * @brief SPI master driver instance configuration structure. + */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED + * if this signal is not needed. The driver + * supports only active low for this signal. + * If the signal should be active high, + * it must be controlled externally. */ + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Over-run character. + /**< This character is used when all bytes from the TX buffer are sent, + but the transfer continues due to RX. */ + nrf_drv_spi_frequency_t frequency; ///< SPI frequency. + nrf_drv_spi_mode_t mode; ///< SPI mode. + nrf_drv_spi_bit_order_t bit_order; ///< SPI bit order. +} nrf_drv_spi_config_t; + +/** + * @brief SPI master instance default configuration. + */ +#define NRF_DRV_SPI_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRF_DRV_SPI_PIN_NOT_USED, \ + .mosi_pin = NRF_DRV_SPI_PIN_NOT_USED, \ + .miso_pin = NRF_DRV_SPI_PIN_NOT_USED, \ + .ss_pin = NRF_DRV_SPI_PIN_NOT_USED, \ + .irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .orc = 0xFF, \ + .frequency = NRF_DRV_SPI_FREQ_4M, \ + .mode = NRF_DRV_SPI_MODE_0, \ + .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST, \ +} + +#define NRF_DRV_SPI_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ +#define NRF_DRV_SPI_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ +#define NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ +#define NRF_DRV_SPI_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ +#define NRF_DRV_SPI_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ + +/** + * @brief Single transfer descriptor structure. + */ +typedef struct +{ + uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. + uint8_t tx_length; ///< TX buffer length. + uint8_t * p_rx_buffer; ///< Pointer to RX buffer. + uint8_t rx_length; ///< RX buffer length. +}nrf_drv_spi_xfer_desc_t; + +/** + * @brief Macro for setting up single transfer descriptor. + * + * This macro is for internal use only. + */ +#define NRF_DRV_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ + { \ + .p_tx_buffer = (uint8_t const *)(p_tx), \ + .tx_length = (tx_len), \ + .p_rx_buffer = (p_rx), \ + .rx_length = (rx_len), \ + } + +/** + * @brief Macro for setting duplex TX RX transfer. + */ +#define NRF_DRV_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ + NRF_DRV_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) + +/** + * @brief Macro for setting TX transfer. + */ +#define NRF_DRV_SPI_XFER_TX(p_buf, length) \ + NRF_DRV_SPI_SINGLE_XFER(p_buf, length, NULL, 0) + +/** + * @brief Macro for setting RX transfer. + */ +#define NRF_DRV_SPI_XFER_RX(p_buf, length) \ + NRF_DRV_SPI_SINGLE_XFER(NULL, 0, p_buf, length) + +/** + * @brief SPI master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRF_DRV_SPI_EVENT_DONE, ///< Transfer done. +} nrf_drv_spi_evt_type_t; + +typedef struct +{ + nrf_drv_spi_evt_type_t type; ///< Event type. + union + { + nrf_drv_spi_xfer_desc_t done; ///< Event data for DONE event. + } data; +} nrf_drv_spi_evt_t; + +/** + * @brief SPI master driver event handler type. + */ +typedef void (* nrf_drv_spi_evt_handler_t)(nrf_drv_spi_evt_t const * p_event, + void * p_context); + + +/** + * @brief Function for initializing the SPI master driver instance. + * + * This function configures and enables the specified peripheral. + * + * @note MISO pin has pull down enabled. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with the initial configuration. + * + * @param handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param p_context Context passed to event handler. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRF_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED + * is set to a value other than zero. + */ +ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance, + nrf_drv_spi_config_t const * p_config, + nrf_drv_spi_evt_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI master driver instance. + * + * @note Configuration of pins is kept. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance); + +/** + * @brief Function for starting the SPI data transfer. + * + * If an event handler was provided in the @ref nrf_drv_spi_init call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, which means that this function + * returns when the transfer is finished. + * + * @note Peripherals using EasyDMA (for example, SPIM) require the transfer buffers + * to be placed in the Data RAM region. If they are not and an SPIM instance is + * used, this function will fail with the error code NRF_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_tx_buffer Pointer to the transmit buffer. Can be NULL + * if there is nothing to send. + * @param tx_buffer_length Length of the transmit buffer. + * @param[in] p_rx_buffer Pointer to the receive buffer. Can be NULL + * if there is nothing to receive. + * @param rx_buffer_length Length of the receive buffer. + * + * @retval NRF_SUCCESS If the operation was successful. + * @retval NRF_ERROR_BUSY If a previously started transfer has not finished + * yet. + * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +__STATIC_INLINE +ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance, + uint8_t const * p_tx_buffer, + uint8_t tx_buffer_length, + uint8_t * p_rx_buffer, + uint8_t rx_buffer_length); + +/** + * @brief Function for starting the SPI data transfer with additional option flags. + * + * Function enables customizing the transfer by using option flags. + * + * Additional options are provided using the flags parameter: + * + * - @ref NRF_DRV_SPI_FLAG_TX_POSTINC and @ref NRF_DRV_SPI_FLAG_RX_POSTINC: + * Post-incrementation of buffer addresses. Supported only by SPIM. + * - @ref NRF_DRV_SPI_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this + * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use + * @ref nrf_drv_spi_start_task_get to get the address of the start task. + * - @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer + * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM. + * If @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into + * busy state, so you must ensure that the next transfers are set up when SPIM is not active. + * @ref nrf_drv_spi_end_event_get function can be used to detect end of transfer. Option can be used + * together with @ref NRF_DRV_SPI_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers + * without interruptions. + * - @ref NRF_DRV_SPI_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set + * up a number of transfers that will be triggered externally (for example by PPI). An example is + * a TXRX transfer with the options @ref NRF_DRV_SPI_FLAG_RX_POSTINC, + * @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_SPI_FLAG_REPEATED_XFER. After the + * transfer is set up, a set of transfers can be triggered by PPI that will read, for example, + * the same register of an external component and put it into a RAM buffer without any interrupts. + * @ref nrf_drv_spi_end_event_get can be used to get the address of the END event, which can be + * used to count the number of transfers. If @ref NRF_DRV_SPI_FLAG_REPEATED_XFER is used, + * the driver does not set the instance into busy state, so you must ensure that the next + * transfers are set up when SPIM is not active. Supported only by SPIM. + * @note Function is intended to be used only in non-blocking mode. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * + * @retval NRF_SUCCESS If the procedure was successful. + * @retval NRF_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +__STATIC_INLINE +ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t const * const p_instance, + nrf_drv_spi_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +/** + * @brief Function for returning the address of a SPIM start task. + * + * This function should be used if @ref nrf_drv_spi_xfer was called with the flag @ref NRF_DRV_SPI_FLAG_HOLD_XFER. + * In that case, the transfer is not started by the driver, but it must be started externally by PPI. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Start task address. + */ +__STATIC_INLINE +uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance); + +/** + * @brief Function for returning the address of a END SPIM event. + * + * A END event can be used to detect the end of a transfer if the @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER + * option is used. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return END event address. + */ +__STATIC_INLINE +uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance); + +/** + * @brief Function for aborting ongoing transfer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if defined(SPI_PRESENT) && !defined(SPIM_PRESENT) +#define NRF_DRV_SPI_WITH_SPI +#elif !defined(SPI_PRESENT) && defined(SPIM_PRESENT) +#define NRF_DRV_SPI_WITH_SPIM +#else +#if (NRFX_CHECK(SPI0_ENABLED) && NRFX_CHECK(SPI0_USE_EASY_DMA)) || \ + (NRFX_CHECK(SPI1_ENABLED) && NRFX_CHECK(SPI1_USE_EASY_DMA)) || \ + (NRFX_CHECK(SPI2_ENABLED) && NRFX_CHECK(SPI2_USE_EASY_DMA)) + #define NRF_DRV_SPI_WITH_SPIM +#endif +#if (NRFX_CHECK(SPI0_ENABLED) && !NRFX_CHECK(SPI0_USE_EASY_DMA)) || \ + (NRFX_CHECK(SPI1_ENABLED) && !NRFX_CHECK(SPI1_USE_EASY_DMA)) || \ + (NRFX_CHECK(SPI2_ENABLED) && !NRFX_CHECK(SPI2_USE_EASY_DMA)) + #define NRF_DRV_SPI_WITH_SPI +#endif +#endif +#if defined(NRF_DRV_SPI_WITH_SPIM) && defined(NRF_DRV_SPI_WITH_SPI) + #define NRF_DRV_SPI_USE_SPIM (p_instance->use_easy_dma) +#elif defined(NRF_DRV_SPI_WITH_SPIM) + #define NRF_DRV_SPI_USE_SPIM true +#else + #define NRF_DRV_SPI_USE_SPIM false +#endif +#define NRF_DRV_SPI_USE_SPI (!NRF_DRV_SPI_USE_SPIM) + +__STATIC_INLINE +void nrf_drv_spi_uninit(nrf_drv_spi_t const * p_instance) +{ + if (NRF_DRV_SPI_USE_SPIM) + { + nrfx_spim_uninit(&p_instance->u.spim); + } + else if (NRF_DRV_SPI_USE_SPI) + { + nrfx_spi_uninit(&p_instance->u.spi); + } +} + +__STATIC_INLINE +ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance, + uint8_t const * p_tx_buffer, + uint8_t tx_buffer_length, + uint8_t * p_rx_buffer, + uint8_t rx_buffer_length) +{ + ret_code_t result = 0; + if (NRF_DRV_SPI_USE_SPIM) + { + #ifdef SPIM_PRESENT + nrfx_spim_xfer_desc_t const spim_xfer_desc = + { + .p_tx_buffer = p_tx_buffer, + .tx_length = tx_buffer_length, + .p_rx_buffer = p_rx_buffer, + .rx_length = rx_buffer_length, + }; + result = nrfx_spim_xfer(&p_instance->u.spim, &spim_xfer_desc, 0); + #endif + } + else if (NRF_DRV_SPI_USE_SPI) + { + #ifdef SPI_PRESENT + nrfx_spi_xfer_desc_t const spi_xfer_desc = + { + .p_tx_buffer = p_tx_buffer, + .tx_length = tx_buffer_length, + .p_rx_buffer = p_rx_buffer, + .rx_length = rx_buffer_length, + }; + result = nrfx_spi_xfer(&p_instance->u.spi, &spi_xfer_desc, 0); + #endif + } + return result; +} + +__STATIC_INLINE +ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t const * const p_instance, + nrf_drv_spi_xfer_desc_t const * p_xfer_desc, + uint32_t flags) +{ + ret_code_t result = 0; + if (NRF_DRV_SPI_USE_SPIM) + { + #ifdef SPIM_PRESENT + nrfx_spim_xfer_desc_t const spim_xfer_desc = + { + .p_tx_buffer = p_xfer_desc->p_tx_buffer, + .tx_length = p_xfer_desc->tx_length, + .p_rx_buffer = p_xfer_desc->p_rx_buffer, + .rx_length = p_xfer_desc->rx_length, + }; + result = nrfx_spim_xfer(&p_instance->u.spim, &spim_xfer_desc, flags); + #endif + } + else if (NRF_DRV_SPI_USE_SPI) + { + #ifdef SPI_PRESENT + nrfx_spi_xfer_desc_t const spi_xfer_desc = + { + .p_tx_buffer = p_xfer_desc->p_tx_buffer, + .tx_length = p_xfer_desc->tx_length, + .p_rx_buffer = p_xfer_desc->p_rx_buffer, + .rx_length = p_xfer_desc->rx_length, + }; + result = nrfx_spi_xfer(&p_instance->u.spi, &spi_xfer_desc, flags); + #endif + } + return result; +} + +__STATIC_INLINE +uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance) +{ + uint32_t result = 0; + if (NRF_DRV_SPI_USE_SPIM) + { + result = nrfx_spim_start_task_get(&p_instance->u.spim); + } + else if (NRF_DRV_SPI_USE_SPI) + { + NRFX_ASSERT(false); // not supported + result = 0; + } + return result; +} + +__STATIC_INLINE +uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance) +{ + uint32_t result = 0; + if (NRF_DRV_SPI_USE_SPIM) + { + result = nrfx_spim_end_event_get(&p_instance->u.spim); + } + else if (NRF_DRV_SPI_USE_SPI) + { + NRFX_ASSERT(false); // not supported + result = 0; + } + return result; +} + +__STATIC_INLINE +void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance) +{ + if (NRF_DRV_SPI_USE_SPIM) + { + nrfx_spim_abort(&p_instance->u.spim); + } + else if (NRF_DRV_SPI_USE_SPI) + { + nrfx_spi_abort(&p_instance->u.spi); + } +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_SPI_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_systick.h b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_systick.h new file mode 100644 index 0000000..11ed387 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_systick.h @@ -0,0 +1,80 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_SYSTICK_H__ +#define NRF_DRV_SYSTICK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_drv_systick ARM(R) SysTick driver - legacy layer + * @{ + * @ingroup nrf_systick + * + * @brief Layer providing compatibility with the former API. + */ + +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_systick_state_t nrf_drv_systick_state_t; + +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_init nrfx_systick_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_get nrfx_systick_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_test nrfx_systick_test +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_delay_ticks nrfx_systick_delay_ticks +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_delay_us nrfx_systick_delay_us +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_systick_delay_ms nrfx_systick_delay_ms + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_SYSTICK_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_timer.h b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_timer.h new file mode 100644 index 0000000..ed985bf --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_timer.h @@ -0,0 +1,121 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_TIMER_H__ +#define NRF_DRV_TIMER_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_drv_timer TIMER driver - legacy layer + * @{ + * @ingroup nrf_timer + * + * @brief Layer providing compatibility with the former API. + */ + +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_timer_t nrf_drv_timer_t; +/** @brief Type definition for forwarding the new implementation. */ +typedef nrfx_timer_config_t nrf_drv_timer_config_t; + +/** @brief Macro for forwarding the new implementation. */ +#define NRF_DRV_TIMER_INSTANCE NRFX_TIMER_INSTANCE +/** @brief Macro for forwarding the new implementation. */ +#define NRF_DRV_TIMER_DEFAULT_CONFIG NRFX_TIMER_DEFAULT_CONFIG + +/** @brief Macro for forwarding the new implementation. */ +#define nrf_timer_event_handler_t nrfx_timer_event_handler_t + +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_init nrfx_timer_init +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_uninit nrfx_timer_uninit +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_enable nrfx_timer_enable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_disable nrfx_timer_disable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_is_enabled nrfx_timer_is_enabled +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_pause nrfx_timer_pause +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_resume nrfx_timer_resume +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_clear nrfx_timer_clear +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_increment nrfx_timer_increment +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_capture nrfx_timer_capture +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_capture_get nrfx_timer_capture_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_compare nrfx_timer_compare +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_extended_compare nrfx_timer_extended_compare +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_us_to_ticks nrfx_timer_us_to_ticks +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_ms_to_ticks nrfx_timer_ms_to_ticks +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_compare_int_enable nrfx_timer_compare_int_enable +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_compare_int_disable nrfx_timer_compare_int_disable + +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_task_address_get nrfx_timer_task_address_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_capture_task_address_get nrfx_timer_capture_task_address_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_event_address_get nrfx_timer_event_address_get +/** @brief Macro for forwarding the new implementation. */ +#define nrf_drv_timer_compare_event_address_get nrfx_timer_compare_event_address_get + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_TIMER_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.c b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.c new file mode 100644 index 0000000..e32b69c --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.c @@ -0,0 +1,141 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nrf_drv_uart.h" + +#ifdef UARTE_PRESENT +#define INSTANCE_COUNT UARTE_COUNT +#else +#define INSTANCE_COUNT UART_COUNT +#endif + +static nrf_uart_event_handler_t m_handlers[INSTANCE_COUNT]; +static void * m_contexts[INSTANCE_COUNT]; + +#if defined(UARTE_PRESENT) && defined(UART_PRESENT) +uint8_t nrf_drv_uart_use_easy_dma[INSTANCE_COUNT]; +#endif + +#if defined(NRF_DRV_UART_WITH_UARTE) +static void uarte_evt_handler(nrfx_uarte_event_t const * p_event, + void * p_context) +{ + uint32_t inst_idx = (uint32_t)p_context; + nrf_drv_uart_event_t event = + { + .type = (nrf_drv_uart_evt_type_t)p_event->type, + .data = + { + .error = + { + .rxtx = + { + .p_data = p_event->data.error.rxtx.p_data, + .bytes = p_event->data.error.rxtx.bytes, + }, + .error_mask = p_event->data.error.error_mask, + } + } + }; + m_handlers[inst_idx](&event, m_contexts[inst_idx]); +} +#endif // defined(NRF_DRV_UART_WITH_UARTE) + +#if defined(NRF_DRV_UART_WITH_UART) +static void uart_evt_handler(nrfx_uart_event_t const * p_event, + void * p_context) +{ + uint32_t inst_idx = (uint32_t)p_context; + nrf_drv_uart_event_t event = + { + .type = (nrf_drv_uart_evt_type_t)p_event->type, + .data = + { + .error = + { + .rxtx = + { + .p_data = p_event->data.error.rxtx.p_data, + .bytes = p_event->data.error.rxtx.bytes, + }, + .error_mask = p_event->data.error.error_mask, + } + } + }; + m_handlers[inst_idx](&event, m_contexts[inst_idx]); +} +#endif // defined(NRF_DRV_UART_WITH_UART) + +ret_code_t nrf_drv_uart_init(nrf_drv_uart_t const * p_instance, + nrf_drv_uart_config_t const * p_config, + nrf_uart_event_handler_t event_handler) +{ + uint32_t inst_idx = p_instance->inst_idx; + m_handlers[inst_idx] = event_handler; + m_contexts[inst_idx] = p_config->p_context; + +#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) +#ifdef NRF52840_XXAA + if (inst_idx == 1) + { + ASSERT(p_config->use_easy_dma); + } +#endif + nrf_drv_uart_use_easy_dma[inst_idx] = p_config->use_easy_dma; +#endif + + nrf_drv_uart_config_t config = *p_config; + config.p_context = (void *)inst_idx; + + ret_code_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_init(&p_instance->uarte, + (nrfx_uarte_config_t const *)&config, + event_handler ? uarte_evt_handler : NULL); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_init(&p_instance->uart, + (nrfx_uart_config_t const *)&config, + event_handler ? uart_evt_handler : NULL); + } + return result; +} diff --git a/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.h b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.h new file mode 100644 index 0000000..d73ef6a --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/legacy/nrf_drv_uart.h @@ -0,0 +1,660 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_UART_H__ +#define NRF_DRV_UART_H__ + +#include + +#if defined(UARTE_PRESENT) && NRFX_CHECK(NRFX_UARTE_ENABLED) + #define NRF_DRV_UART_WITH_UARTE +#endif +#if defined(UART_PRESENT) && NRFX_CHECK(NRFX_UART_ENABLED) + #define NRF_DRV_UART_WITH_UART +#endif + +#if defined(NRF_DRV_UART_WITH_UARTE) + #include + #define NRF_DRV_UART_CREATE_UARTE(id) \ + .uarte = NRFX_UARTE_INSTANCE(id), +#else + // Compilers (at least the smart ones) will remove the UARTE related code + // (blocks starting with "if (NRF_DRV_UART_USE_UARTE)") when it is not used, + // but to perform the compilation they need the following definitions. + #define nrfx_uarte_init(...) 0 + #define nrfx_uarte_uninit(...) + #define nrfx_uarte_task_address_get(...) 0 + #define nrfx_uarte_event_address_get(...) 0 + #define nrfx_uarte_tx(...) 0 + #define nrfx_uarte_tx_in_progress(...) 0 + #define nrfx_uarte_tx_abort(...) + #define nrfx_uarte_rx(...) 0 + #define nrfx_uarte_rx_ready(...) 0 + #define nrfx_uarte_rx_abort(...) + #define nrfx_uarte_errorsrc_get(...) 0 + #define NRF_DRV_UART_CREATE_UARTE(id) +#endif + +#if defined(NRF_DRV_UART_WITH_UART) + #include + + #define NRF_DRV_UART_CREATE_UART(id) _NRF_DRV_UART_CREATE_UART(id) + #define _NRF_DRV_UART_CREATE_UART(id) NRF_DRV_UART_CREATE_UART_##id + #define NRF_DRV_UART_CREATE_UART_0 \ + .uart = NRFX_UART_INSTANCE(0), + #define NRF_DRV_UART_CREATE_UART_1 \ + .uart = { .p_reg = NULL }, + +#else + // Compilers (at least the smart ones) will remove the UART related code + // (blocks starting with "if (NRF_DRV_UART_USE_UART)") when it is not used, + // but to perform the compilation they need the following definitions. + #define nrfx_uart_init(...) 0 + #define nrfx_uart_uninit(...) + #define nrfx_uart_task_address_get(...) 0 + #define nrfx_uart_event_address_get(...) 0 + #define nrfx_uart_tx(...) 0 + #define nrfx_uart_tx_in_progress(...) 0 + #define nrfx_uart_tx_abort(...) + #define nrfx_uart_rx(...) 0 + #define nrfx_uart_rx_enable(...) + #define nrfx_uart_rx_disable(...) + #define nrfx_uart_rx_ready(...) 0 + #define nrfx_uart_rx_abort(...) + #define nrfx_uart_errorsrc_get(...) 0 + #define NRF_DRV_UART_CREATE_UART(id) + + // This part is for old modules that use directly UART HAL definitions + // (to make them compilable for chips that have only UARTE). + #define NRF_UART_BAUDRATE_1200 NRF_UARTE_BAUDRATE_1200 + #define NRF_UART_BAUDRATE_2400 NRF_UARTE_BAUDRATE_2400 + #define NRF_UART_BAUDRATE_4800 NRF_UARTE_BAUDRATE_4800 + #define NRF_UART_BAUDRATE_9600 NRF_UARTE_BAUDRATE_9600 + #define NRF_UART_BAUDRATE_14400 NRF_UARTE_BAUDRATE_14400 + #define NRF_UART_BAUDRATE_19200 NRF_UARTE_BAUDRATE_19200 + #define NRF_UART_BAUDRATE_28800 NRF_UARTE_BAUDRATE_28800 + #define NRF_UART_BAUDRATE_38400 NRF_UARTE_BAUDRATE_38400 + #define NRF_UART_BAUDRATE_57600 NRF_UARTE_BAUDRATE_57600 + #define NRF_UART_BAUDRATE_76800 NRF_UARTE_BAUDRATE_76800 + #define NRF_UART_BAUDRATE_115200 NRF_UARTE_BAUDRATE_115200 + #define NRF_UART_BAUDRATE_230400 NRF_UARTE_BAUDRATE_230400 + #define NRF_UART_BAUDRATE_250000 NRF_UARTE_BAUDRATE_250000 + #define NRF_UART_BAUDRATE_460800 NRF_UARTE_BAUDRATE_460800 + #define NRF_UART_BAUDRATE_921600 NRF_UARTE_BAUDRATE_921600 + #define NRF_UART_BAUDRATE_1000000 NRF_UARTE_BAUDRATE_1000000 + typedef nrf_uarte_baudrate_t nrf_uart_baudrate_t; + #define NRF_UART_ERROR_OVERRUN_MASK NRF_UARTE_ERROR_OVERRUN_MASK + #define NRF_UART_ERROR_PARITY_MASK NRF_UARTE_ERROR_PARITY_MASK + #define NRF_UART_ERROR_FRAMING_MASK NRF_UARTE_ERROR_PARITY_MASK + #define NRF_UART_ERROR_BREAK_MASK NRF_UARTE_ERROR_BREAK_MASK + typedef nrf_uarte_error_mask_t nrf_uart_error_mask_t; + #define NRF_UART_HWFC_DISABLED NRF_UARTE_HWFC_DISABLED + #define NRF_UART_HWFC_ENABLED NRF_UARTE_HWFC_ENABLED + typedef nrf_uarte_hwfc_t nrf_uart_hwfc_t; + #define NRF_UART_PARITY_EXCLUDED NRF_UARTE_PARITY_EXCLUDED + #define NRF_UART_PARITY_INCLUDED NRF_UARTE_PARITY_INCLUDED + typedef nrf_uarte_parity_t nrf_uart_parity_t; + typedef nrf_uarte_task_t nrf_uart_task_t; + typedef nrf_uarte_event_t nrf_uart_event_t; + #define NRF_UART_PSEL_DISCONNECTED NRF_UARTE_PSEL_DISCONNECTED + #define nrf_uart_event_clear(...) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_drv_uart UART driver - legacy layer + * @{ + * @ingroup nrf_uart + * @brief Layer providing compatibility with the former API. + */ + +/** + * @brief Structure for the UART driver instance. + */ +typedef struct +{ + uint8_t inst_idx; +#if defined(NRF_DRV_UART_WITH_UARTE) + nrfx_uarte_t uarte; +#endif +#if defined(NRF_DRV_UART_WITH_UART) + nrfx_uart_t uart; +#endif +} nrf_drv_uart_t; + +/** + * @brief Macro for creating an UART driver instance. + */ +#define NRF_DRV_UART_INSTANCE(id) \ +{ \ + .inst_idx = id, \ + NRF_DRV_UART_CREATE_UARTE(id) \ + NRF_DRV_UART_CREATE_UART(id) \ +} + +/** + * @brief Types of UART driver events. + */ +typedef enum +{ + NRF_DRV_UART_EVT_TX_DONE, ///< Requested TX transfer completed. + NRF_DRV_UART_EVT_RX_DONE, ///< Requested RX transfer completed. + NRF_DRV_UART_EVT_ERROR, ///< Error reported by UART peripheral. +} nrf_drv_uart_evt_type_t; + +/**@brief Structure for UART configuration. */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uart_hwfc_t hwfc; ///< Flow control configuration. + nrf_uart_parity_t parity; ///< Parity configuration. + nrf_uart_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) + bool use_easy_dma; +#endif +} nrf_drv_uart_config_t; + +#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) +extern uint8_t nrf_drv_uart_use_easy_dma[]; +#define NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA .use_easy_dma = true, +#else +#define NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA +#endif + +/**@brief UART default configuration. */ +#define NRF_DRV_UART_DEFAULT_CONFIG \ +{ \ + .pseltxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselrxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselcts = NRF_UART_PSEL_DISCONNECTED, \ + .pselrts = NRF_UART_PSEL_DISCONNECTED, \ + .p_context = NULL, \ + .hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_CONFIG_HWFC, \ + .parity = (nrf_uart_parity_t)UART_DEFAULT_CONFIG_PARITY, \ + .baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_CONFIG_BAUDRATE, \ + .interrupt_priority = UART_DEFAULT_CONFIG_IRQ_PRIORITY, \ + NRF_DRV_UART_DEFAULT_CONFIG_USE_EASY_DMA \ +} + +/**@brief Structure for UART transfer completion event. */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + uint8_t bytes; ///< Number of bytes transfered. +} nrf_drv_uart_xfer_evt_t; + +/**@brief Structure for UART error event. */ +typedef struct +{ + nrf_drv_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transfered. + uint32_t error_mask;///< Mask of error flags that generated the event. +} nrf_drv_uart_error_evt_t; + +/**@brief Structure for UART event. */ +typedef struct +{ + nrf_drv_uart_evt_type_t type; ///< Event type. + union + { + nrf_drv_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrf_drv_uart_error_evt_t error;///< Data provided for error event. + } data; +} nrf_drv_uart_event_t; + +/** + * @brief UART interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrf_uart_event_handler_t)(nrf_drv_uart_event_t * p_event, void * p_context); + +/** + * @brief Function for initializing the UART driver. + * + * This function configures and enables UART. After this function GPIO pins are controlled by UART. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Initial configuration. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. + */ +ret_code_t nrf_drv_uart_init(nrf_drv_uart_t const * p_instance, + nrf_drv_uart_config_t const * p_config, + nrf_uart_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UART driver. + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_uart_uninit(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for getting the address of a specific UART task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE +uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance, + nrf_uart_task_t task); + +/** + * @brief Function for getting the address of a specific UART event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE +uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance, + nrf_uart_event_t event); + +/** + * @brief Function for sending data over UART. + * + * If an event handler was provided in nrf_drv_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * + * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers + * are placed in the Data RAM region. If they are not and UARTE instance is + * used, this function will fail with error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If driver is already transferring. + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). + */ +__STATIC_INLINE +ret_code_t nrf_drv_uart_tx(nrf_drv_uart_t const * p_instance, + uint8_t const * const p_data, + uint8_t length); + +/** + * @brief Function for checking if UART is currently transmitting. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If UART is transmitting. + * @retval false If UART is not transmitting. + */ +__STATIC_INLINE +bool nrf_drv_uart_tx_in_progress(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRF_DRV_UART_EVT_TX_DONE event will be generated in non-blocking mode. Event will + * contain number of bytes sent until abort was called. If Easy DMA is not used event will be + * called from the function context. If Easy DMA is used it will be called from UART interrupt + * context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_uart_tx_abort(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for receiving data over UART. + * + * If an event handler was provided in the nrf_drv_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * @note Peripherals using EasyDMA (i.e. UARTE) require that the transfer buffers + * are placed in the Data RAM region. If they are not and UARTE driver instance + * is used, this function will fail with error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrf_drv_uart_rx_disable). + * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error. + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer (UARTE only). + */ +__STATIC_INLINE +ret_code_t nrf_drv_uart_rx(nrf_drv_uart_t const * p_instance, + uint8_t * p_data, + uint8_t length); + + + +/** + * @brief Function for testing the receiver state in blocking mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the receiver has at least one byte of data to get. + * @retval false If the receiver is empty. + */ +__STATIC_INLINE +bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for enabling the receiver. + * + * UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the + * UART receive function before the FIFO is filled, an overrun error will appear. Enabling the receiver + * without specifying an RX buffer is supported only in UART mode (without Easy DMA). The receiver must be + * explicitly closed by the user @sa nrf_drv_uart_rx_disable. This function asserts if the mode is wrong. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_uart_rx_enable(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for disabling the receiver. + * + * This function must be called to close the receiver after it has been explicitly enabled by + * @sa nrf_drv_uart_rx_enable. The feature is supported only in UART mode (without Easy DMA). The function + * asserts if mode is wrong. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_uart_rx_disable(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRF_DRV_UART_EVT_RX_DONE event will be generated in non-blocking mode. The event will + * contain the number of bytes received until abort was called. The event is called from UART interrupt + * context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE +void nrf_drv_uart_rx_abort(nrf_drv_uart_t const * p_instance); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is + * generated. Function clears error sources after reading. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval Mask of reported errors. + */ +__STATIC_INLINE +uint32_t nrf_drv_uart_errorsrc_get(nrf_drv_uart_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if defined(NRF_DRV_UART_WITH_UARTE) && defined(NRF_DRV_UART_WITH_UART) + #define NRF_DRV_UART_USE_UARTE (nrf_drv_uart_use_easy_dma[p_instance->inst_idx]) +#elif defined(NRF_DRV_UART_WITH_UARTE) + #define NRF_DRV_UART_USE_UARTE true +#else + #define NRF_DRV_UART_USE_UARTE false +#endif +#define NRF_DRV_UART_USE_UART (!NRF_DRV_UART_USE_UARTE) + +__STATIC_INLINE +void nrf_drv_uart_uninit(nrf_drv_uart_t const * p_instance) +{ + if (NRF_DRV_UART_USE_UARTE) + { + nrfx_uarte_uninit(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + nrfx_uart_uninit(&p_instance->uart); + } +} + +__STATIC_INLINE +uint32_t nrf_drv_uart_task_address_get(nrf_drv_uart_t const * p_instance, + nrf_uart_task_t task) +{ + uint32_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_task_address_get(&p_instance->uarte, + (nrf_uarte_task_t)task); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_task_address_get(&p_instance->uart, task); + } + return result; +} + +__STATIC_INLINE +uint32_t nrf_drv_uart_event_address_get(nrf_drv_uart_t const * p_instance, + nrf_uart_event_t event) +{ + uint32_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_event_address_get(&p_instance->uarte, + (nrf_uarte_event_t)event); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_event_address_get(&p_instance->uart, event); + } + return result; +} + +__STATIC_INLINE +ret_code_t nrf_drv_uart_tx(nrf_drv_uart_t const * p_instance, + uint8_t const * p_data, + uint8_t length) +{ + uint32_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_tx(&p_instance->uarte, + p_data, + length); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_tx(&p_instance->uart, + p_data, + length); + } + return result; +} + +__STATIC_INLINE +bool nrf_drv_uart_tx_in_progress(nrf_drv_uart_t const * p_instance) +{ + bool result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_tx_in_progress(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_tx_in_progress(&p_instance->uart); + } + return result; +} + +__STATIC_INLINE +void nrf_drv_uart_tx_abort(nrf_drv_uart_t const * p_instance) +{ + if (NRF_DRV_UART_USE_UARTE) + { + nrfx_uarte_tx_abort(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + nrfx_uart_tx_abort(&p_instance->uart); + } +} + +__STATIC_INLINE +ret_code_t nrf_drv_uart_rx(nrf_drv_uart_t const * p_instance, + uint8_t * p_data, + uint8_t length) +{ + uint32_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_rx(&p_instance->uarte, + p_data, + length); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_rx(&p_instance->uart, + p_data, + length); + } + return result; +} + +__STATIC_INLINE +bool nrf_drv_uart_rx_ready(nrf_drv_uart_t const * p_instance) +{ + bool result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_rx_ready(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + result = nrfx_uart_rx_ready(&p_instance->uart); + } + return result; +} + +__STATIC_INLINE +void nrf_drv_uart_rx_enable(nrf_drv_uart_t const * p_instance) +{ + if (NRF_DRV_UART_USE_UARTE) + { + NRFX_ASSERT(false); // not supported + } + else if (NRF_DRV_UART_USE_UART) + { + nrfx_uart_rx_enable(&p_instance->uart); + } +} + +__STATIC_INLINE +void nrf_drv_uart_rx_disable(nrf_drv_uart_t const * p_instance) +{ + if (NRF_DRV_UART_USE_UARTE) + { + NRFX_ASSERT(false); // not supported + } + else if (NRF_DRV_UART_USE_UART) + { + nrfx_uart_rx_disable(&p_instance->uart); + } +} + +__STATIC_INLINE +void nrf_drv_uart_rx_abort(nrf_drv_uart_t const * p_instance) +{ + if (NRF_DRV_UART_USE_UARTE) + { + nrfx_uarte_rx_abort(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + nrfx_uart_rx_abort(&p_instance->uart); + } +} + +__STATIC_INLINE +uint32_t nrf_drv_uart_errorsrc_get(nrf_drv_uart_t const * p_instance) +{ + uint32_t result = 0; + if (NRF_DRV_UART_USE_UARTE) + { + result = nrfx_uarte_errorsrc_get(&p_instance->uarte); + } + else if (NRF_DRV_UART_USE_UART) + { + nrf_uart_event_clear(p_instance->uart.p_reg, NRF_UART_EVENT_ERROR); + result = nrfx_uart_errorsrc_get(&p_instance->uart); + } + return result; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_UART_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/nrfx_glue.h b/HAL_Driver/sdk/integration/nrfx/nrfx_glue.h new file mode 100644 index 0000000..adea7d4 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/nrfx_glue.h @@ -0,0 +1,338 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +#include + +#include + +//------------------------------------------------------------------------------ + +#include +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_ASSERT(expression) ASSERT(expression) + +#include +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_STATIC_ASSERT(expression) STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +#ifdef NRF51 +#ifdef SOFTDEVICE_PRESENT +#define INTERRUPT_PRIORITY_IS_VALID(pri) (((pri) == 1) || ((pri) == 3)) +#else +#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 4) +#endif //SOFTDEVICE_PRESENT +#else +#ifdef SOFTDEVICE_PRESENT +#define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || \ + (((pri) > 4) && ((pri) < 8))) +#else +#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8) +#endif //SOFTDEVICE_PRESENT +#endif //NRF52 + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) \ + _NRFX_IRQ_PRIORITY_SET(irq_number, priority) +static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, + uint8_t priority) +{ + ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + NVIC_SetPriority(irq_number, priority); +} + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) +{ + NVIC_EnableIRQ(irq_number); +} + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) +{ + NVIC_SetPendingIRQ(irq_number); +} + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); +} + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) +{ + return (NVIC_GetPendingIRQ(irq_number) == 1); +} + +#include +#include +/** + * @brief Macro for entering into a critical section. + */ +#define NRFX_CRITICAL_SECTION_ENTER() CRITICAL_REGION_ENTER() + +/** + * @brief Macro for exiting from a critical section. + */ +#define NRFX_CRITICAL_SECTION_EXIT() CRITICAL_REGION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +#include + +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +#include + +/** + * @brief Atomic 32 bit unsigned type. + */ +#define nrfx_atomic_t nrfx_atomic_u32_t + +/** + * @brief Stores value to an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) + +/** + * @brief Performs logical OR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of OR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) + +/** + * @brief Performs logical AND operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of AND operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) + +/** + * @brief Performs logical XOR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of XOR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) + +/** + * @brief Performs logical ADD operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of ADD operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) + +/** + * @brief Performs logical SUB operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of SUB operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) + +//------------------------------------------------------------------------------ +#ifndef NRFX_CUSTOM_ERROR_CODES + +#include +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref ret_code_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 1 + +typedef ret_code_t nrfx_err_t; + +#define NRFX_SUCCESS NRF_SUCCESS +#define NRFX_ERROR_INTERNAL NRF_ERROR_INTERNAL +#define NRFX_ERROR_NO_MEM NRF_ERROR_NO_MEM +#define NRFX_ERROR_NOT_SUPPORTED NRF_ERROR_NOT_SUPPORTED +#define NRFX_ERROR_INVALID_PARAM NRF_ERROR_INVALID_PARAM +#define NRFX_ERROR_INVALID_STATE NRF_ERROR_INVALID_STATE +#define NRFX_ERROR_INVALID_LENGTH NRF_ERROR_INVALID_LENGTH +#define NRFX_ERROR_TIMEOUT NRF_ERROR_TIMEOUT +#define NRFX_ERROR_FORBIDDEN NRF_ERROR_FORBIDDEN +#define NRFX_ERROR_NULL NRF_ERROR_NULL +#define NRFX_ERROR_INVALID_ADDR NRF_ERROR_INVALID_ADDR +#define NRFX_ERROR_BUSY NRF_ERROR_BUSY +#define NRFX_ERROR_ALREADY_INITIALIZED NRF_ERROR_MODULE_ALREADY_INITIALIZED + +#define NRFX_ERROR_DRV_TWI_ERR_OVERRUN NRF_ERROR_DRV_TWI_ERR_OVERRUN +#define NRFX_ERROR_DRV_TWI_ERR_ANACK NRF_ERROR_DRV_TWI_ERR_ANACK +#define NRFX_ERROR_DRV_TWI_ERR_DNACK NRF_ERROR_DRV_TWI_ERR_DNACK + +#endif // NRFX_CUSTOM_ERROR_CODES +//------------------------------------------------------------------------------ + +#include +/** + * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. + */ +#define NRFX_PPI_CHANNELS_USED NRF_PPI_CHANNELS_USED + +/** + * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. + */ +#define NRFX_PPI_GROUPS_USED NRF_PPI_GROUPS_USED + +/** + * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. + */ +#define NRFX_SWI_USED NRF_SWI_USED + +/** + * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. + */ +#define NRFX_TIMERS_USED NRF_TIMERS_USED + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/HAL_Driver/sdk/integration/nrfx/nrfx_log.h b/HAL_Driver/sdk/integration/nrfx/nrfx_log.h new file mode 100644 index 0000000..2b1d611 --- /dev/null +++ b/HAL_Driver/sdk/integration/nrfx/nrfx_log.h @@ -0,0 +1,152 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(NRFX_LOG_MODULE) +#define NRF_LOG_MODULE_NAME NRFX_LOG_MODULE + +#define NRFX_CONFIG_ENTRY(x) CONCAT_3(NRFX_, NRFX_LOG_MODULE, x) + +#if NRFX_CHECK(NRFX_CONFIG_ENTRY(_CONFIG_LOG_ENABLED)) +#define NRF_LOG_LEVEL NRFX_CONFIG_ENTRY(_CONFIG_LOG_LEVEL) +#define NRF_LOG_INFO_COLOR NRFX_CONFIG_ENTRY(_CONFIG_INFO_COLOR) +#define NRF_LOG_DEBUG_COLOR NRFX_CONFIG_ENTRY(_CONFIG_DEBUG_COLOR) +#else +#define NRF_LOG_LEVEL 0 +#endif +#endif // defined(NRFX_LOG_MODULE) + +#include + +#if defined(NRFX_LOG_MODULE) +NRF_LOG_MODULE_REGISTER(); +#endif + +#define TEST_MACRO_INFO(...) NRF_LOG_INFO(__VA_ARGS__) +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + */ +#define NRFX_LOG_ERROR(...) NRF_LOG_ERROR(__VA_ARGS__) + +/** + * @brief Macro for logging a message with the severity level WARNING. + */ +#define NRFX_LOG_WARNING(...) NRF_LOG_WARNING(__VA_ARGS__) + +/** + * @brief Macro for logging a message with the severity level INFO. + */ +#define NRFX_LOG_INFO(...) TEST_MACRO_INFO(__VA_ARGS__) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + */ +#define NRFX_LOG_DEBUG(...) NRF_LOG_DEBUG(__VA_ARGS__) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) \ + NRF_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) \ + NRF_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) \ + NRF_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) \ + NRF_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) \ + NRF_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/HAL_Driver/sdk/license.txt b/HAL_Driver/sdk/license.txt new file mode 100644 index 0000000..03042d9 --- /dev/null +++ b/HAL_Driver/sdk/license.txt @@ -0,0 +1 @@ +For details on licenses, see .\documentation\licenses.txt or .\documentation\licenses.html. diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h new file mode 100644 index 0000000..51532c0 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_gpiote.h @@ -0,0 +1,423 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_GPIOTE_H__ +#define NRFX_GPIOTE_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_gpiote GPIOTE driver + * @{ + * @ingroup nrf_gpiote + * @brief GPIOTE peripheral driver. + */ + +/**@brief Input pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t sense; /**< Transition that triggers interrupt. */ + nrf_gpio_pin_pull_t pull; /**< Pulling mode. */ + bool is_watcher : 1; /**< True when the input pin is tracking an output pin. */ + bool hi_accuracy : 1; /**< True when high accuracy (IN_EVENT) is used. */ + bool skip_gpio_setup : 1; /**< Do not change GPIO configuration */ +} nrfx_gpiote_in_config_t; + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. + * @details Set hi_accu to true to use IN_EVENT.*/ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ + .skip_gpio_setup = true, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_HITOLO, \ + .skip_gpio_setup = true, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ + .skip_gpio_setup = true, \ + } + + +/**@brief Output pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t action; /**< Configuration of the pin task. */ + nrf_gpiote_outinit_t init_state; /**< Initial state of the output pin. */ + bool task_pin; /**< True if the pin is controlled by a GPIOTE task. */ +} nrfx_gpiote_out_config_t; + +/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */ +#define NRFX_GPIOTE_CONFIG_OUT_SIMPLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = false, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low. + * @details The task will clear the pin. Therefore, the pin is set initially. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_LOW \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high. + * @details The task will set the pin. Therefore, the pin is cleared initially. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state. + * @details The initial pin state must be provided. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/** @brief Pin. */ +typedef uint32_t nrfx_gpiote_pin_t; + +/** + * @brief Pin event handler prototype. + * + * @param pin Pin that triggered this event. + * @param action Action that lead to triggering this event. + */ +typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action); + +/** + * @brief Function for initializing the GPIOTE module. + * + * @details Only static configuration is supported to prevent the shared + * resource being customized by the initiator. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + */ +nrfx_err_t nrfx_gpiote_init(void); + +/** + * @brief Function for checking if the GPIOTE module is initialized. + * + * @details The GPIOTE module is a shared module. Therefore, you should check if + * the module is already initialized and skip initialization if it is. + * + * @retval true If the module is already initialized. + * @retval false If the module is not initialized. + */ +bool nrfx_gpiote_is_init(void); + +/** + * @brief Function for uninitializing the GPIOTE module. + */ +void nrfx_gpiote_uninit(void); + +/** + * @brief Function for initializing a GPIOTE output pin. + * @details The output pin can be controlled by the CPU or by PPI. The initial + * configuration specifies which mode is used. If PPI mode is used, the driver + * attempts to allocate one of the available GPIOTE channels. If no channel is + * available, an error is returned. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. + */ +nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_out_config_t const * p_config); + +/** + * @brief Function for uninitializing a GPIOTE output pin. + * @details The driver frees the GPIOTE channel if the output pin was using one. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for setting a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for clearing a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for toggling a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for enabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for disabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of OUT task. + */ +uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin); + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of SET task. + */ +uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of CLR task. + */ +uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for initializing a GPIOTE input pin. + * @details The input pin can act in two ways: + * - lower accuracy but low power (high frequency clock not needed) + * - higher accuracy (high frequency clock required) + * + * The initial configuration specifies which mode is used. + * If high-accuracy mode is used, the driver attempts to allocate one + * of the available GPIOTE channels. If no channel is + * available, an error is returned. + * In low accuracy mode SENSE feature is used. In this case only one active pin + * can be detected at a time. It can be worked around by setting all of the used + * low accuracy pins to toggle mode. + * For more information about SENSE functionality, refer to Product Specification. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * @param[in] evt_handler User function to be called when the configured transition occurs. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. + */ +nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_in_config_t const * p_config, + nrfx_gpiote_evt_handler_t evt_handler); + +/** + * @brief Function for uninitializing a GPIOTE input pin. + * @details The driver frees the GPIOTE channel if the input pin was using one. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for enabling sensing of a GPIOTE input pin. + * + * @details If the input pin is configured as high-accuracy pin, the function + * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism. + * Note that a PORT event is shared between multiple pins, therefore the + * interrupt is always enabled. + * + * @param[in] pin Pin. + * @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin. + */ +void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable); + +/** + * @brief Function for disabling a GPIOTE input pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for checking if a GPIOTE input pin is set. + * + * @param[in] pin Pin. + * + * @retval true If the input pin is set. + * @retval false If the input pin is not set. + */ +bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a GPIOTE input pin event. + * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned. + * + * @param[in] pin Pin. + */ +uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for forcing a specific state on the pin configured as task. + * + * @param[in] pin Pin. + * @param[in] state Pin state. + */ +void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state); + +/** + * @brief Function for triggering the task OUT manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin); + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for triggering the task SET manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for triggering the task CLR manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + + +void nrfx_gpiote_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GPIOTE_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spi.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spi.h new file mode 100644 index 0000000..8ae9388 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spi.h @@ -0,0 +1,273 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_SPI_H__ +#define NRFX_SPI_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_spi SPI driver + * @{ + * @ingroup nrf_spi + * @brief SPI peripheral driver. + */ + +/** + * @brief SPI master driver instance data structure. + */ +typedef struct +{ + NRF_SPI_Type * p_reg; ///< Pointer to a structure with SPI registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_spi_t; + +enum { +#if NRFX_CHECK(NRFX_SPI0_ENABLED) + NRFX_SPI0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPI1_ENABLED) + NRFX_SPI1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPI2_ENABLED) + NRFX_SPI2_INST_IDX, +#endif + NRFX_SPI_ENABLED_COUNT +}; + +/** + * @brief Macro for creating an SPI master driver instance. + */ +#define NRFX_SPI_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPI, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPI, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for signals MOSI, + * MISO, and Slave Select to specify that the given signal is not used and + * therefore does not need to be connected to a pin. + */ +#define NRFX_SPI_PIN_NOT_USED 0xFF + +/** + * @brief SPI master driver instance configuration structure. + */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. The driver + * supports only active low for this signal. + * If the signal should be active high, + * it must be controlled externally. */ + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Over-run character. + /**< This character is used when all bytes from the TX buffer are sent, + but the transfer continues due to RX. */ + nrf_spi_frequency_t frequency; ///< SPI frequency. + nrf_spi_mode_t mode; ///< SPI mode. + nrf_spi_bit_order_t bit_order; ///< SPI bit order. +} nrfx_spi_config_t; + +/** + * @brief SPI master instance default configuration. + */ +#define NRFX_SPI_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPI_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPI_PIN_NOT_USED, \ + .miso_pin = NRFX_SPI_PIN_NOT_USED, \ + .ss_pin = NRFX_SPI_PIN_NOT_USED, \ + .irq_priority = NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .orc = 0xFF, \ + .frequency = NRF_SPI_FREQ_4M, \ + .mode = NRF_SPI_MODE_0, \ + .bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \ +} + +/** + * @brief Single transfer descriptor structure. + */ +typedef struct +{ + uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. + size_t tx_length; ///< TX buffer length. + uint8_t * p_rx_buffer; ///< Pointer to RX buffer. + size_t rx_length; ///< RX buffer length. +} nrfx_spi_xfer_desc_t; + +/** + * @brief Macro for setting up single transfer descriptor. + * + * This macro is for internal use only. + */ +#define NRFX_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ + { \ + .p_tx_buffer = (uint8_t const *)(p_tx), \ + .tx_length = (tx_len), \ + .p_rx_buffer = (p_rx), \ + .rx_length = (rx_len), \ + } + +/** + * @brief Macro for setting duplex TX RX transfer. + */ +#define NRFX_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ + NRFX_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) + +/** + * @brief Macro for setting TX transfer. + */ +#define NRFX_SPI_XFER_TX(p_buf, length) \ + NRFX_SPI_SINGLE_XFER(p_buf, length, NULL, 0) + +/** + * @brief Macro for setting RX transfer. + */ +#define NRFX_SPI_XFER_RX(p_buf, length) \ + NRFX_SPI_SINGLE_XFER(NULL, 0, p_buf, length) + +/** + * @brief SPI master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRFX_SPI_EVENT_DONE, ///< Transfer done. +} nrfx_spi_evt_type_t; + +typedef struct +{ + nrfx_spi_evt_type_t type; ///< Event type. + nrfx_spi_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_spi_evt_t; + +/** + * @brief SPI master driver event handler type. + */ +typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the SPI master driver instance. + * + * This function configures and enables the specified peripheral. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @param handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, + nrfx_spi_config_t const * p_config, + nrfx_spi_evt_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI master driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spi_uninit(nrfx_spi_t const * const p_instance); + +/** + * @brief Function for starting the SPI data transfer. + * + * If an event handler was provided in the @ref nrfx_spi_init call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, which means that this function + * returns when the transfer is finished. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * Currently, no additional flags are available. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + */ +nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance, + nrfx_spi_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +/** + * @brief Function for aborting ongoing transfer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spi_abort(nrfx_spi_t const * p_instance); + + +void nrfx_spi_0_irq_handler(void); +void nrfx_spi_1_irq_handler(void); +void nrfx_spi_2_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SPI_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spim.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spim.h new file mode 100644 index 0000000..d721143 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_spim.h @@ -0,0 +1,396 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_SPIM_H__ +#define NRFX_SPIM_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_spim SPIM driver + * @{ + * @ingroup nrf_spim + * @brief SPIM peripheral driver. + */ + +/** + * @brief SPIM master driver instance data structure. + */ +typedef struct +{ + NRF_SPIM_Type * p_reg; ///< Pointer to a structure with SPIM registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_spim_t; + +enum { +#if NRFX_CHECK(NRFX_SPIM0_ENABLED) + NRFX_SPIM0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM1_ENABLED) + NRFX_SPIM1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM2_ENABLED) + NRFX_SPIM2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM3_ENABLED) + NRFX_SPIM3_INST_IDX, +#endif + NRFX_SPIM_ENABLED_COUNT +}; + +/** + * @brief Macro for creating an SPIM master driver instance. + */ +#define NRFX_SPIM_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPIM, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIM, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for signals MOSI, + * MISO, and Slave Select to specify that the given signal is not used and + * therefore does not need to be connected to a pin. + */ +#define NRFX_SPIM_PIN_NOT_USED 0xFF + +/** + * @brief SPIM master driver instance configuration structure. + */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + bool ss_active_high; ///< Polarity of the Slave Select pin during transmission. + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Over-run character. + /**< This character is used when all bytes from the TX buffer are sent, + but the transfer continues due to RX. */ + nrf_spim_frequency_t frequency; ///< SPI frequency. + nrf_spim_mode_t mode; ///< SPI mode. + nrf_spim_bit_order_t bit_order; ///< SPI bit order. +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) + uint8_t dcx_pin; ///< D/CX pin number (optional). + uint8_t rx_delay; ///< Sample delay for input serial data on MISO. + /**< The value specifies the delay, in number of 64 MHz clock cycles + * (15.625 ns), from the the sampling edge of SCK (leading edge for + * CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until + * the input serial data is sampled.*/ + bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin. + uint8_t ss_duration; ///< Slave Select duration before and after transmission. + /**< Minimum duration between the edge of CSN and the edge of SCK and minimum + * duration of CSN must stay inactive between transactions. + * The value is specified in number of 64 MHz clock cycles (15.625 ns). + * Supported only for hardware controlled Slave Select.*/ +#endif +} nrfx_spim_config_t; + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) +/** + * @brief SPIM master instance extended default configuration. + */ + #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ + .dcx_pin = NRFX_SPIM_PIN_NOT_USED, \ + .rx_delay = 0x02, \ + .ss_duration = 0x02, \ + .use_hw_ss = false, +#else + #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG +#endif + +/** + * @brief SPIM master instance default configuration. + */ +#define NRFX_SPIM_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPIM_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPIM_PIN_NOT_USED, \ + .miso_pin = NRFX_SPIM_PIN_NOT_USED, \ + .ss_pin = NRFX_SPIM_PIN_NOT_USED, \ + .ss_active_high = false, \ + .irq_priority = NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .orc = 0xFF, \ + .frequency = NRF_SPIM_FREQ_4M, \ + .mode = NRF_SPIM_MODE_0, \ + .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, \ + NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ +} + +#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ +#define NRFX_SPIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ +#define NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ +#define NRFX_SPIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ +#define NRFX_SPIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ + +/** + * @brief Single transfer descriptor structure. + */ +typedef struct +{ + uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. + size_t tx_length; ///< TX buffer length. + uint8_t * p_rx_buffer; ///< Pointer to RX buffer. + size_t rx_length; ///< RX buffer length. +} nrfx_spim_xfer_desc_t; + +/** + * @brief Macro for setting up single transfer descriptor. + * + * This macro is for internal use only. + */ +#define NRFX_SPIM_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ + { \ + .p_tx_buffer = (uint8_t const *)(p_tx), \ + .tx_length = (tx_len), \ + .p_rx_buffer = (p_rx), \ + .rx_length = (rx_len), \ + } + +/** + * @brief Macro for setting duplex TX RX transfer. + */ +#define NRFX_SPIM_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ + NRFX_SPIM_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) + +/** + * @brief Macro for setting TX transfer. + */ +#define NRFX_SPIM_XFER_TX(p_buf, length) \ + NRFX_SPIM_SINGLE_XFER(p_buf, length, NULL, 0) + +/** + * @brief Macro for setting RX transfer. + */ +#define NRFX_SPIM_XFER_RX(p_buf, length) \ + NRFX_SPIM_SINGLE_XFER(NULL, 0, p_buf, length) + +/** + * @brief SPIM master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRFX_SPIM_EVENT_DONE, ///< Transfer done. +} nrfx_spim_evt_type_t; + +typedef struct +{ + nrfx_spim_evt_type_t type; ///< Event type. + nrfx_spim_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_spim_evt_t; + +/** + * @brief SPIM master driver event handler type. + */ +typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the SPI master driver instance. + * + * This function configures and enables the specified peripheral. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @param handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + * @retval NRFX_ERROR_NOT_SUPPORTED If requested configuration is not supported + * by the SPIM instance. + */ +nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, + nrfx_spim_config_t const * p_config, + nrfx_spim_evt_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI master driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spim_uninit(nrfx_spim_t const * const p_instance); + +/** + * @brief Function for starting the SPI data transfer. + * + * Additional options are provided using the @c flags parameter: + * + * - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC: + * Post-incrementation of buffer addresses. Supported only by SPIM. + * - @ref NRFX_SPIM_FLAG_HOLD_XFER: Driver is not starting the transfer. Use this + * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use + * @ref nrfx_spim_start_task_get to get the address of the start task. + * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER: No user event handler after transfer + * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM. + * If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into + * busy state, so you must ensure that the next transfers are set up when SPIM is not active. + * @ref nrfx_spim_end_event_get function can be used to detect end of transfer. Option can be used + * together with @ref NRFX_SPIM_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers + * without interruptions. + * - @ref NRFX_SPIM_FLAG_REPEATED_XFER: Prepare for repeated transfers. You can set + * up a number of transfers that will be triggered externally (for example by PPI). An example is + * a TXRX transfer with the options @ref NRFX_SPIM_FLAG_RX_POSTINC, + * @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_SPIM_FLAG_REPEATED_XFER. After the + * transfer is set up, a set of transfers can be triggered by PPI that will read, for example, + * the same register of an external component and put it into a RAM buffer without any interrupts. + * @ref nrfx_spim_end_event_get can be used to get the address of the END event, which can be + * used to count the number of transfers. If @ref NRFX_SPIM_FLAG_REPEATED_XFER is used, + * the driver does not set the instance into busy state, so you must ensure that the next + * transfers are set up when SPIM is not active. Supported only by SPIM. + * + * @note Peripherals using EasyDMA (including SPIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for starting the SPI data transfer with DCX control. + * + * See @ref nrfx_spim_xfer for description of additional options of transfer + * provided by the @c flags parameter. + * + * @note Peripherals that use EasyDMA (including SPIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * @param cmd_length Length of the command bytes preceding the data + * bytes. The DCX line will be low during transmission + * of command bytes and high during transmission of data bytes. + * Maximum value available for dividing the transmitted bytes + * into command bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. + * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the + * @c cmd_length parameter causes all transmitted bytes + * to be marked as command bytes. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags, + uint8_t cmd_length); +#endif + +/** + * @brief Function for returning the address of a SPIM start task. + * + * This function should be used if @ref nrfx_spim_xfer was called with the flag @ref NRFX_SPIM_FLAG_HOLD_XFER. + * In that case, the transfer is not started by the driver, but it must be started externally by PPI. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Start task address. + */ +uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance); + +/** + * @brief Function for returning the address of a END SPIM event. + * + * The END event can be used to detect the end of a transfer + * if the @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER option is used. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return END event address. + */ +uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance); + +/** + * @brief Function for aborting ongoing transfer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spim_abort(nrfx_spim_t const * p_instance); + + +void nrfx_spim_0_irq_handler(void); +void nrfx_spim_1_irq_handler(void); +void nrfx_spim_2_irq_handler(void); +void nrfx_spim_3_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SPIM_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_systick.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_systick.h new file mode 100644 index 0000000..0195ac6 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_systick.h @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_SYSTICK_H__ +#define NRFX_SYSTICK_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_systick ARM(R) SysTick driver + * @{ + * @ingroup nrf_systick + * + * @brief ARM(R) SysTick driver. + * + * This driver configures ARM(R) SysTick as a free-running timer. + * This timer is used to generate delays and pool for timeouts. + * Only relatively short timeouts are supported. + * The SysTick works on 64MHz and is 24-bits wide. + * It means that it overflows around 4 times per second and around 250 ms + * would be the highest supported time in the library. + * But it would be really hard to detect if overflow was generated without + * using interrupts. For safety we would limit the maximum delay range by half. + */ + +/** + * @brief The value type that holds the SysTick state + * + * This variable is used to count the requested timeout. + * @sa nrfx_systick_get + */ +typedef struct { + uint32_t time; //!< Registered time value +} nrfx_systick_state_t; + +/** + * @brief Configure and start the timer + * + * Function configures SysTick as a free-running timer without interrupt. + */ +void nrfx_systick_init(void); + +/** + * @brief Get current SysTick state + * + * Function gets current state of the SysTick timer. + * It can be used to check time-out by @ref nrfx_systick_test. + * + * @param[out] p_state The pointer to the state variable to be filled + */ +void nrfx_systick_get(nrfx_systick_state_t * p_state); + +/** + * @brief Test if specified time is up in relation to remembered state + * + * @param[in] p_state Remembered state set by @ref nrfx_systick_get + * @param[in] us Required time-out. + * + * @retval true If current time is higher than specified state plus given time-out. + * @retval false If current time is lower than specified state plus given time-out + */ +bool nrfx_systick_test(nrfx_systick_state_t const * p_state, uint32_t us); + +/** + * @brief Blocking delay in CPU ticks + * + * @param[in] ticks Number of CPU ticks to delay. + */ +void nrfx_systick_delay_ticks(uint32_t ticks); + +/** + * @brief Blocking delay in us + * + * @param[in] us Number of microseconds to delay. + */ +void nrfx_systick_delay_us(uint32_t us); + +/** + * @brief Blocking delay in ms + * + * This delay function removes the limits of the highest possible delay value. + * + * @param[in] ms Number of milliseconds to delay. + */ +void nrfx_systick_delay_ms(uint32_t ms); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRFX_SYSTICK_H__ */ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_timer.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_timer.h new file mode 100644 index 0000000..195fc01 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_timer.h @@ -0,0 +1,413 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_TIMER_H__ +#define NRFX_TIMER_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_timer Timer driver + * @{ + * @ingroup nrf_timer + * @brief TIMER peripheral driver. + */ + +/** + * @brief Timer driver instance data structure. + */ +typedef struct +{ + NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers. + uint8_t instance_id; ///< Driver instance index. + uint8_t cc_channel_count; ///< Number of capture/compare channels. +} nrfx_timer_t; + +/** + * @brief Macro for creating a timer driver instance. + */ +#define NRFX_TIMER_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_TIMER, id), \ + .instance_id = NRFX_CONCAT_3(NRFX_TIMER, id, _INST_IDX), \ + .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \ +} + +enum { +#if NRFX_CHECK(NRFX_TIMER0_ENABLED) + NRFX_TIMER0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER1_ENABLED) + NRFX_TIMER1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER2_ENABLED) + NRFX_TIMER2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER3_ENABLED) + NRFX_TIMER3_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER4_ENABLED) + NRFX_TIMER4_INST_IDX, +#endif + NRFX_TIMER_ENABLED_COUNT +}; + +/** + * @brief Timer driver instance configuration structure. + */ +typedef struct +{ + nrf_timer_frequency_t frequency; ///< Frequency. + nrf_timer_mode_t mode; ///< Mode of operation. + nrf_timer_bit_width_t bit_width; ///< Bit width. + uint8_t interrupt_priority; ///< Interrupt priority. + void * p_context; ///< Context passed to interrupt handler. +} nrfx_timer_config_t; + +/** + * @brief Timer driver instance default configuration. + */ +#define NRFX_TIMER_DEFAULT_CONFIG \ +{ \ + .frequency = (nrf_timer_frequency_t)NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY,\ + .mode = (nrf_timer_mode_t)NRFX_TIMER_DEFAULT_CONFIG_MODE, \ + .bit_width = (nrf_timer_bit_width_t)NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH,\ + .interrupt_priority = NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .p_context = NULL \ +} + +/** + * @brief Timer driver event handler type. + * + * @param[in] event_type Timer event. + * @param[in] p_context General purpose parameter set during initialization of + * the timer. This parameter can be used to pass + * additional information to the handler function, for + * example, the timer ID. + */ +typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type, + void * p_context); + +/** + * @brief Function for initializing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] timer_event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. + */ +nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance, + nrfx_timer_config_t const * p_config, + nrfx_timer_event_handler_t timer_event_handler); + +/** + * @brief Function for uninitializing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_uninit(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for turning on the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_enable(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for turning off the timer. + * + * Note that the timer will allow to enter the lowest possible SYSTEM_ON state + * only after this function is called. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_disable(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for checking the timer state. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return True if timer is enabled, false otherwise. + */ +bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for pausing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_pause(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for resuming the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_resume(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for clearing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_clear(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for incrementing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_increment(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for returning the address of a specific timer task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] timer_task Timer task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_task_t timer_task); + +/** + * @brief Function for returning the address of a specific timer capture task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Capture channel number. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for returning the address of a specific timer event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] timer_event Timer event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_event_t timer_event); + +/** + * @brief Function for returning the address of a specific timer compare event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel number. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for capturing the timer value. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for returning the capture value from a specific channel. + * + * Use this function to read channel values when PPI is used for capturing. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for setting the timer channel in compare mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] enable_int Enable or disable the interrupt for the compare channel. + */ +void nrfx_timer_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + bool enable_int); + +/** + * @brief Function for setting the timer channel in extended compare mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] timer_short_mask Shortcut between the compare event on the channel + * and the timer task (STOP or CLEAR). + * @param[in] enable_int Enable or disable the interrupt for the compare + * channel. + */ +void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + nrf_timer_short_mask_t timer_short_mask, + bool enable_int); + +/** + * @brief Function for converting time in microseconds to timer ticks. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] time_us Time in microseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t time_us); + +/** + * @brief Function for converting time in milliseconds to timer ticks. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] time_ms Time in milliseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t time_ms); + +/** + * @brief Function for enabling timer compare interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel. + */ +void nrfx_timer_compare_int_enable(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for disabling timer compare interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel. + */ +void nrfx_timer_compare_int_disable(nrfx_timer_t const * const p_instance, + uint32_t channel); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_task_t timer_task) +{ + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task); +} + +__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, + nrf_timer_capture_task_get(channel)); +} + +__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_event_t timer_event) +{ + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event); +} + +__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, + nrf_timer_compare_event_get(channel)); +} + +__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel) +{ + return nrf_timer_cc_read(p_instance->p_reg, cc_channel); +} + +__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t timer_us) +{ + return nrf_timer_us_to_ticks(timer_us, nrf_timer_frequency_get(p_instance->p_reg)); +} + +__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t timer_ms) +{ + return nrf_timer_ms_to_ticks(timer_ms, nrf_timer_frequency_get(p_instance->p_reg)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_timer_0_irq_handler(void); +void nrfx_timer_1_irq_handler(void); +void nrfx_timer_2_irq_handler(void); +void nrfx_timer_3_irq_handler(void); +void nrfx_timer_4_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TIMER_H__ + diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uart.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uart.h new file mode 100644 index 0000000..e8b0486 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uart.h @@ -0,0 +1,376 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_UART_H__ +#define NRFX_UART_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_uart UART driver + * @{ + * @ingroup nrf_uart + * @brief UART peripheral driver. + */ + +/** + * @brief UART driver instance data structure. + */ +typedef struct +{ + NRF_UART_Type * p_reg; ///< Pointer to a structure with UART registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_uart_t; + +enum { +#if NRFX_CHECK(NRFX_UART0_ENABLED) + NRFX_UART0_INST_IDX, +#endif + NRFX_UART_ENABLED_COUNT +}; + +/** + * @brief Macro for creating a UART driver instance. + */ +#define NRFX_UART_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_UART, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_UART, id, _INST_IDX), \ +} + +/** + * @brief Types of UART driver events. + */ +typedef enum +{ + NRFX_UART_EVT_TX_DONE, ///< Requested TX transfer completed. + NRFX_UART_EVT_RX_DONE, ///< Requested RX transfer completed. + NRFX_UART_EVT_ERROR, ///< Error reported by UART peripheral. +} nrfx_uart_evt_type_t; + +/** + * @brief Structure for UART configuration. + */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uart_hwfc_t hwfc; ///< Flow control configuration. + nrf_uart_parity_t parity; ///< Parity configuration. + nrf_uart_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +} nrfx_uart_config_t; + +/** + * @brief UART default configuration. + */ +#define NRFX_UART_DEFAULT_CONFIG \ +{ \ + .pseltxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselrxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselcts = NRF_UART_PSEL_DISCONNECTED, \ + .pselrts = NRF_UART_PSEL_DISCONNECTED, \ + .p_context = NULL, \ + .hwfc = (nrf_uart_hwfc_t)NRFX_UART_DEFAULT_CONFIG_HWFC, \ + .parity = (nrf_uart_parity_t)NRFX_UART_DEFAULT_CONFIG_PARITY, \ + .baudrate = (nrf_uart_baudrate_t)NRFX_UART_DEFAULT_CONFIG_BAUDRATE, \ + .interrupt_priority = NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY, \ +} + +/** + * @brief Structure for UART transfer completion event. + */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + uint32_t bytes; ///< Number of bytes transfered. +} nrfx_uart_xfer_evt_t; + +/** + * @brief Structure for UART error event. + */ +typedef struct +{ + nrfx_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. + uint32_t error_mask; ///< Mask of error flags that generated the event. +} nrfx_uart_error_evt_t; + +/** + * @brief Structure for UART event. + */ +typedef struct +{ + nrfx_uart_evt_type_t type; ///< Event type. + union + { + nrfx_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrfx_uart_error_evt_t error; ///< Data provided for error event. + } data; +} nrfx_uart_event_t; + +/** + * @brief UART interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the UART driver. + * + * This function configures and enables UART. After this function GPIO pins are controlled by UART. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, + nrfx_uart_config_t const * p_config, + nrfx_uart_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UART driver. + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_uninit(nrfx_uart_t const * p_instance); + +/** + * @brief Function for getting the address of a specific UART task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, + nrf_uart_task_t task); + +/** + * @brief Function for getting the address of a specific UART event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, + nrf_uart_event_t event); + +/** + * @brief Function for sending data over UART. + * + * If an event handler was provided in nrfx_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt + * so there is no context switching inside the function. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If driver is already transferring. + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + */ +nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance, + uint8_t const * p_data, + size_t length); + +/** + * @brief Function for checking if UART is currently transmitting. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If UART is transmitting. + * @retval false If UART is not transmitting. + */ +bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes sent until abort was called. The event + * handler will be called from the function context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance); + +/** + * @brief Function for receiving data over UART. + * + * If an event handler was provided in the nrfx_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, meaning that this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * If this function is used without a previous call to @ref nrfx_uart_rx_enable, the reception + * will be stopped on error or when the supplied buffer fills up. In both cases, + * RX FIFO gets disabled. This means that, in case of error, the bytes that follow are lost. + * If this nrfx_uart_rx() function is used with the previous call to @ref nrfx_uart_rx_enable, + * the reception is stopped in case of error, but FIFO is still ongoing. The receiver is still + * working, so after handling the error, an immediate repeated call to this nrfx_uart_rx() + * function with fresh data buffer will re-establish reception. To disable the receiver, + * you must call @ref nrfx_uart_rx_disable explicitly. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. + * + * @retval NRFX_SUCCESS If reception is complete (in case of blocking mode) or it is + * successfully started (in case of non-blocking mode). + * @retval NRFX_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrfx_uart_rx_disable). + * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error. + */ +nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance, + uint8_t * p_data, + size_t length); + + + +/** + * @brief Function for testing the receiver state in blocking mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the receiver has at least one byte of data to get. + * @retval false If the receiver is empty. + */ +bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance); + +/** + * @brief Function for enabling the receiver. + * + * UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the + * UART receive function before the FIFO is filled, an overrun error will appear. The receiver must be + * explicitly closed by the user @sa nrfx_uart_rx_disable. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_enable(nrfx_uart_t const * p_instance); + +/** + * @brief Function for disabling the receiver. + * + * This function must be called to close the receiver after it has been explicitly enabled by + * @sa nrfx_uart_rx_enable. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes received until abort was called. The event + * handler will be called from the UART interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is + * generated. Function clears error sources after reading. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval Mask of reported errors. + */ +uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, + nrf_uart_task_t task) +{ + return nrf_uart_task_address_get(p_instance->p_reg, task); +} + +__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, + nrf_uart_event_t event) +{ + return nrf_uart_event_address_get(p_instance->p_reg, event); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_uart_0_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_UART_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uarte.h b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uarte.h new file mode 100644 index 0000000..758f2af --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/include/nrfx_uarte.h @@ -0,0 +1,371 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_UARTE_H__ +#define NRFX_UARTE_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_uarte UARTE driver + * @{ + * @ingroup nrf_uarte + * @brief UARTE peripheral driver. + */ + +/** + * @brief Structure for the UARTE driver instance. + */ +typedef struct +{ + NRF_UARTE_Type * p_reg; ///< Pointer to a structure with UARTE registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_uarte_t; + +enum { +#if NRFX_CHECK(NRFX_UARTE0_ENABLED) + NRFX_UARTE0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_UARTE1_ENABLED) + NRFX_UARTE1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_UARTE2_ENABLED) + NRFX_UARTE2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_UARTE3_ENABLED) + NRFX_UARTE3_INST_IDX, +#endif + NRFX_UARTE_ENABLED_COUNT +}; + +/** + * @brief Macro for creating a UARTE driver instance. + */ +#define NRFX_UARTE_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_UARTE, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_UARTE, id, _INST_IDX), \ +} + +/** + * @brief Types of UARTE driver events. + */ +typedef enum +{ + NRFX_UARTE_EVT_TX_DONE, ///< Requested TX transfer completed. + NRFX_UARTE_EVT_RX_DONE, ///< Requested RX transfer completed. + NRFX_UARTE_EVT_ERROR, ///< Error reported by UART peripheral. +} nrfx_uarte_evt_type_t; + +/** + * @brief Structure for UARTE configuration. + */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uarte_hwfc_t hwfc; ///< Flow control configuration. + nrf_uarte_parity_t parity; ///< Parity configuration. + nrf_uarte_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +} nrfx_uarte_config_t; + +/** + * @brief UARTE default configuration. + */ +#define NRFX_UARTE_DEFAULT_CONFIG \ +{ \ + .pseltxd = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselrxd = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselcts = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselrts = NRF_UARTE_PSEL_DISCONNECTED, \ + .p_context = NULL, \ + .hwfc = (nrf_uarte_hwfc_t)NRFX_UARTE_DEFAULT_CONFIG_HWFC, \ + .parity = (nrf_uarte_parity_t)NRFX_UARTE_DEFAULT_CONFIG_PARITY, \ + .baudrate = (nrf_uarte_baudrate_t)NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE, \ + .interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \ +} + +/** + * @brief Structure for UARTE transfer completion event. + */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + size_t bytes; ///< Number of bytes transfered. +} nrfx_uarte_xfer_evt_t; + +/** + * @brief Structure for UARTE error event. + */ +typedef struct +{ + nrfx_uarte_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. + uint32_t error_mask; ///< Mask of error flags that generated the event. +} nrfx_uarte_error_evt_t; + +/** + * @brief Structure for UARTE event. + */ +typedef struct +{ + nrfx_uarte_evt_type_t type; ///< Event type. + union + { + nrfx_uarte_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrfx_uarte_error_evt_t error; ///< Data provided for error event. + } data; +} nrfx_uarte_event_t; + +/** + * @brief UARTE interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the UARTE driver. + * + * This function configures and enables UARTE. After this function GPIO pins are controlled by UARTE. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, + nrfx_uarte_config_t const * p_config, + nrfx_uarte_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UARTE driver. + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for getting the address of a specific UARTE task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_task_t task); + +/** + * @brief Function for getting the address of a specific UARTE event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_event_t event); + +/** + * @brief Function for sending data over UARTE. + * + * If an event handler was provided in nrfx_uarte_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt + * so there is no context switching inside the function. + * + * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. Maximum possible length is + * dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If driver is already transferring. + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. + */ +nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance, + uint8_t const * p_data, + size_t length); + +/** + * @brief Function for checking if UARTE is currently transmitting. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If UARTE is transmitting. + * @retval false If UARTE is not transmitting. + */ +bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRFX_UARTE_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes sent until abort was called. The event + * handler will be called from UARTE interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for receiving data over UARTE. + * + * If an event handler was provided in the nrfx_uarte_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. Maximum possible length is + * dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + * @retval NRFX_ERROR_INTERNAL If UARTE peripheral reported an error. + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. + */ +nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance, + uint8_t * p_data, + size_t length); + + + +/** + * @brief Function for testing the receiver state in blocking mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the receiver has at least one byte of data to get. + * @retval false If the receiver is empty. + */ +bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRFX_UARTE_EVT_RX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes received until abort was called. The event + * handler will be called from UARTE interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uarte_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is + * generated. Function clears error sources after reading. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval Mask of reported errors. + */ +uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_task_t task) +{ + return nrf_uarte_task_address_get(p_instance->p_reg, task); +} + +__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_event_t event) +{ + return nrf_uarte_event_address_get(p_instance->p_reg, event); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_uarte_0_irq_handler(void); +void nrfx_uarte_1_irq_handler(void); +void nrfx_uarte_2_irq_handler(void); +void nrfx_uarte_3_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_UARTE_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_common.h b/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_common.h new file mode 100644 index 0000000..351b90f --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_common.h @@ -0,0 +1,337 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_COMMON_H__ +#define NRFX_COMMON_H__ + +#include +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_common Common module + * @{ + * @ingroup nrfx + * @brief Common module. + */ + +/** + * @brief Macro for checking if the specified identifier is defined and it has + * a non-zero value. + * + * Normally, preprocessors treat all undefined identifiers as having the value + * zero. However, some tools, like static code analyzers, may issue a warning + * when such identifier is evaluated. This macro gives the possibility to suppress + * such warnings only in places where this macro is used for evaluation, not in + * the whole analyzed code. + */ +#define NRFX_CHECK(module_enabled) (module_enabled) + +/** + * @brief Macro for concatenating two tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param p1 First token. + * @param p2 Second token. + * + * @return The two tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_3 + */ +#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2) +/** + * @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion + * in two steps. + */ +#define NRFX_CONCAT_2_(p1, p2) p1 ## p2 + +/** + * @brief Macro for concatenating three tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param p1 First token. + * @param p2 Second token. + * @param p3 Third token. + * + * @return The three tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_2 + */ +#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3) +/** + * @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion + * in two steps. + */ +#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3 + +/**@brief Macro for performing rounded integer division (as opposed to + * truncating the result). + * + * @param a Numerator. + * @param b Denominator. + * + * @return Rounded (integer) result of dividing @c a by @c b. + */ +#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) + +/**@brief Macro for performing integer division, making sure the result is rounded up. + * + * @details A typical use case for this macro is to compute the number of objects + * with size @c b required to hold @c a number of bytes. + * + * @param a Numerator. + * @param b Denominator. + * + * @return Integer result of dividing @c a by @c b, rounded up. + */ +#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1) + +/** + * @brief Macro for getting the number of elements in an array. + * + * @param array Name of the array. + * + * @return Array element count. + */ +#define NRFX_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) + +/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed + * the limit of the specified peripheral. + * + * @param peripheral Peripheral to check the lengths against. + * @param length1 First length to be checked. + * @param length2 Second length to be checked (pass 0 if not needed). + * + * @return + */ +#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \ + (((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \ + ((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE)))) + +/**@brief Macro for waiting until condition is met. + * + * @param[in] condition Condition to meet. + * @param[in] attempts Maximum number of condition checks. Must not be 0. + * @param[in] delay_us Delay between consecutive checks, in microseconds. + * @param[out] result Boolean variable to store the result of the wait process. + * Set to true if the condition is met or false otherwise. + */ +#define NRFX_WAIT_FOR(condition, attempts, delay_us, result) \ +do { \ + result = false; \ + uint32_t remaining_attempts = (attempts); \ + do { \ + if (condition) \ + { \ + result = true; \ + break; \ + } \ + NRFX_DELAY_US(delay_us); \ + } while (--remaining_attempts); \ +} while(0) + +/** + * @brief Macro for getting the ID number of the specified peripheral. + * + * For peripherals in Nordic SoCs, there is a direct relationship between their + * ID numbers and their base addresses. See the chapter "Peripheral interface" + * (section "Peripheral ID") in the Product Specification. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return ID number associated with the specified peripheral. + */ +#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12) + +/** + * @brief Macro for getting the interrupt number assigned to a specific + * peripheral. + * + * For peripherals in Nordic SoCs, the IRQ number assigned to a peripheral is + * equal to its ID number. See the chapter "Peripheral interface" (sections + * "Peripheral ID" and "Interrupts") in the Product Specification. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return Interrupt number associated with the specified peripheral. + */ +#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr) + +/** + * @brief IRQ handler type. + */ +typedef void (* nrfx_irq_handler_t)(void); + +/** + * @brief Driver state. + */ +typedef enum +{ + NRFX_DRV_STATE_UNINITIALIZED, ///< Uninitialized. + NRFX_DRV_STATE_INITIALIZED, ///< Initialized but powered off. + NRFX_DRV_STATE_POWERED_ON, ///< Initialized and powered on. +} nrfx_drv_state_t; + + +/** + * @brief Function for checking if an object is placed in the Data RAM region. + * + * Several peripherals (the ones using EasyDMA) require the transfer buffers + * to be placed in the Data RAM region. This function can be used to check if + * this condition is met. + * + * @param[in] p_object Pointer to an object whose location is to be checked. + * + * @retval true If the pointed object is located in the Data RAM region. + * @retval false Otherwise. + */ +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); + + +/** + * @brief Function for checking if an object is aligned to a 32-bit word + * + * Several peripherals (the ones using EasyDMA) require the transfer buffers + * to be aligned to a 32-bit word. This function can be used to check if + * this condition is met. + * + * @param[in] p_object Pointer to an object whose location is to be checked. + * + * @retval true if the pointed object is aligned to a 32-bit word. + * @retval false otherwise. + */ +__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object); + + +/** + * @brief Function for getting the interrupt number for a specific peripheral. + * + * @param[in] p_reg Peripheral base pointer. + * + * @return Interrupt number associated with the pointed peripheral. + */ +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); + +/** + * @brief Function for converting an INTEN register bit position to the + * corresponding event identifier. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + + * @param bit INTEN register bit position. + * + * @return Event identifier. + * + * @sa nrfx_event_to_bitpos + */ +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); + +/** + * @brief Function for converting an event identifier to the corresponding + * INTEN register bit position. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + * + * @param event Event identifier. + * + * @return INTEN register bit position. + * + * @sa nrfx_bitpos_to_event + */ +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) +{ + return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u); +} + +__STATIC_INLINE bool nrfx_is_word_aligned(void const * p_object) +{ + return ((((uint32_t)p_object) & 0x3u) == 0u); +} + +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) +{ + return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg); +} + +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) +{ + static const uint32_t event_reg_offset = 0x100u; + return event_reg_offset + (bit * sizeof(uint32_t)); +} + +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) +{ + static const uint32_t event_reg_offset = 0x100u; + return (event - event_reg_offset) / sizeof(uint32_t); +} + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_COMMON_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_errors.h b/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_errors.h new file mode 100644 index 0000000..a80bf36 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/nrfx_errors.h @@ -0,0 +1,82 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_ERRORS_H__ +#define NRFX_ERRORS_H__ + +#if !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +/** + * @defgroup nrfx_error_codes Global Error Codes + * @{ + * @ingroup nrfx + * + * @brief Global error codes definitions. + */ + +#define NRFX_ERROR_BASE_NUM 0x0BAD0000 +#define NRFX_ERROR_DRIVERS_BASE_NUM (NRFX_ERROR_BASE_NUM + 0x10000) + +/** @brief Enumerated type for error codes. */ +typedef enum { + NRFX_SUCCESS = (NRFX_ERROR_BASE_NUM + 0), ///< Operation performed successfully. + NRFX_ERROR_INTERNAL = (NRFX_ERROR_BASE_NUM + 1), ///< Internal error. + NRFX_ERROR_NO_MEM = (NRFX_ERROR_BASE_NUM + 2), ///< No memory for operation. + NRFX_ERROR_NOT_SUPPORTED = (NRFX_ERROR_BASE_NUM + 3), ///< Not supported. + NRFX_ERROR_INVALID_PARAM = (NRFX_ERROR_BASE_NUM + 4), ///< Invalid parameter. + NRFX_ERROR_INVALID_STATE = (NRFX_ERROR_BASE_NUM + 5), ///< Invalid state, operation disallowed in this state. + NRFX_ERROR_INVALID_LENGTH = (NRFX_ERROR_BASE_NUM + 6), ///< Invalid length. + NRFX_ERROR_TIMEOUT = (NRFX_ERROR_BASE_NUM + 7), ///< Operation timed out. + NRFX_ERROR_FORBIDDEN = (NRFX_ERROR_BASE_NUM + 8), ///< Operation is forbidden. + NRFX_ERROR_NULL = (NRFX_ERROR_BASE_NUM + 9), ///< Null pointer. + NRFX_ERROR_INVALID_ADDR = (NRFX_ERROR_BASE_NUM + 10), ///< Bad memory address. + NRFX_ERROR_BUSY = (NRFX_ERROR_BASE_NUM + 11), ///< Busy. + NRFX_ERROR_ALREADY_INITIALIZED = (NRFX_ERROR_BASE_NUM + 12), ///< Module already initialized. + + NRFX_ERROR_DRV_TWI_ERR_OVERRUN = (NRFX_ERROR_DRIVERS_BASE_NUM + 0), ///< TWI error: Overrun. + NRFX_ERROR_DRV_TWI_ERR_ANACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 1), ///< TWI error: Address not acknowledged. + NRFX_ERROR_DRV_TWI_ERR_DNACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 2) ///< TWI error: Data not acknowledged. +} nrfx_err_t; + +/** @} */ + +#endif // !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +#endif // NRFX_ERRORS_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c new file mode 100644 index 0000000..77b67af --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_gpiote.c @@ -0,0 +1,829 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include + +#if NRFX_CHECK(NRFX_GPIOTE_ENABLED) + +#include +#include "nrf_bitmask.h" +#include + +#define NRFX_LOG_MODULE GPIOTE +#include + + +#define FORBIDDEN_HANDLER_ADDRESS ((nrfx_gpiote_evt_handler_t)UINT32_MAX) +#define PIN_NOT_USED (-1) +#define PIN_USED (-2) +#define NO_CHANNELS (-1) +#define SENSE_FIELD_POS (6) +#define SENSE_FIELD_MASK (0xC0) + +/* Check if every pin can be encoded on provided number of bits. */ +NRFX_STATIC_ASSERT(NUMBER_OF_PINS <= (1 << SENSE_FIELD_POS)); + +/** + * @brief Macro for converting task-event index to an address of an event register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_IDX_TO_EVENT_ADDR(idx) (nrf_gpiote_events_t)((uint32_t)NRF_GPIOTE_EVENTS_IN_0 + \ + (sizeof(uint32_t) * (idx))) + +/** + * @brief Macro for converting task-event index of OUT task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_OUT_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_OUT_0 + \ + (sizeof(uint32_t) * (idx))) + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Macro for converting task-event index of SET task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_SET_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_SET_0 + \ + (sizeof(uint32_t) * (idx))) + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Macro for converting task-event index of CLR task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_CLR_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_CLR_0 + \ + (sizeof(uint32_t) * (idx))) + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + +/*lint -save -e571*/ /* Suppress "Warning 571: Suspicious cast" */ +typedef struct +{ + nrfx_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; + int8_t pin_assignments[NUMBER_OF_PINS]; + int8_t port_handlers_pins[NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; + uint8_t configured_pins[((NUMBER_OF_PINS)+7) / 8]; + nrfx_drv_state_t state; +} gpiote_control_block_t; + +static gpiote_control_block_t m_cb; + +__STATIC_INLINE bool pin_in_use(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] != PIN_NOT_USED); +} + + +__STATIC_INLINE bool pin_in_use_as_non_task_out(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] == PIN_USED); +} + + +__STATIC_INLINE bool pin_in_use_by_te(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] < GPIOTE_CH_NUM) ? + true : false; +} + + +__STATIC_INLINE bool pin_in_use_by_port(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= GPIOTE_CH_NUM); +} + + +__STATIC_INLINE bool pin_in_use_by_gpiote(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= 0); +} + + +__STATIC_INLINE void pin_in_use_by_te_set(uint32_t pin, + uint32_t channel_id, + nrfx_gpiote_evt_handler_t handler, + bool is_channel) +{ + m_cb.pin_assignments[pin] = channel_id; + m_cb.handlers[channel_id] = handler; + if (!is_channel) + { + m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)pin; + } +} + + +__STATIC_INLINE void pin_in_use_set(uint32_t pin) +{ + m_cb.pin_assignments[pin] = PIN_USED; +} + + +__STATIC_INLINE void pin_in_use_clear(uint32_t pin) +{ + m_cb.pin_assignments[pin] = PIN_NOT_USED; +} + + +__STATIC_INLINE void pin_configured_set(uint32_t pin) +{ + nrf_bitmask_bit_set(pin, m_cb.configured_pins); +} + +__STATIC_INLINE void pin_configured_clear(uint32_t pin) +{ + nrf_bitmask_bit_clear(pin, m_cb.configured_pins); +} + +__STATIC_INLINE bool pin_configured_check(uint32_t pin) +{ + return 0 != nrf_bitmask_bit_is_set(pin, m_cb.configured_pins); +} + +__STATIC_INLINE int8_t channel_port_get(uint32_t pin) +{ + return m_cb.pin_assignments[pin]; +} + + +__STATIC_INLINE nrfx_gpiote_evt_handler_t channel_handler_get(uint32_t channel) +{ + return m_cb.handlers[channel]; +} + + +static int8_t channel_port_alloc(uint32_t pin, nrfx_gpiote_evt_handler_t handler, bool channel) +{ + int8_t channel_id = NO_CHANNELS; + uint32_t i; + + uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM; + uint32_t end_idx = + channel ? GPIOTE_CH_NUM : (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); + + // critical section + + for (i = start_idx; i < end_idx; i++) + { + if (m_cb.handlers[i] == FORBIDDEN_HANDLER_ADDRESS) + { + pin_in_use_by_te_set(pin, i, handler, channel); + channel_id = i; + break; + } + } + // critical section + return channel_id; +} + + +static void channel_free(uint8_t channel_id) +{ + m_cb.handlers[channel_id] = FORBIDDEN_HANDLER_ADDRESS; + if (channel_id >= GPIOTE_CH_NUM) + { + m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; + } +} + + +nrfx_err_t nrfx_gpiote_init(void) +{ + nrfx_err_t err_code; + + if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + uint8_t i; + + for (i = 0; i < NUMBER_OF_PINS; i++) + { + pin_in_use_clear(i); + } + + for (i = 0; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) + { + channel_free(i); + } + + memset(m_cb.configured_pins, 0, sizeof(m_cb.configured_pins)); + + NRFX_IRQ_PRIORITY_SET(GPIOTE_IRQn, NRFX_GPIOTE_CONFIG_IRQ_PRIORITY); + NRFX_IRQ_ENABLE(GPIOTE_IRQn); + nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); + nrf_gpiote_int_enable(GPIOTE_INTENSET_PORT_Msk); + m_cb.state = NRFX_DRV_STATE_INITIALIZED; + + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + + +bool nrfx_gpiote_is_init(void) +{ + return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false; +} + + +void nrfx_gpiote_uninit(void) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + + uint32_t i; + + for (i = 0; i < NUMBER_OF_PINS; i++) + { + if (pin_in_use_as_non_task_out(i)) + { + nrfx_gpiote_out_uninit(i); + } + else if ( pin_in_use_by_gpiote(i)) + { + /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on + * so it can be called on all pins used by GPIOTE. + */ + nrfx_gpiote_in_uninit(i); + } + } + m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; + NRFX_LOG_INFO("Uninitialized."); +} + + +nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_out_config_t const * p_config) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED); + NRFX_ASSERT(p_config); + + nrfx_err_t err_code = NRFX_SUCCESS; + + if (pin_in_use(pin)) + { + err_code = NRFX_ERROR_INVALID_STATE; + } + else + { + if (p_config->task_pin) + { + int8_t channel = channel_port_alloc(pin, NULL, true); + + if (channel != NO_CHANNELS) + { + nrf_gpiote_task_configure((uint32_t)channel, + pin, + p_config->action, + p_config->init_state); + } + else + { + err_code = NRFX_ERROR_NO_MEM; + } + } + else + { + pin_in_use_set(pin); + } + + if (err_code == NRFX_SUCCESS) + { + if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH) + { + nrf_gpio_pin_set(pin); + } + else + { + nrf_gpio_pin_clear(pin); + } + + nrf_gpio_cfg_output(pin); + pin_configured_set(pin); + } + } + + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + + +void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + + if (pin_in_use_by_te(pin)) + { + channel_free((uint8_t)channel_port_get(pin)); + nrf_gpiote_te_default((uint32_t)channel_port_get(pin)); + } + pin_in_use_clear(pin); + + if (pin_configured_check(pin)) + { + nrf_gpio_cfg_default(pin); + pin_configured_clear(pin); + } +} + + +void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(!pin_in_use_by_te(pin)); + + nrf_gpio_pin_set(pin); +} + + +void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(!pin_in_use_by_te(pin)); + + nrf_gpio_pin_clear(pin); +} + + +void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(!pin_in_use_by_te(pin)); + + nrf_gpio_pin_toggle(pin); +} + + +void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_task_enable((uint32_t)m_cb.pin_assignments[pin]); +} + + +void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_task_disable((uint32_t)m_cb.pin_assignments[pin]); +} + + +uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#if defined(GPIOTE_FEATURE_SET_PRESENT) +uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) +uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) + +void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_outinit_t init_val = + state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW; + nrf_gpiote_task_force((uint32_t)m_cb.pin_assignments[pin], init_val); +} + + +void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#if defined(GPIOTE_FEATURE_SET_PRESENT) +void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) +void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use(pin)); + NRFX_ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR((uint32_t)channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) + +nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_in_config_t const * p_config, + nrfx_gpiote_evt_handler_t evt_handler) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + nrfx_err_t err_code = NRFX_SUCCESS; + + /* Only one GPIOTE channel can be assigned to one physical pin. */ + if (pin_in_use_by_gpiote(pin)) + { + err_code = NRFX_ERROR_INVALID_STATE; + } + else + { + int8_t channel = channel_port_alloc(pin, evt_handler, p_config->hi_accuracy); + if (channel != NO_CHANNELS) + { + if (!p_config->skip_gpio_setup) + { + if (p_config->is_watcher) + { + nrf_gpio_cfg_watcher(pin); + } + else + { + nrf_gpio_cfg_input(pin, p_config->pull); + } + pin_configured_set(pin); + } + + if (p_config->hi_accuracy) + { + nrf_gpiote_event_configure((uint32_t)channel, pin, p_config->sense); + } + else + { + m_cb.port_handlers_pins[channel - + GPIOTE_CH_NUM] |= (p_config->sense) << SENSE_FIELD_POS; + } + } + else + { + err_code = NRFX_ERROR_NO_MEM; + } + } + + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_gpiote(pin)); + if (pin_in_use_by_port(pin)) + { + uint8_t pin_and_sense = (uint8_t) + m_cb.port_handlers_pins[channel_port_get(pin) - GPIOTE_CH_NUM]; + nrf_gpiote_polarity_t polarity = + (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS); + nrf_gpio_pin_sense_t sense; + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + /* read current pin state and set for next sense to oposit */ + sense = (nrf_gpio_pin_read(pin)) ? + NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; + } + else + { + sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ? + NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW; + } + nrf_gpio_cfg_sense_set(pin, sense); + } + else if (pin_in_use_by_te(pin)) + { + int32_t channel = (int32_t)channel_port_get(pin); + nrf_gpiote_events_t event = TE_IDX_TO_EVENT_ADDR((uint32_t)channel); + + nrf_gpiote_event_enable((uint32_t)channel); + + nrf_gpiote_event_clear(event); + if (int_enable) + { + nrfx_gpiote_evt_handler_t handler = channel_handler_get((uint32_t)channel_port_get(pin)); + // Enable the interrupt only if event handler was provided. + if (handler) + { + nrf_gpiote_int_enable(1 << channel); + } + } + } +} + + +void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_gpiote(pin)); + if (pin_in_use_by_port(pin)) + { + nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); + } + else if (pin_in_use_by_te(pin)) + { + int32_t channel = (int32_t)channel_port_get(pin); + nrf_gpiote_event_disable((uint32_t)channel); + nrf_gpiote_int_disable(1 << channel); + } +} + + +void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_gpiote(pin)); + nrfx_gpiote_in_event_disable(pin); + if (pin_in_use_by_te(pin)) + { + nrf_gpiote_te_default((uint32_t)channel_port_get(pin)); + } + if (pin_configured_check(pin)) + { + nrf_gpio_cfg_default(pin); + pin_configured_clear(pin); + } + channel_free((uint8_t)channel_port_get(pin)); + pin_in_use_clear(pin); +} + + +bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + return nrf_gpio_pin_read(pin) ? true : false; +} + + +uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin) +{ + NRFX_ASSERT(pin < NUMBER_OF_PINS); + NRFX_ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin)); + + nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_PORT; + + if (pin_in_use_by_te(pin)) + { + event = TE_IDX_TO_EVENT_ADDR((uint32_t)channel_port_get(pin)); + } + return nrf_gpiote_event_addr_get(event); +} + + +void nrfx_gpiote_irq_handler(void) +{ + uint32_t status = 0; + uint32_t input[GPIO_COUNT] = {0}; + + /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/ + uint32_t i; + nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_IN_0; + uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + + for (i = 0; i < GPIOTE_CH_NUM; i++) + { + if (nrf_gpiote_event_is_set(event) && nrf_gpiote_int_is_enabled(mask)) + { + nrf_gpiote_event_clear(event); + status |= mask; + } + mask <<= 1; + /* Incrementing to next event, utilizing the fact that events are grouped together + * in ascending order. */ + event = (nrf_gpiote_events_t)((uint32_t)event + sizeof(uint32_t)); + } + + /* collect PORT status event, if event is set read pins state. Processing is postponed to the + * end of interrupt. */ + if (nrf_gpiote_event_is_set(NRF_GPIOTE_EVENTS_PORT)) + { + nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); + status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK; + nrf_gpio_ports_read(0, GPIO_COUNT, input); + } + + /* Process pin events. */ + if (status & NRF_GPIOTE_INT_IN_MASK) + { + mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + + for (i = 0; i < GPIOTE_CH_NUM; i++) + { + if (mask & status) + { + nrfx_gpiote_pin_t pin = nrf_gpiote_event_pin_get(i); + NRFX_LOG_DEBUG("Event in number: %d.", i); + nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(i); + nrfx_gpiote_evt_handler_t handler = channel_handler_get(i); + NRFX_LOG_DEBUG("Pin: %d, polarity: %d.", pin, polarity); + if (handler) + { + handler(pin, polarity); + } + } + mask <<= 1; + } + } + + if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK) + { + /* Process port event. */ + uint32_t port_idx; + uint8_t repeat = 0; + uint32_t toggle_mask[GPIO_COUNT] = {0}; + uint32_t pins_to_check[GPIO_COUNT]; + + // Faster way of doing memset because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + pins_to_check[port_idx] = 0xFFFFFFFF; + } + + do + { + repeat = 0; + + for (i = 0; i < NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++) + { + uint8_t pin_and_sense = (uint8_t)m_cb.port_handlers_pins[i]; + nrfx_gpiote_pin_t pin = (pin_and_sense & ~SENSE_FIELD_MASK); + + if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED) + && nrf_bitmask_bit_is_set(pin, pins_to_check)) + { + nrf_gpiote_polarity_t polarity = + (nrf_gpiote_polarity_t)((pin_and_sense & + SENSE_FIELD_MASK) >> SENSE_FIELD_POS); + nrfx_gpiote_evt_handler_t handler = + channel_handler_get((uint32_t)channel_port_get(pin)); + if (handler || (polarity == NRF_GPIOTE_POLARITY_TOGGLE)) + { + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + nrf_bitmask_bit_set(pin, toggle_mask); + } + nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); + uint32_t pin_state = nrf_bitmask_bit_is_set(pin, input); + if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) || + (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) ) + { + NRFX_LOG_DEBUG("PORT event for pin: %d, polarity: %d.", pin, polarity); + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + nrf_gpio_pin_sense_t next_sense = + (sense == NRF_GPIO_PIN_SENSE_HIGH) ? + NRF_GPIO_PIN_SENSE_LOW : + NRF_GPIO_PIN_SENSE_HIGH; + nrf_gpio_cfg_sense_set(pin, next_sense); + ++repeat; + + } + if (handler) + { + handler(pin, polarity); + } + } + } + } + } + + if (repeat) + { + // When one of the pins in low-accuracy and toggle mode becomes active, + // it's sense mode is inverted to clear the internal SENSE signal. + // State of any other enabled low-accuracy input in toggle mode must be checked + // explicitly, because it does not trigger the interrput when SENSE signal is active. + // For more information about SENSE functionality, refer to Product Specification. + + uint32_t new_input[GPIO_COUNT]; + bool input_unchanged = true; + nrf_gpio_ports_read(0, GPIO_COUNT, new_input); + + // Faster way of doing memcmp because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + if (new_input[port_idx] != input[port_idx]) + { + input_unchanged = false; + break; + } + } + + if (input_unchanged) + { + // No change. + repeat = 0; + } + else + { + // Faster way of doing memcpy because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + input[port_idx] = new_input[port_idx]; + pins_to_check[port_idx] = toggle_mask[port_idx]; + } + } + } + } + while (repeat); + } +} + + +/*lint -restore*/ +#endif // NRFX_CHECK(NRFX_GPIOTE_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spi.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spi.c new file mode 100644 index 0000000..91943c4 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spi.c @@ -0,0 +1,441 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_SPI_ENABLED) + +#if !(NRFX_CHECK(NRFX_SPI0_ENABLED) || NRFX_CHECK(NRFX_SPI1_ENABLED) || \ + NRFX_CHECK(NRFX_SPI2_ENABLED)) +#error "No enabled SPI instances. Check ." +#endif + +#include +#include "prs/nrfx_prs.h" +#include + +#define NRFX_LOG_MODULE SPI +#include + +// Control block - driver instance local data. +typedef struct +{ + nrfx_spi_evt_handler_t handler; + void * p_context; + nrfx_spi_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy. + nrfx_drv_state_t state; + volatile bool transfer_in_progress; + + // [no need for 'volatile' attribute for the following members, as they + // are not concurrently used in IRQ handlers and main line code] + uint8_t ss_pin; + uint8_t miso_pin; + uint8_t orc; + size_t bytes_transferred; + + bool abort; +} spi_control_block_t; +static spi_control_block_t m_cb[NRFX_SPI_ENABLED_COUNT]; + + +nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, + nrfx_spi_config_t const * p_config, + nrfx_spi_evt_handler_t handler, + void * p_context) +{ + NRFX_ASSERT(p_config); + spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + static nrfx_irq_handler_t const irq_handlers[NRFX_SPI_ENABLED_COUNT] = { + #if NRFX_CHECK(NRFX_SPI0_ENABLED) + nrfx_spi_0_irq_handler, + #endif + #if NRFX_CHECK(NRFX_SPI1_ENABLED) + nrfx_spi_1_irq_handler, + #endif + #if NRFX_CHECK(NRFX_SPI2_ENABLED) + nrfx_spi_2_irq_handler, + #endif + }; + if (nrfx_prs_acquire(p_instance->p_reg, + irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) + + p_cb->handler = handler; + p_cb->p_context = p_context; + + uint32_t mosi_pin; + uint32_t miso_pin; + // Configure pins used by the peripheral: + // - SCK - output with initial value corresponding with the SPI mode used: + // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); + // according to the reference manual guidelines this pin and its input + // buffer must always be connected for the SPI to work. + if (p_config->mode <= NRF_SPI_MODE_1) + { + nrf_gpio_pin_clear(p_config->sck_pin); + } + else + { + nrf_gpio_pin_set(p_config->sck_pin); + } + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + // - MOSI (optional) - output with initial value 0, + if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED) + { + mosi_pin = p_config->mosi_pin; + nrf_gpio_pin_clear(mosi_pin); + nrf_gpio_cfg_output(mosi_pin); + } + else + { + mosi_pin = NRF_SPI_PIN_NOT_CONNECTED; + } + // - MISO (optional) - input, + if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED) + { + miso_pin = p_config->miso_pin; + nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPI_MISO_PULL_CFG); + } + else + { + miso_pin = NRF_SPI_PIN_NOT_CONNECTED; + } + m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin; + // - Slave Select (optional) - output with initial value 1 (inactive). + if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_set(p_config->ss_pin); + nrf_gpio_cfg_output(p_config->ss_pin); + } + m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin; + + NRF_SPI_Type * p_spi = p_instance->p_reg; + nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin); + nrf_spi_frequency_set(p_spi, p_config->frequency); + nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order); + + m_cb[p_instance->drv_inst_idx].orc = p_config->orc; + + if (p_cb->handler) + { + nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK); + } + + nrf_spi_enable(p_spi); + + if (p_cb->handler) + { + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), + p_config->irq_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); + } + + p_cb->transfer_in_progress = false; + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_spi_uninit(nrfx_spi_t const * const p_instance) +{ + spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + if (p_cb->handler) + { + NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); + } + + NRF_SPI_Type * p_spi = p_instance->p_reg; + if (p_cb->handler) + { + nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK); + } + + if (p_cb->miso_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->miso_pin); + } + nrf_spi_disable(p_spi); + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + nrfx_prs_release(p_instance->p_reg); +#endif + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; +} + +static void finish_transfer(spi_control_block_t * p_cb) +{ + // If Slave Select signal is used, this is the time to deactivate it. + if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_set(p_cb->ss_pin); + } + + // By clearing this flag before calling the handler we allow subsequent + // transfers to be started directly from the handler function. + p_cb->transfer_in_progress = false; + + p_cb->evt.type = NRFX_SPI_EVENT_DONE; + p_cb->handler(&p_cb->evt, p_cb->p_context); +} + +// This function is called from the IRQ handler or, in blocking mode, directly +// from the 'spi_xfer' function. +// It returns true as long as the transfer should be continued, otherwise (when +// there is nothing more to send/receive) it returns false. +static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb) +{ + // Read the data byte received in this transfer (always, because no further + // READY event can be generated until the current byte is read out from the + // RXD register), and store it in the RX buffer (only when needed). + volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi); + if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length) + { + p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data; + } + + ++p_cb->bytes_transferred; + + // Check if there are more bytes to send or receive and write proper data + // byte (next one from TX buffer or over-run character) to the TXD register + // when needed. + // NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our + // buffers, because we take advantage of double buffering of TXD + // register (so in effect one byte is still being transmitted now); + // see how the transfer is started in the 'spi_xfer' function. + size_t bytes_used = p_cb->bytes_transferred + 1; + + if (p_cb->abort) + { + if (bytes_used < p_cb->evt.xfer_desc.tx_length) + { + p_cb->evt.xfer_desc.tx_length = bytes_used; + } + if (bytes_used < p_cb->evt.xfer_desc.rx_length) + { + p_cb->evt.xfer_desc.rx_length = bytes_used; + } + } + + if (bytes_used < p_cb->evt.xfer_desc.tx_length) + { + nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]); + return true; + } + else if (bytes_used < p_cb->evt.xfer_desc.rx_length) + { + nrf_spi_txd_set(p_spi, p_cb->orc); + return true; + } + + return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length || + p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length); +} + +static void spi_xfer(NRF_SPI_Type * p_spi, + spi_control_block_t * p_cb, + nrfx_spi_xfer_desc_t const * p_xfer_desc) +{ + p_cb->bytes_transferred = 0; + nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK); + + nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); + + // Start the transfer by writing some byte to the TXD register; + // if TX buffer is not empty, take the first byte from this buffer, + // otherwise - use over-run character. + nrf_spi_txd_set(p_spi, + (p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc)); + + // TXD register is double buffered, so next byte to be transmitted can + // be written immediately, if needed, i.e. if TX or RX transfer is to + // be more that 1 byte long. Again - if there is something more in TX + // buffer send it, otherwise use over-run character. + if (p_xfer_desc->tx_length > 1) + { + nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]); + } + else if (p_xfer_desc->rx_length > 1) + { + nrf_spi_txd_set(p_spi, p_cb->orc); + } + + // For blocking mode (user handler not provided) wait here for READY + // events (indicating that the byte from TXD register was transmitted + // and a new incoming byte was moved to the RXD register) and continue + // transaction until all requested bytes are transferred. + // In non-blocking mode - IRQ service routine will do this stuff. + if (p_cb->handler) + { + nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK); + } + else + { + do { + while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {} + nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); + NRFX_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY."); + } while (transfer_byte(p_spi, p_cb)); + if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_set(p_cb->ss_pin); + } + } +} + +nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance, + nrfx_spi_xfer_desc_t const * p_xfer_desc, + uint32_t flags) +{ + spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0); + NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0); + + nrfx_err_t err_code = NRFX_SUCCESS; + + if (p_cb->transfer_in_progress) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + else + { + if (p_cb->handler) + { + p_cb->transfer_in_progress = true; + } + } + + p_cb->evt.xfer_desc = *p_xfer_desc; + p_cb->abort = false; + + if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_clear(p_cb->ss_pin); + } + if (flags) + { + p_cb->transfer_in_progress = false; + err_code = NRFX_ERROR_NOT_SUPPORTED; + } + else + { + spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc); + } + NRFX_LOG_INFO("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_spi_abort(nrfx_spi_t const * p_instance) +{ + spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + p_cb->abort = true; +} + +static void irq_handler(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb) +{ + NRFX_ASSERT(p_cb->handler); + + nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY); + NRFX_LOG_DEBUG("Event: NRF_SPI_EVENT_READY."); + + if (!transfer_byte(p_spi, p_cb)) + { + finish_transfer(p_cb); + } +} + +#if NRFX_CHECK(NRFX_SPI0_ENABLED) +void nrfx_spi_0_irq_handler(void) +{ + irq_handler(NRF_SPI0, &m_cb[NRFX_SPI0_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_SPI1_ENABLED) +void nrfx_spi_1_irq_handler(void) +{ + irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_SPI2_ENABLED) +void nrfx_spi_2_irq_handler(void) +{ + irq_handler(NRF_SPI2, &m_cb[NRFX_SPI2_INST_IDX]); +} +#endif + +#endif // NRFX_CHECK(NRFX_SPI_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spim.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spim.c new file mode 100644 index 0000000..f8de9bd --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_spim.c @@ -0,0 +1,702 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_SPIM_ENABLED) + +#if !(NRFX_CHECK(NRFX_SPIM0_ENABLED) || NRFX_CHECK(NRFX_SPIM1_ENABLED) || \ + NRFX_CHECK(NRFX_SPIM2_ENABLED) || NRFX_CHECK(NRFX_SPIM3_ENABLED)) +#error "No enabled SPIM instances. Check ." +#endif + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) && !NRFX_CHECK(NRFX_SPIM3_ENABLED) +#error "Extended options are available only in SPIM3 on the nRF52840 SoC." +#endif + +#include +#include "prs/nrfx_prs.h" +#include + +#define NRFX_LOG_MODULE SPIM +#include + +#define SPIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, rx_len, tx_len) \ + (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ + NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, rx_len, tx_len)) + +#if NRFX_CHECK(NRFX_SPIM0_ENABLED) +#define SPIM0_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM0, __VA_ARGS__) +#else +#define SPIM0_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_SPIM1_ENABLED) +#define SPIM1_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM1, __VA_ARGS__) +#else +#define SPIM1_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_SPIM2_ENABLED) +#define SPIM2_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM2, __VA_ARGS__) +#else +#define SPIM2_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_SPIM3_ENABLED) +#define SPIM3_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM3, __VA_ARGS__) +#else +#define SPIM3_LENGTH_VALIDATE(...) 0 +#endif + +#define SPIM_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \ + (SPIM0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ + SPIM1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ + SPIM2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \ + SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len)) + +#if defined(NRF52840_XXAA) && (NRFX_CHECK(NRFX_SPIM3_ENABLED)) +// Enable workaround for nRF52840 anomaly 195 (SPIM3 continues to draw current after disable). +#define USE_WORKAROUND_FOR_ANOMALY_195 +#endif + +// Control block - driver instance local data. +typedef struct +{ + nrfx_spim_evt_handler_t handler; + void * p_context; + nrfx_spim_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy. + nrfx_drv_state_t state; + volatile bool transfer_in_progress; + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + bool use_hw_ss; +#endif + + // [no need for 'volatile' attribute for the following members, as they + // are not concurrently used in IRQ handlers and main line code] + bool ss_active_high; + uint8_t ss_pin; + uint8_t miso_pin; + uint8_t orc; + +#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) + size_t tx_length; + size_t rx_length; +#endif +} spim_control_block_t; +static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT]; + +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + +// Workaround for nRF52840 anomaly 198: SPIM3 transmit data might be corrupted. + +static uint32_t m_anomaly_198_preserved_value; + +static void anomaly_198_enable(uint8_t const * p_buffer, size_t buf_len) +{ + m_anomaly_198_preserved_value = *((volatile uint32_t *)0x40000E00); + + if (buf_len == 0) + { + return; + } + uint32_t buffer_end_addr = ((uint32_t)p_buffer) + buf_len; + uint32_t block_addr = ((uint32_t)p_buffer) & ~0x1FFF; + uint32_t block_flag = (1UL << ((block_addr >> 13) & 0xFFFF)); + uint32_t occupied_blocks = 0; + + if (block_addr >= 0x20010000) + { + occupied_blocks = (1UL << 8); + } + else + { + do { + occupied_blocks |= block_flag; + block_flag <<= 1; + block_addr += 0x2000; + } while ((block_addr < buffer_end_addr) && (block_addr < 0x20012000)); + } + + *((volatile uint32_t *)0x40000E00) = occupied_blocks; +} + +static void anomaly_198_disable(void) +{ + *((volatile uint32_t *)0x40000E00) = m_anomaly_198_preserved_value; +} +#endif // NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + +nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, + nrfx_spim_config_t const * p_config, + nrfx_spim_evt_handler_t handler, + void * p_context) +{ + NRFX_ASSERT(p_config); + spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + // Currently, only SPIM3 in nRF52840 supports the extended features. + // Other instances must be checked. + if ((p_instance->drv_inst_idx != NRFX_SPIM3_INST_IDX) && + ((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) || + (p_config->frequency == NRF_SPIM_FREQ_16M) || + (p_config->frequency == NRF_SPIM_FREQ_32M) || + (p_config->use_hw_ss))) + { + err_code = NRFX_ERROR_NOT_SUPPORTED; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif + + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + static nrfx_irq_handler_t const irq_handlers[NRFX_SPIM_ENABLED_COUNT] = { + #if NRFX_CHECK(NRFX_SPIM0_ENABLED) + nrfx_spim_0_irq_handler, + #endif + #if NRFX_CHECK(NRFX_SPIM1_ENABLED) + nrfx_spim_1_irq_handler, + #endif + #if NRFX_CHECK(NRFX_SPIM2_ENABLED) + nrfx_spim_2_irq_handler, + #endif + #if NRFX_CHECK(NRFX_SPIM3_ENABLED) + nrfx_spim_3_irq_handler, + #endif + }; + if (nrfx_prs_acquire(p_instance->p_reg, + irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) + + p_cb->handler = handler; + p_cb->p_context = p_context; + + uint32_t mosi_pin; + uint32_t miso_pin; + // Configure pins used by the peripheral: + // - SCK - output with initial value corresponding with the SPI mode used: + // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); + // according to the reference manual guidelines this pin and its input + // buffer must always be connected for the SPI to work. + if (p_config->mode <= NRF_SPIM_MODE_1) + { + nrf_gpio_pin_clear(p_config->sck_pin); + } + else + { + nrf_gpio_pin_set(p_config->sck_pin); + } + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + // - MOSI (optional) - output with initial value 0, + if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) + { + mosi_pin = p_config->mosi_pin; + nrf_gpio_pin_clear(mosi_pin); + nrf_gpio_cfg_output(mosi_pin); + } + else + { + mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED; + } + // - MISO (optional) - input, + if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) + { + miso_pin = p_config->miso_pin; + nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPIM_MISO_PULL_CFG); + } + else + { + miso_pin = NRF_SPIM_PIN_NOT_CONNECTED; + } + p_cb->miso_pin = p_config->miso_pin; + // - Slave Select (optional) - output with initial value 1 (inactive). + + // 'p_cb->ss_pin' variable is used during transfers to check if SS pin should be toggled, + // so this field needs to be initialized even if the pin is not used. + p_cb->ss_pin = p_config->ss_pin; + + if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { + if (p_config->ss_active_high) + { + nrf_gpio_pin_clear(p_config->ss_pin); + } + else + { + nrf_gpio_pin_set(p_config->ss_pin); + } + nrf_gpio_cfg_output(p_config->ss_pin); +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (p_config->use_hw_ss) + { + p_cb->use_hw_ss = p_config->use_hw_ss; + nrf_spim_csn_configure(p_spim, + p_config->ss_pin, + (p_config->ss_active_high == true ? + NRF_SPIM_CSN_POL_HIGH : NRF_SPIM_CSN_POL_LOW), + p_config->ss_duration); + } +#endif + p_cb->ss_active_high = p_config->ss_active_high; + } + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + // - DCX (optional) - output. + if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_pin_set(p_config->dcx_pin); + nrf_gpio_cfg_output(p_config->dcx_pin); + nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin); + } + + // Change rx delay + nrf_spim_iftiming_set(p_spim, p_config->rx_delay); +#endif + + + nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); + nrf_spim_frequency_set(p_spim, p_config->frequency); + nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order); + + nrf_spim_orc_set(p_spim, p_config->orc); + + if (p_cb->handler) + { + nrf_spim_int_enable(p_spim, NRF_SPIM_INT_END_MASK); + } + + nrf_spim_enable(p_spim); + + if (p_cb->handler) + { + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), + p_config->irq_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); + } + + p_cb->transfer_in_progress = false; + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_spim_uninit(nrfx_spim_t const * const p_instance) +{ + spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + if (p_cb->handler) + { + NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); + } + + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; + if (p_cb->handler) + { + nrf_spim_int_disable(p_spim, NRF_SPIM_ALL_INTS_MASK); + if (p_cb->transfer_in_progress) + { + // Ensure that SPI is not performing any transfer. + nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP); + while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) + {} + p_cb->transfer_in_progress = false; + } + } + + if (p_cb->miso_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->miso_pin); + } + nrf_spim_disable(p_spim); + +#ifdef USE_WORKAROUND_FOR_ANOMALY_195 + if (p_spim == NRF_SPIM3) + { + *(volatile uint32_t *)0x4002F004 = 1; + } +#endif + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + nrfx_prs_release(p_instance->p_reg); +#endif + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; +} + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) +nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags, + uint8_t cmd_length) +{ + NRFX_ASSERT(cmd_length <= NRF_SPIM_DCX_CNT_ALL_CMD); + nrf_spim_dcx_cnt_set((NRF_SPIM_Type *)p_instance->p_reg, cmd_length); + return nrfx_spim_xfer(p_instance, p_xfer_desc, 0); +} +#endif + +static void finish_transfer(spim_control_block_t * p_cb) +{ + // If Slave Select signal is used, this is the time to deactivate it. + if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (!p_cb->use_hw_ss) +#endif + { + if (p_cb->ss_active_high) + { + nrf_gpio_pin_clear(p_cb->ss_pin); + } + else + { + nrf_gpio_pin_set(p_cb->ss_pin); + } + } + } + + // By clearing this flag before calling the handler we allow subsequent + // transfers to be started directly from the handler function. + p_cb->transfer_in_progress = false; + + p_cb->evt.type = NRFX_SPIM_EVENT_DONE; + p_cb->handler(&p_cb->evt, p_cb->p_context); +} + +__STATIC_INLINE void spim_int_enable(NRF_SPIM_Type * p_spim, bool enable) +{ + if (!enable) + { + nrf_spim_int_disable(p_spim, NRF_SPIM_INT_END_MASK); + } + else + { + nrf_spim_int_enable(p_spim, NRF_SPIM_INT_END_MASK); + } +} + +__STATIC_INLINE void spim_list_enable_handle(NRF_SPIM_Type * p_spim, uint32_t flags) +{ + if (NRFX_SPIM_FLAG_TX_POSTINC & flags) + { + nrf_spim_tx_list_enable(p_spim); + } + else + { + nrf_spim_tx_list_disable(p_spim); + } + + if (NRFX_SPIM_FLAG_RX_POSTINC & flags) + { + nrf_spim_rx_list_enable(p_spim); + } + else + { + nrf_spim_rx_list_disable(p_spim); + } +} + +static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, + spim_control_block_t * p_cb, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags) +{ + nrfx_err_t err_code; + // EasyDMA requires that transfer buffers are placed in Data RAM region; + // signal error if they are not. + if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) || + (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer))) + { + p_cb->transfer_in_progress = false; + err_code = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) + p_cb->tx_length = 0; + p_cb->rx_length = 0; +#endif + + nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); + nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length); + +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_enable(p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length); + } +#endif + + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); + + spim_list_enable_handle(p_spim, flags); + + if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER)) + { + nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START); + } +#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) + if (flags & NRFX_SPIM_FLAG_HOLD_XFER) + { + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); + p_cb->tx_length = p_xfer_desc->tx_length; + p_cb->rx_length = p_xfer_desc->rx_length; + nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, 0); + nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, 0); + nrf_spim_int_enable(p_spim, NRF_SPIM_INT_STARTED_MASK); + } +#endif + + if (!p_cb->handler) + { + while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){} + +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_disable(); + } +#endif + if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (!p_cb->use_hw_ss) +#endif + { + if (p_cb->ss_active_high) + { + nrf_gpio_pin_clear(p_cb->ss_pin); + } + else + { + nrf_gpio_pin_set(p_cb->ss_pin); + } + } + } + } + else + { + spim_int_enable(p_spim, !(flags & NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER)); + } + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags) +{ + spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0); + NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0); + NRFX_ASSERT(SPIM_LENGTH_VALIDATE(p_instance->drv_inst_idx, + p_xfer_desc->rx_length, + p_xfer_desc->tx_length)); + + nrfx_err_t err_code = NRFX_SUCCESS; + + if (p_cb->transfer_in_progress) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + else + { + if (p_cb->handler && !(flags & (NRFX_SPIM_FLAG_REPEATED_XFER | + NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER))) + { + p_cb->transfer_in_progress = true; + } + } + + p_cb->evt.xfer_desc = *p_xfer_desc; + + if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (!p_cb->use_hw_ss) +#endif + { + if (p_cb->ss_active_high) + { + nrf_gpio_pin_set(p_cb->ss_pin); + } + else + { + nrf_gpio_pin_clear(p_cb->ss_pin); + } + } + } + + return spim_xfer(p_instance->p_reg, p_cb, p_xfer_desc, flags); +} + +void nrfx_spim_abort(nrfx_spim_t const * p_instance) +{ + spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + nrf_spim_task_trigger(p_instance->p_reg, NRF_SPIM_TASK_STOP); + while (!nrf_spim_event_check(p_instance->p_reg, NRF_SPIM_EVENT_STOPPED)) + {} + p_cb->transfer_in_progress = false; +} + +uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance) +{ + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; + return nrf_spim_task_address_get(p_spim, NRF_SPIM_TASK_START); +} + +uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance) +{ + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; + return nrf_spim_event_address_get(p_spim, NRF_SPIM_EVENT_END); +} + +static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) +{ + +#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) + if ((nrf_spim_int_enable_check(p_spim, NRF_SPIM_INT_STARTED_MASK)) && + (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STARTED)) ) + { + /* Handle first, zero-length, auxiliary transmission. */ + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); + + NRFX_ASSERT(p_spim->TXD.MAXCNT == 0); + p_spim->TXD.MAXCNT = p_cb->tx_length; + + NRFX_ASSERT(p_spim->RXD.MAXCNT == 0); + p_spim->RXD.MAXCNT = p_cb->rx_length; + + /* Disable STARTED interrupt, used only in auxiliary transmission. */ + nrf_spim_int_disable(p_spim, NRF_SPIM_INT_STARTED_MASK); + + /* Start the actual, glitch-free transmission. */ + nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START); + return; + } +#endif + + if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)) + { +#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) + if (p_spim == NRF_SPIM3) + { + anomaly_198_disable(); + } +#endif + nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); + NRFX_ASSERT(p_cb->handler); + NRFX_LOG_DEBUG("Event: NRF_SPIM_EVENT_END."); + finish_transfer(p_cb); + } +} + +#if NRFX_CHECK(NRFX_SPIM0_ENABLED) +void nrfx_spim_0_irq_handler(void) +{ + irq_handler(NRF_SPIM0, &m_cb[NRFX_SPIM0_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_SPIM1_ENABLED) +void nrfx_spim_1_irq_handler(void) +{ + irq_handler(NRF_SPIM1, &m_cb[NRFX_SPIM1_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_SPIM2_ENABLED) +void nrfx_spim_2_irq_handler(void) +{ + irq_handler(NRF_SPIM2, &m_cb[NRFX_SPIM2_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_SPIM3_ENABLED) +void nrfx_spim_3_irq_handler(void) +{ + irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]); +} +#endif + +#endif // NRFX_CHECK(NRFX_SPIM_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_timer.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_timer.c new file mode 100644 index 0000000..3ef8fa9 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_timer.c @@ -0,0 +1,330 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_TIMER_ENABLED) + +#if !(NRFX_CHECK(NRFX_TIMER0_ENABLED) || NRFX_CHECK(NRFX_TIMER1_ENABLED) || \ + NRFX_CHECK(NRFX_TIMER2_ENABLED) || NRFX_CHECK(NRFX_TIMER3_ENABLED) || \ + NRFX_CHECK(NRFX_TIMER4_ENABLED)) +#error "No enabled TIMER instances. Check ." +#endif + +#include + +#define NRFX_LOG_MODULE TIMER +#include + +/**@brief Timer control block. */ +typedef struct +{ + nrfx_timer_event_handler_t handler; + void * context; + nrfx_drv_state_t state; +} timer_control_block_t; + +static timer_control_block_t m_cb[NRFX_TIMER_ENABLED_COUNT]; + +nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance, + nrfx_timer_config_t const * p_config, + nrfx_timer_event_handler_t timer_event_handler) +{ + timer_control_block_t * p_cb = &m_cb[p_instance->instance_id]; +#ifdef SOFTDEVICE_PRESENT + NRFX_ASSERT(p_instance->p_reg != NRF_TIMER0); +#endif + NRFX_ASSERT(p_config); + NRFX_ASSERT(timer_event_handler); + + nrfx_err_t err_code; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + /* Warning 685: Relational operator '<=' always evaluates to 'true'" + * Warning in NRF_TIMER_IS_BIT_WIDTH_VALID macro. Macro validate timers resolution. + * Not necessary in nRF52 based systems. Obligatory in nRF51 based systems. + */ + + /*lint -save -e685 */ + + NRFX_ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width)); + + //lint -restore + + p_cb->handler = timer_event_handler; + p_cb->context = p_config->p_context; + + uint8_t i; + for (i = 0; i < p_instance->cc_channel_count; ++i) + { + nrf_timer_event_clear(p_instance->p_reg, + nrf_timer_compare_event_get(i)); + } + + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg), + p_config->interrupt_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg)); + + nrf_timer_mode_set(p_instance->p_reg, p_config->mode); + nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width); + nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency); + + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_timer_uninit(nrfx_timer_t const * const p_instance) +{ + NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); + + #define DISABLE_ALL UINT32_MAX + nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL); + nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL); + #undef DISABLE_ALL + + nrfx_timer_disable(p_instance); + + m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_UNINITIALIZED; + NRFX_LOG_INFO("Uninitialized instance: %d.", p_instance->instance_id); +} + +void nrfx_timer_enable(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_INITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); + m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_POWERED_ON; + NRFX_LOG_INFO("Enabled instance: %d.", p_instance->instance_id); +} + +void nrfx_timer_disable(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN); + m_cb[p_instance->instance_id].state = NRFX_DRV_STATE_INITIALIZED; + NRFX_LOG_INFO("Disabled instance: %d.", p_instance->instance_id); +} + +bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + return (m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_POWERED_ON); +} + +void nrfx_timer_resume(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START); + NRFX_LOG_INFO("Resumed instance: %d.", p_instance->instance_id); +} + +void nrfx_timer_pause(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP); + NRFX_LOG_INFO("Paused instance: %d.", p_instance->instance_id); +} + +void nrfx_timer_clear(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR); +} + +void nrfx_timer_increment(nrfx_timer_t const * const p_instance) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER); + + nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT); +} + +uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(cc_channel < p_instance->cc_channel_count); + + nrf_timer_task_trigger(p_instance->p_reg, + nrf_timer_capture_task_get(cc_channel)); + return nrf_timer_cc_read(p_instance->p_reg, cc_channel); +} + +void nrfx_timer_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + bool enable_int) +{ + nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel); + + if (enable_int) + { + nrf_timer_event_clear(p_instance->p_reg, nrf_timer_compare_event_get(cc_channel)); + nrf_timer_int_enable(p_instance->p_reg, timer_int); + } + else + { + nrf_timer_int_disable(p_instance->p_reg, timer_int); + } + + nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value); + NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.", + p_instance->instance_id, + cc_value, + cc_channel); +} + +void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + nrf_timer_short_mask_t timer_short_mask, + bool enable_int) +{ + nrf_timer_shorts_disable(p_instance->p_reg, + (TIMER_SHORTS_COMPARE0_STOP_Msk << cc_channel) | + (TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel)); + + nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask); + + nrfx_timer_compare(p_instance, + cc_channel, + cc_value, + enable_int); + NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.", + p_instance->instance_id, + cc_value, + cc_channel); +} + +void nrfx_timer_compare_int_enable(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(channel < p_instance->cc_channel_count); + + nrf_timer_event_clear(p_instance->p_reg, + nrf_timer_compare_event_get(channel)); + nrf_timer_int_enable(p_instance->p_reg, + nrf_timer_compare_int_get(channel)); +} + +void nrfx_timer_compare_int_disable(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(channel < p_instance->cc_channel_count); + + nrf_timer_int_disable(p_instance->p_reg, + nrf_timer_compare_int_get(channel)); +} + +static void irq_handler(NRF_TIMER_Type * p_reg, + timer_control_block_t * p_cb, + uint8_t channel_count) +{ + uint8_t i; + for (i = 0; i < channel_count; ++i) + { + nrf_timer_event_t event = nrf_timer_compare_event_get(i); + nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i); + + if (nrf_timer_event_check(p_reg, event) && + nrf_timer_int_enable_check(p_reg, int_mask)) + { + nrf_timer_event_clear(p_reg, event); + NRFX_LOG_DEBUG("Compare event, channel: %d.", i); + p_cb->handler(event, p_cb->context); + } + } +} + +#if NRFX_CHECK(NRFX_TIMER0_ENABLED) +void nrfx_timer_0_irq_handler(void) +{ + irq_handler(NRF_TIMER0, &m_cb[NRFX_TIMER0_INST_IDX], + NRF_TIMER_CC_CHANNEL_COUNT(0)); +} +#endif + +#if NRFX_CHECK(NRFX_TIMER1_ENABLED) +void nrfx_timer_1_irq_handler(void) +{ + irq_handler(NRF_TIMER1, &m_cb[NRFX_TIMER1_INST_IDX], + NRF_TIMER_CC_CHANNEL_COUNT(1)); +} +#endif + +#if NRFX_CHECK(NRFX_TIMER2_ENABLED) +void nrfx_timer_2_irq_handler(void) +{ + irq_handler(NRF_TIMER2, &m_cb[NRFX_TIMER2_INST_IDX], + NRF_TIMER_CC_CHANNEL_COUNT(2)); +} +#endif + +#if NRFX_CHECK(NRFX_TIMER3_ENABLED) +void nrfx_timer_3_irq_handler(void) +{ + irq_handler(NRF_TIMER3, &m_cb[NRFX_TIMER3_INST_IDX], + NRF_TIMER_CC_CHANNEL_COUNT(3)); +} +#endif + +#if NRFX_CHECK(NRFX_TIMER4_ENABLED) +void nrfx_timer_4_irq_handler(void) +{ + irq_handler(NRF_TIMER4, &m_cb[NRFX_TIMER4_INST_IDX], + NRF_TIMER_CC_CHANNEL_COUNT(4)); +} +#endif + +#endif // NRFX_CHECK(NRFX_TIMER_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uart.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uart.c new file mode 100644 index 0000000..f05643c --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uart.c @@ -0,0 +1,649 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_UART_ENABLED) + +#if !NRFX_CHECK(NRFX_UART0_ENABLED) +#error "No enabled UART instances. Check ." +#endif + +#include +#include "prs/nrfx_prs.h" +#include + +#define NRFX_LOG_MODULE UART +#include + +#define EVT_TO_STR(event) \ + (event == NRF_UART_EVENT_ERROR ? "NRF_UART_EVENT_ERROR" : \ + "UNKNOWN EVENT") + + +#define TX_COUNTER_ABORT_REQ_VALUE UINT32_MAX + +typedef struct +{ + void * p_context; + nrfx_uart_event_handler_t handler; + uint8_t const * p_tx_buffer; + uint8_t * p_rx_buffer; + uint8_t * p_rx_secondary_buffer; + size_t tx_buffer_length; + size_t rx_buffer_length; + size_t rx_secondary_buffer_length; + volatile size_t tx_counter; + volatile size_t rx_counter; + volatile bool tx_abort; + bool rx_enabled; + nrfx_drv_state_t state; +} uart_control_block_t; +static uart_control_block_t m_cb[NRFX_UART_ENABLED_COUNT]; + +static void apply_config(nrfx_uart_t const * p_instance, + nrfx_uart_config_t const * p_config) +{ + if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pseltxd); + nrf_gpio_cfg_output(p_config->pseltxd); + } + if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + } + + nrf_uart_baudrate_set(p_instance->p_reg, p_config->baudrate); + nrf_uart_configure(p_instance->p_reg, p_config->parity, p_config->hwfc); + nrf_uart_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); + if (p_config->hwfc == NRF_UART_HWFC_ENABLED) + { + if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + } + if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + } + nrf_uart_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); + } +} + +static void interrupts_enable(nrfx_uart_t const * p_instance, + uint8_t interrupt_priority) +{ + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_TXDRDY); + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXTO); + nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_TXDRDY | + NRF_UART_INT_MASK_RXTO); + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg), + interrupt_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); +} + +static void interrupts_disable(nrfx_uart_t const * p_instance) +{ + nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_TXDRDY | + NRF_UART_INT_MASK_ERROR | + NRF_UART_INT_MASK_RXTO); + NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); +} + +static void pins_to_default(nrfx_uart_t const * p_instance) +{ + /* Reset pins to default states */ + uint32_t txd; + uint32_t rxd; + uint32_t rts; + uint32_t cts; + + txd = nrf_uart_tx_pin_get(p_instance->p_reg); + rxd = nrf_uart_rx_pin_get(p_instance->p_reg); + rts = nrf_uart_rts_pin_get(p_instance->p_reg); + cts = nrf_uart_cts_pin_get(p_instance->p_reg); + nrf_uart_txrx_pins_disconnect(p_instance->p_reg); + nrf_uart_hwfc_pins_disconnect(p_instance->p_reg); + + if (txd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(txd); + } + if (rxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rxd); + } + if (cts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(cts); + } + if (rts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rts); + } +} + +nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, + nrfx_uart_config_t const * p_config, + nrfx_uart_event_handler_t event_handler) +{ + NRFX_ASSERT(p_config); + uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code = NRFX_SUCCESS; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + static nrfx_irq_handler_t const irq_handlers[NRFX_UART_ENABLED_COUNT] = { + #if NRFX_CHECK(NRFX_UART0_ENABLED) + nrfx_uart_0_irq_handler, + #endif + }; + if (nrfx_prs_acquire(p_instance->p_reg, + irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) + + apply_config(p_instance, p_config); + + p_cb->handler = event_handler; + p_cb->p_context = p_config->p_context; + + if (p_cb->handler) + { + interrupts_enable(p_instance, p_config->interrupt_priority); + } + + nrf_uart_enable(p_instance->p_reg); + p_cb->rx_buffer_length = 0; + p_cb->rx_secondary_buffer_length = 0; + p_cb->rx_enabled = false; + p_cb->tx_buffer_length = 0; + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_uart_uninit(nrfx_uart_t const * p_instance) +{ + uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + nrf_uart_disable(p_instance->p_reg); + + if (p_cb->handler) + { + interrupts_disable(p_instance); + } + + pins_to_default(p_instance); + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + nrfx_prs_release(p_instance->p_reg); +#endif + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; + p_cb->handler = NULL; + NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); +} + +static void tx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) +{ + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY); + uint8_t txd = p_cb->p_tx_buffer[p_cb->tx_counter]; + p_cb->tx_counter++; + nrf_uart_txd_set(p_uart, txd); +} + +static bool tx_blocking(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) +{ + while (p_cb->tx_counter < p_cb->tx_buffer_length) + { + // Wait until the transmitter is ready to accept a new byte. + // Exit immediately if the transfer has been aborted. + while (!nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY)) + { + if (p_cb->tx_abort) + { + return false; + } + } + + tx_byte(p_uart, p_cb); + } + + return true; +} + +nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance, + uint8_t const * p_data, + size_t length) +{ + uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); + NRFX_ASSERT(p_data); + NRFX_ASSERT(length > 0); + + nrfx_err_t err_code; + + if (nrfx_uart_tx_in_progress(p_instance)) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + p_cb->tx_buffer_length = length; + p_cb->p_tx_buffer = p_data; + p_cb->tx_counter = 0; + p_cb->tx_abort = false; + + NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length); + NRFX_LOG_DEBUG("Tx data:"); + NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer, + p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0])); + + err_code = NRFX_SUCCESS; + + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_TXDRDY); + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTTX); + + tx_byte(p_instance->p_reg, p_cb); + + if (p_cb->handler == NULL) + { + if (!tx_blocking(p_instance->p_reg, p_cb)) + { + // The transfer has been aborted. + err_code = NRFX_ERROR_FORBIDDEN; + } + else + { + // Wait until the last byte is completely transmitted. + while (!nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_TXDRDY)) + {} + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPTX); + } + p_cb->tx_buffer_length = 0; + } + + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance) +{ + return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0); +} + +static void rx_enable(nrfx_uart_t const * p_instance) +{ + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_ERROR); + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTRX); +} + +static void rx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb) +{ + if (!p_cb->rx_buffer_length) + { + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY); + // Byte received when buffer is not set - data lost. + (void) nrf_uart_rxd_get(p_uart); + return; + } + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXDRDY); + p_cb->p_rx_buffer[p_cb->rx_counter] = nrf_uart_rxd_get(p_uart); + p_cb->rx_counter++; +} + +nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance, + uint8_t * p_data, + size_t length) +{ + uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); + NRFX_ASSERT(p_data); + NRFX_ASSERT(length > 0); + + nrfx_err_t err_code; + + bool second_buffer = false; + + if (p_cb->handler) + { + nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + } + if (p_cb->rx_buffer_length != 0) + { + if (p_cb->rx_secondary_buffer_length != 0) + { + if (p_cb->handler) + { + nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + } + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + second_buffer = true; + } + + if (!second_buffer) + { + p_cb->rx_buffer_length = length; + p_cb->p_rx_buffer = p_data; + p_cb->rx_counter = 0; + p_cb->rx_secondary_buffer_length = 0; + } + else + { + p_cb->p_rx_secondary_buffer = p_data; + p_cb->rx_secondary_buffer_length = length; + } + + NRFX_LOG_INFO("Transfer rx_len: %d.", length); + + if ((!p_cb->rx_enabled) && (!second_buffer)) + { + rx_enable(p_instance); + } + + if (p_cb->handler == NULL) + { + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_RXTO); + + bool rxrdy; + bool rxto; + bool error; + do + { + do + { + error = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_ERROR); + rxrdy = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); + rxto = nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXTO); + } while ((!rxrdy) && (!rxto) && (!error)); + + if (error || rxto) + { + break; + } + rx_byte(p_instance->p_reg, p_cb); + } while (p_cb->rx_buffer_length > p_cb->rx_counter); + + p_cb->rx_buffer_length = 0; + if (error) + { + err_code = NRFX_ERROR_INTERNAL; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + if (rxto) + { + err_code = NRFX_ERROR_FORBIDDEN; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + if (p_cb->rx_enabled) + { + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STARTRX); + } + else + { + // Skip stopping RX if driver is forced to be enabled. + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); + } + } + else + { + nrf_uart_int_enable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + } + err_code = NRFX_SUCCESS; + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance) +{ + return nrf_uart_event_check(p_instance->p_reg, NRF_UART_EVENT_RXDRDY); +} + +void nrfx_uart_rx_enable(nrfx_uart_t const * p_instance) +{ + if (!m_cb[p_instance->drv_inst_idx].rx_enabled) + { + rx_enable(p_instance); + m_cb[p_instance->drv_inst_idx].rx_enabled = true; + } +} + +void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance) +{ + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); + m_cb[p_instance->drv_inst_idx].rx_enabled = false; +} + +uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance) +{ + nrf_uart_event_clear(p_instance->p_reg, NRF_UART_EVENT_ERROR); + return nrf_uart_errorsrc_get_and_clear(p_instance->p_reg); +} + +static void rx_done_event(uart_control_block_t * p_cb, + size_t bytes, + uint8_t * p_data) +{ + nrfx_uart_event_t event; + + event.type = NRFX_UART_EVT_RX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = p_data; + + p_cb->handler(&event, p_cb->p_context); +} + +static void tx_done_event(uart_control_block_t * p_cb, + size_t bytes) +{ + nrfx_uart_event_t event; + + event.type = NRFX_UART_EVT_TX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer; + + p_cb->tx_buffer_length = 0; + + p_cb->handler(&event, p_cb->p_context); +} + +void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance) +{ + uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + p_cb->tx_abort = true; + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPTX); + if (p_cb->handler) + { + tx_done_event(p_cb, p_cb->tx_counter); + } + + NRFX_LOG_INFO("TX transaction aborted."); +} + +void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance) +{ + nrf_uart_int_disable(p_instance->p_reg, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + nrf_uart_task_trigger(p_instance->p_reg, NRF_UART_TASK_STOPRX); + + NRFX_LOG_INFO("RX transaction aborted."); +} + +static void uart_irq_handler(NRF_UART_Type * p_uart, + uart_control_block_t * p_cb) +{ + if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_ERROR) && + nrf_uart_event_check(p_uart, NRF_UART_EVENT_ERROR)) + { + nrfx_uart_event_t event; + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_ERROR); + NRFX_LOG_DEBUG("Event: %s.", EVT_TO_STR(NRF_UART_EVENT_ERROR)); + nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + if (!p_cb->rx_enabled) + { + nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX); + } + event.type = NRFX_UART_EVT_ERROR; + event.data.error.error_mask = nrf_uart_errorsrc_get_and_clear(p_uart); + event.data.error.rxtx.bytes = p_cb->rx_buffer_length; + event.data.error.rxtx.p_data = p_cb->p_rx_buffer; + + // Abort transfer. + p_cb->rx_buffer_length = 0; + p_cb->rx_secondary_buffer_length = 0; + + p_cb->handler(&event,p_cb->p_context); + } + else if (nrf_uart_int_enable_check(p_uart, NRF_UART_INT_MASK_RXDRDY) && + nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXDRDY)) + { + rx_byte(p_uart, p_cb); + if (p_cb->rx_buffer_length == p_cb->rx_counter) + { + if (p_cb->rx_secondary_buffer_length) + { + uint8_t * p_data = p_cb->p_rx_buffer; + size_t rx_counter = p_cb->rx_counter; + + // Switch to secondary buffer. + p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length; + p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer; + p_cb->rx_secondary_buffer_length = 0; + p_cb->rx_counter = 0; + rx_done_event(p_cb, rx_counter, p_data); + } + else + { + if (!p_cb->rx_enabled) + { + nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STOPRX); + } + nrf_uart_int_disable(p_uart, NRF_UART_INT_MASK_RXDRDY | + NRF_UART_INT_MASK_ERROR); + p_cb->rx_buffer_length = 0; + rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer); + } + } + } + + if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_TXDRDY)) + { + if (p_cb->tx_counter < p_cb->tx_buffer_length && + !p_cb->tx_abort) + { + tx_byte(p_uart, p_cb); + } + else + { + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_TXDRDY); + if (p_cb->tx_buffer_length) + { + tx_done_event(p_cb, p_cb->tx_buffer_length); + } + } + } + + if (nrf_uart_event_check(p_uart, NRF_UART_EVENT_RXTO)) + { + nrf_uart_event_clear(p_uart, NRF_UART_EVENT_RXTO); + + // RXTO event may be triggered as a result of abort call. In th + if (p_cb->rx_enabled) + { + nrf_uart_task_trigger(p_uart, NRF_UART_TASK_STARTRX); + } + if (p_cb->rx_buffer_length) + { + p_cb->rx_buffer_length = 0; + rx_done_event(p_cb, p_cb->rx_counter, p_cb->p_rx_buffer); + } + } +} + +#if NRFX_CHECK(NRFX_UART0_ENABLED) +void nrfx_uart_0_irq_handler(void) +{ + uart_irq_handler(NRF_UART0, &m_cb[NRFX_UART0_INST_IDX]); +} +#endif + +#endif // NRFX_CHECK(NRFX_UART_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uarte.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uarte.c new file mode 100644 index 0000000..ceea3bb --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/nrfx_uarte.c @@ -0,0 +1,632 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_UARTE_ENABLED) + +#if !(NRFX_CHECK(NRFX_UARTE0_ENABLED) || \ + NRFX_CHECK(NRFX_UARTE1_ENABLED) || \ + NRFX_CHECK(NRFX_UARTE2_ENABLED) || \ + NRFX_CHECK(NRFX_UARTE3_ENABLED)) +#error "No enabled UARTE instances. Check ." +#endif + +#include +#include "prs/nrfx_prs.h" +#include + +#define NRFX_LOG_MODULE UARTE +#include + +#define EVT_TO_STR(event) \ + (event == NRF_UARTE_EVENT_ERROR ? "NRF_UARTE_EVENT_ERROR" : \ + "UNKNOWN EVENT") + +#define UARTEX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \ + (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ + NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2)) + +#if NRFX_CHECK(NRFX_UARTE0_ENABLED) +#define UARTE0_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE0, __VA_ARGS__) +#else +#define UARTE0_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_UARTE1_ENABLED) +#define UARTE1_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE1, __VA_ARGS__) +#else +#define UARTE1_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_UARTE2_ENABLED) +#define UARTE2_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE2, __VA_ARGS__) +#else +#define UARTE2_LENGTH_VALIDATE(...) 0 +#endif + +#if NRFX_CHECK(NRFX_UARTE3_ENABLED) +#define UARTE3_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE3, __VA_ARGS__) +#else +#define UARTE3_LENGTH_VALIDATE(...) 0 +#endif + +#define UARTE_LENGTH_VALIDATE(drv_inst_idx, length) \ + (UARTE0_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \ + UARTE1_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \ + UARTE2_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \ + UARTE3_LENGTH_VALIDATE(drv_inst_idx, length, 0)) + + +typedef struct +{ + void * p_context; + nrfx_uarte_event_handler_t handler; + uint8_t const * p_tx_buffer; + uint8_t * p_rx_buffer; + uint8_t * p_rx_secondary_buffer; + volatile size_t tx_buffer_length; + size_t rx_buffer_length; + size_t rx_secondary_buffer_length; + nrfx_drv_state_t state; +} uarte_control_block_t; +static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT]; + +static void apply_config(nrfx_uarte_t const * p_instance, + nrfx_uarte_config_t const * p_config) +{ + if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pseltxd); + nrf_gpio_cfg_output(p_config->pseltxd); + } + if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + } + + nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate); + nrf_uarte_configure(p_instance->p_reg, p_config->parity, p_config->hwfc); + nrf_uarte_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); + if (p_config->hwfc == NRF_UARTE_HWFC_ENABLED) + { + if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + } + if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + } + nrf_uarte_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); + } +} + +static void interrupts_enable(nrfx_uarte_t const * p_instance, + uint8_t interrupt_priority) +{ + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); + nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK | + NRF_UARTE_INT_ENDTX_MASK | + NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_RXTO_MASK); + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg), + interrupt_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); +} + +static void interrupts_disable(nrfx_uarte_t const * p_instance) +{ + nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK | + NRF_UARTE_INT_ENDTX_MASK | + NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_RXTO_MASK); + NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg)); +} + +static void pins_to_default(nrfx_uarte_t const * p_instance) +{ + /* Reset pins to default states */ + uint32_t txd; + uint32_t rxd; + uint32_t rts; + uint32_t cts; + + txd = nrf_uarte_tx_pin_get(p_instance->p_reg); + rxd = nrf_uarte_rx_pin_get(p_instance->p_reg); + rts = nrf_uarte_rts_pin_get(p_instance->p_reg); + cts = nrf_uarte_cts_pin_get(p_instance->p_reg); + nrf_uarte_txrx_pins_disconnect(p_instance->p_reg); + nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg); + + if (txd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(txd); + } + if (rxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rxd); + } + if (cts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(cts); + } + if (rts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rts); + } +} + +nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, + nrfx_uarte_config_t const * p_config, + nrfx_uarte_event_handler_t event_handler) +{ + NRFX_ASSERT(p_config); + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + nrfx_err_t err_code = NRFX_SUCCESS; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + err_code = NRFX_ERROR_INVALID_STATE; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + static nrfx_irq_handler_t const irq_handlers[NRFX_UARTE_ENABLED_COUNT] = { + #if NRFX_CHECK(NRFX_UARTE0_ENABLED) + nrfx_uarte_0_irq_handler, + #endif + #if NRFX_CHECK(NRFX_UARTE1_ENABLED) + nrfx_uarte_1_irq_handler, + #endif + #if NRFX_CHECK(NRFX_UARTE2_ENABLED) + nrfx_uarte_2_irq_handler, + #endif + #if NRFX_CHECK(NRFX_UARTE3_ENABLED) + nrfx_uarte_3_irq_handler, + #endif + }; + if (nrfx_prs_acquire(p_instance->p_reg, + irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) + + apply_config(p_instance, p_config); + + p_cb->handler = event_handler; + p_cb->p_context = p_config->p_context; + + if (p_cb->handler) + { + interrupts_enable(p_instance, p_config->interrupt_priority); + } + + nrf_uarte_enable(p_instance->p_reg); + p_cb->rx_buffer_length = 0; + p_cb->rx_secondary_buffer_length = 0; + p_cb->tx_buffer_length = 0; + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance) +{ + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + nrf_uarte_disable(p_instance->p_reg); + + if (p_cb->handler) + { + interrupts_disable(p_instance); + } + + pins_to_default(p_instance); + +#if NRFX_CHECK(NRFX_PRS_ENABLED) + nrfx_prs_release(p_instance->p_reg); +#endif + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; + p_cb->handler = NULL; + NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx); +} + +nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance, + uint8_t const * p_data, + size_t length) +{ + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED); + NRFX_ASSERT(p_data); + NRFX_ASSERT(length > 0); + NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length)); + + nrfx_err_t err_code; + + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if the are not. + if (!nrfx_is_in_ram(p_data)) + { + err_code = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + if (nrfx_uarte_tx_in_progress(p_instance)) + { + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + p_cb->tx_buffer_length = length; + p_cb->p_tx_buffer = p_data; + + NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length); + NRFX_LOG_DEBUG("Tx data:"); + NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer, + p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0])); + + err_code = NRFX_SUCCESS; + + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); + nrf_uarte_tx_buffer_set(p_instance->p_reg, p_cb->p_tx_buffer, p_cb->tx_buffer_length); + nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTTX); + + if (p_cb->handler == NULL) + { + bool endtx; + bool txstopped; + do + { + endtx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX); + txstopped = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); + } + while ((!endtx) && (!txstopped)); + + if (txstopped) + { + err_code = NRFX_ERROR_FORBIDDEN; + } + p_cb->tx_buffer_length = 0; + } + + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance) +{ + return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0); +} + +nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance, + uint8_t * p_data, + size_t length) +{ + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED); + NRFX_ASSERT(p_data); + NRFX_ASSERT(length > 0); + NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length)); + + nrfx_err_t err_code; + + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if the are not. + if (!nrfx_is_in_ram(p_data)) + { + err_code = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + + bool second_buffer = false; + + if (p_cb->handler) + { + nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_ENDRX_MASK); + } + if (p_cb->rx_buffer_length != 0) + { + if (p_cb->rx_secondary_buffer_length != 0) + { + if (p_cb->handler) + { + nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_ENDRX_MASK); + } + err_code = NRFX_ERROR_BUSY; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + second_buffer = true; + } + + if (!second_buffer) + { + p_cb->rx_buffer_length = length; + p_cb->p_rx_buffer = p_data; + p_cb->rx_secondary_buffer_length = 0; + } + else + { + p_cb->p_rx_secondary_buffer = p_data; + p_cb->rx_secondary_buffer_length = length; + } + + NRFX_LOG_INFO("Transfer rx_len: %d.", length); + + err_code = NRFX_SUCCESS; + + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); + nrf_uarte_rx_buffer_set(p_instance->p_reg, p_data, length); + if (!second_buffer) + { + nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTRX); + } + else + { + nrf_uarte_shorts_enable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX); + } + + if (m_cb[p_instance->drv_inst_idx].handler == NULL) + { + bool endrx; + bool rxto; + bool error; + do { + endrx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); + rxto = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_RXTO); + error = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); + } while ((!endrx) && (!rxto) && (!error)); + + m_cb[p_instance->drv_inst_idx].rx_buffer_length = 0; + + if (error) + { + err_code = NRFX_ERROR_INTERNAL; + } + + if (rxto) + { + err_code = NRFX_ERROR_FORBIDDEN; + } + } + else + { + nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK | + NRF_UARTE_INT_ENDRX_MASK); + } + NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; +} + +bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance) +{ + return nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX); +} + +uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance) +{ + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR); + return nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg); +} + +static void rx_done_event(uarte_control_block_t * p_cb, + size_t bytes, + uint8_t * p_data) +{ + nrfx_uarte_event_t event; + + event.type = NRFX_UARTE_EVT_RX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = p_data; + + p_cb->handler(&event, p_cb->p_context); +} + +static void tx_done_event(uarte_control_block_t * p_cb, + size_t bytes) +{ + nrfx_uarte_event_t event; + + event.type = NRFX_UARTE_EVT_TX_DONE; + event.data.rxtx.bytes = bytes; + event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer; + + p_cb->tx_buffer_length = 0; + + p_cb->handler(&event, p_cb->p_context); +} + +void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance) +{ + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED); + nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX); + if (p_cb->handler == NULL) + { + while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED)) + {} + } + NRFX_LOG_INFO("TX transaction aborted."); +} + +void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance) +{ + uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + // Short between ENDRX event and STARTRX task must be disabled before + // aborting transmission. + if (p_cb->rx_secondary_buffer_length != 0) + { + nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX); + } + nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX); + NRFX_LOG_INFO("RX transaction aborted."); +} + +static void uarte_irq_handler(NRF_UARTE_Type * p_uarte, + uarte_control_block_t * p_cb) +{ + if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ERROR)) + { + nrfx_uarte_event_t event; + + nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ERROR); + + event.type = NRFX_UARTE_EVT_ERROR; + event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(p_uarte); + event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte); + event.data.error.rxtx.p_data = p_cb->p_rx_buffer; + + // Abort transfer. + p_cb->rx_buffer_length = 0; + p_cb->rx_secondary_buffer_length = 0; + + p_cb->handler(&event, p_cb->p_context); + } + else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX)) + { + nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX); + size_t amount = nrf_uarte_rx_amount_get(p_uarte); + // If the transfer was stopped before completion, amount of transfered bytes + // will not be equal to the buffer length. Interrupted transfer is ignored. + if (amount == p_cb->rx_buffer_length) + { + if (p_cb->rx_secondary_buffer_length != 0) + { + uint8_t * p_data = p_cb->p_rx_buffer; + nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX); + p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length; + p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer; + p_cb->rx_secondary_buffer_length = 0; + rx_done_event(p_cb, amount, p_data); + } + else + { + p_cb->rx_buffer_length = 0; + rx_done_event(p_cb, amount, p_cb->p_rx_buffer); + } + } + } + + if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO)) + { + nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO); + + if (p_cb->rx_buffer_length != 0) + { + p_cb->rx_buffer_length = 0; + // In case of using double-buffered reception both variables storing buffer length + // have to be cleared to prevent incorrect behaviour of the driver. + p_cb->rx_secondary_buffer_length = 0; + rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer); + } + } + + if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX)) + { + nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX); + if (p_cb->tx_buffer_length != 0) + { + tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte)); + } + } +} + +#if NRFX_CHECK(NRFX_UARTE0_ENABLED) +void nrfx_uarte_0_irq_handler(void) +{ + uarte_irq_handler(NRF_UARTE0, &m_cb[NRFX_UARTE0_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_UARTE1_ENABLED) +void nrfx_uarte_1_irq_handler(void) +{ + uarte_irq_handler(NRF_UARTE1, &m_cb[NRFX_UARTE1_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_UARTE2_ENABLED) +void nrfx_uarte_2_irq_handler(void) +{ + uarte_irq_handler(NRF_UARTE2, &m_cb[NRFX_UARTE2_INST_IDX]); +} +#endif + +#if NRFX_CHECK(NRFX_UARTE3_ENABLED) +void nrfx_uarte_3_irq_handler(void) +{ + uarte_irq_handler(NRF_UARTE3, &m_cb[NRFX_UARTE3_INST_IDX]); +} +#endif + +#endif // NRFX_CHECK(NRFX_UARTE_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c b/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c new file mode 100644 index 0000000..34e7d4b --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.c @@ -0,0 +1,166 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include + +#if NRFX_CHECK(NRFX_PRS_ENABLED) +#include "nrfx_prs.h" + +#define NRFX_LOG_MODULE PRS +#include + +#define LOG_FUNCTION_EXIT(level, ret_code) \ + NRFX_LOG_##level("Function: %s, error code: %s.", \ + __func__, \ + NRFX_LOG_ERROR_STRING_GET(ret_code)) + + +typedef struct { + nrfx_irq_handler_t handler; + bool acquired; +} prs_box_t; + +#define PRS_BOX_DEFINE(n) \ + static prs_box_t m_prs_box_##n = { .handler = NULL, .acquired = false }; \ + void nrfx_prs_box_##n##_irq_handler(void) \ + { \ + NRFX_ASSERT(m_prs_box_##n.handler); \ + m_prs_box_##n.handler(); \ + } + +#if defined(NRFX_PRS_BOX_0_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +PRS_BOX_DEFINE(0) +#endif +#if defined(NRFX_PRS_BOX_1_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +PRS_BOX_DEFINE(1) +#endif +#if defined(NRFX_PRS_BOX_2_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +PRS_BOX_DEFINE(2) +#endif +#if defined(NRFX_PRS_BOX_3_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +PRS_BOX_DEFINE(3) +#endif +#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +PRS_BOX_DEFINE(4) +#endif + + +static prs_box_t * prs_box_get(void const * p_base_addr) +{ +#if !defined(IS_PRS_BOX) +#define IS_PRS_BOX(n, p_base_addr) ((p_base_addr) == NRFX_PRS_BOX_##n##_ADDR) +#endif + +#if defined(NRFX_PRS_BOX_0_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) + if (IS_PRS_BOX(0, p_base_addr)) { return &m_prs_box_0; } + else +#endif +#if defined(NRFX_PRS_BOX_1_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) + if (IS_PRS_BOX(1, p_base_addr)) { return &m_prs_box_1; } + else +#endif +#if defined(NRFX_PRS_BOX_2_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) + if (IS_PRS_BOX(2, p_base_addr)) { return &m_prs_box_2; } + else +#endif +#if defined(NRFX_PRS_BOX_3_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) + if (IS_PRS_BOX(3, p_base_addr)) { return &m_prs_box_3; } + else +#endif +#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) + if (IS_PRS_BOX(4, p_base_addr)) { return &m_prs_box_4; } + else +#endif + { + return NULL; + } +} + +nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, + nrfx_irq_handler_t irq_handler) +{ + NRFX_ASSERT(p_base_addr); + + nrfx_err_t ret_code; + + prs_box_t * p_box = prs_box_get(p_base_addr); + if (p_box != NULL) + { + bool busy = false; + + NRFX_CRITICAL_SECTION_ENTER(); + if (p_box->acquired) + { + busy = true; + } + else + { + p_box->handler = irq_handler; + p_box->acquired = true; + } + NRFX_CRITICAL_SECTION_EXIT(); + + if (busy) + { + ret_code = NRFX_ERROR_BUSY; + LOG_FUNCTION_EXIT(WARNING, ret_code); + return ret_code; + } + } + + ret_code = NRFX_SUCCESS; + LOG_FUNCTION_EXIT(INFO, ret_code); + return ret_code; +} + +void nrfx_prs_release(void const * p_base_addr) +{ + NRFX_ASSERT(p_base_addr); + + prs_box_t * p_box = prs_box_get(p_base_addr); + if (p_box != NULL) + { + p_box->handler = NULL; + p_box->acquired = false; + } +} + + +#endif // NRFX_CHECK(NRFX_PRS_ENABLED) diff --git a/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h b/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h new file mode 100644 index 0000000..f6b2e6e --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/drivers/src/prs/nrfx_prs.h @@ -0,0 +1,158 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_PRS_H__ +#define NRFX_PRS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_prs Peripheral Resource Sharing (PRS) + * @{ + * @ingroup nrfx + * + * @brief Peripheral Resource Sharing interface (PRS). + */ + +#if defined(NRF51) + // SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 + // SPI1, SPIS1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 +#elif defined(NRF52810_XXAA) + // TWIM0, TWIS0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 + // SPIM0, SPIS0, SPI0 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UARTE0, UART0 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 +#elif defined(NRF52811_XXAA) + // TWIM0, TWIS0, TWI0, SPIM1, SPIS1, SPI1 + #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 + // SPIM0, SPIS0, SPI0 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UART0, UARTE0 + #define NRFX_PRS_BOX_2_ADDR NRF_UART0 +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 + // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 + // SPIM2, SPIS2, SPI2 + #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 + // COMP, LPCOMP + #define NRFX_PRS_BOX_3_ADDR NRF_COMP + // UARTE0, UART0 + #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 +#elif defined(NRF52840_XXAA) + // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 + #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 + // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1 + // SPIM2, SPIS2, SPI2 + #define NRFX_PRS_BOX_2_ADDR NRF_SPIM2 + // COMP, LPCOMP + #define NRFX_PRS_BOX_3_ADDR NRF_COMP + // UARTE0, UART0 + #define NRFX_PRS_BOX_4_ADDR NRF_UARTE0 +#elif defined(NRF9160_XXAA) + // UARTE0, SPIM0, SPIS0, TWIM0, TWIS0 + #define NRFX_PRS_BOX_0_ADDR NRF_UARTE0 + // UARTE1, SPIM1, SPIS1, TWIM1, TWIS1 + #define NRFX_PRS_BOX_1_ADDR NRF_UARTE1 + // UARTE2, SPIM2, SPIS2, TWIM2, TWIS2 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE2 + // UARTE3, SPIM3, SPIS3, TWIM3, TWIS3 + #define NRFX_PRS_BOX_3_ADDR NRF_UARTE3 +#else + #error "Unknown device." +#endif + +/** + * @brief Function for acquiring shared peripheral resources associated with + * the specified peripheral. + * + * Certain resources and registers are shared among peripherals that have + * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0 in + * nRF52832). Only one of them can be utilized at a given time. This function + * reserves proper resources to be used by the specified peripheral. + * If NRFX_PRS_ENABLED is set to a non-zero value, IRQ handlers for peripherals + * that are sharing resources with others are implemented by the @ref nrfx_prs + * module instead of individual drivers. The drivers must then specify their + * interrupt handling routines and register them by using this function. + * + * @param[in] p_base_addr Requested peripheral base pointer. + * @param[in] irq_handler Interrupt handler to register. + * + * @retval NRFX_SUCCESS If resources were acquired successfully or the + * specified peripheral is not handled by the PRS + * subsystem and there is no need to acquire resources + * for it. + * @retval NRFX_ERROR_BUSY If resources were already acquired. + */ +nrfx_err_t nrfx_prs_acquire(void const * p_base_addr, + nrfx_irq_handler_t irq_handler); + +/** + * @brief Function for releasing shared resources reserved previously by + * @ref nrfx_prs_acquire() for the specified peripheral. + * + * @param[in] p_base_addr Released peripheral base pointer. + */ +void nrfx_prs_release(void const * p_base_addr); + + +void nrfx_prs_box_0_irq_handler(void); +void nrfx_prs_box_1_irq_handler(void); +void nrfx_prs_box_2_irq_handler(void); +void nrfx_prs_box_3_irq_handler(void); +void nrfx_prs_box_4_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PRS_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpio.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpio.h new file mode 100644 index 0000000..c7c4178 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpio.h @@ -0,0 +1,840 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_GPIO_H__ +#define NRF_GPIO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_gpio_hal GPIO HAL + * @{ + * @ingroup nrf_gpio + * @brief Hardware access layer for managing the GPIO peripheral. + */ + +#ifndef NRF_P0 +#define NRF_P0 NRF_GPIO +#endif + +#if (GPIO_COUNT == 1) +#define NUMBER_OF_PINS (P0_PIN_NUM) +#define GPIO_REG_LIST {NRF_P0} +#elif (GPIO_COUNT == 2) +#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) +#define GPIO_REG_LIST {NRF_P0, NRF_P1} +#else +#error "Not supported." +#endif + + +/** + * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. + */ +#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) + +/** + * @brief Pin direction definitions. + */ +typedef enum +{ + NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input. + NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output. +} nrf_gpio_pin_dir_t; + +/** + * @brief Connection of input buffer. + */ +typedef enum +{ + NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer. + NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer. +} nrf_gpio_pin_input_t; + +/** + * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration. + */ +typedef enum +{ + NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled. + NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled. + NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled. +} nrf_gpio_pin_pull_t; + +/** + * @brief Enumerator used for selecting output drive mode. + */ +typedef enum +{ + NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. + NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. + NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. + NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. + NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. + NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. + NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. + NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. +} nrf_gpio_pin_drive_t; + +/** + * @brief Enumerator used for selecting the pin to sense high or low level on the pin input. + */ +typedef enum +{ + NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. + NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. + NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. +} nrf_gpio_pin_sense_t; + +/** + * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. + * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output. + * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); + +/** + * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input. + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + * + * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input. + * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + */ +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Pin configuration function. + * + * The main pin configuration function. + * This function allows to set any aspect in PIN_CNF register. + * @param pin_number Specifies the pin number. + * @param dir Pin direction. + * @param input Connect or disconnect the input buffer. + * @param pull Pull configuration. + * @param drive Drive configuration. + * @param sense Pin sensing mechanism. + */ +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense); + +/** + * @brief Function for configuring the given GPIO pin number as output, hiding inner details. + * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_number Specifies the pin number. + * + * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure a pin as simple input. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + * + * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + */ +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Function for resetting pin configuration to its default state. + * + * @param pin_number Specifies the pin number. + */ +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. + * + * @param pin_number Specifies the pin number. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); + +/** + * @brief Function for disconnecting input for the given GPIO. + * + * @param pin_number Specifies the pin number. + * + */ +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure pin range as simple input. + * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). + * @param sense_config Sense level of the pin (no sense, sense low, or sense high). + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for configuring sense level for the given GPIO. + * + * @param pin_number Specifies the pin number. + * @param sense_config Sense configuration. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for setting the direction for a GPIO pin. + * + * @param pin_number Specifies the pin number for which to set the direction. + * + * @param direction Specifies the direction. + */ +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); + +/** + * @brief Function for setting a GPIO pin. + * + * Note that the pin must be configured as an output for this function to have any effect. + * + * @param pin_number Specifies the pin number to set. + */ +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); + +/** + * @brief Function for clearing a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to clear. + */ +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); + +/** + * @brief Function for toggling a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to toggle. + */ +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); + +/** + * @brief Function for writing a value to a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to write. + * + * @param value Specifies the value to be written to the pin. + * @arg 0 Clears the pin. + * @arg >=1 Sets the pin. + */ +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); + +/** + * @brief Function for reading the input level of a GPIO pin. + * + * Note that the pin must have input connected for the value + * returned from this function to be valid. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin input level is low. Positive value if the pin is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); + +/** + * @brief Function for reading the output level of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin output level is low. Positive value if pin output is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); + +/** + * @brief Function for reading the sense configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Sense configuration. + */ +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); + +/** + * @brief Function for reading the direction configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Direction configuration. + */ +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); + +/** + * @brief Function for reading the status of GPIO pin input buffer. + * + * @param pin_number Pin number to be read. + * + * @retval Input buffer configuration. + */ +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); + +/** + * @brief Function for reading the pull configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Pull configuration. + */ +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); + +/** + * @brief Function for setting output direction on selected pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param out_mask Mask specifying the pins to set as output. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); + +/** + * @brief Function for setting input direction on selected pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param in_mask Mask specifying the pins to set as input. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); + +/** + * @brief Function for writing the direction configuration of GPIO pins in a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); + +/** + * @brief Function for reading the direction configuration of a GPIO port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the input signals of GPIO pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Port input values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the output signals of GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Port output values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for writing the GPIO pins output on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param value Output port mask. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); + +/** + * @brief Function for setting high level on selected GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param set_mask Mask with pins to set as logical high level. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); + +/** + * @brief Function for setting low level on selected GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param clr_mask Mask with pins to set as logical low level. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); + +/** + * @brief Function for reading pins state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where port states will be stored. + */ +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); + +#if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__) +/** + * @brief Function for reading latch state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where latch states will be stored. + */ +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, + uint32_t * p_masks); + +/** + * @brief Function for reading latch state of single pin. + * + * @param pin_number Pin number. + * @return 0 if latch is not set. Positive value otherwise. + * + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); + +/** + * @brief Function for clearing latch state of a single pin. + * + * @param pin_number Pin number. + * + */ +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); +#endif + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/** + * @brief Function for extracting port and relative pin number from absolute pin number. + * + * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number. + * + * @return Pointer to port register set. + * + */ +__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) +{ + NRFX_ASSERT(*p_pin < NUMBER_OF_PINS); +#if (GPIO_COUNT == 1) + return NRF_P0; +#else + if (*p_pin < P0_PIN_NUM) + { + return NRF_P0; + } + else + { + *p_pin = *p_pin & (P0_PIN_NUM - 1); + return NRF_P1; + } +#endif +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_output(pin_range_start); + } +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_input(pin_range_start, pull_config); + } +} + + +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + sense_config); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; + reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) +{ + if (direction == NRF_GPIO_PIN_DIR_INPUT) + { + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + else + { + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + reg->DIRSET = (1UL << pin_number); + } +} + + +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_set(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_clear(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t pins_state = reg->OUT; + + reg->OUTSET = (~pins_state & (1UL << pin_number)); + reg->OUTCLR = (pins_state & (1UL << pin_number)); +} + + +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) +{ + if (value == 0) + { + nrf_gpio_pin_clear(pin_number); + } + else + { + nrf_gpio_pin_set(pin_number); + } +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); +} + +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos); +} + +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos); +} + + +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) +{ + p_reg->DIRSET = out_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) +{ + p_reg->DIRCLR = in_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->DIR = value; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->DIR; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->IN; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->OUT; +} + + +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->OUT = value; +} + + +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) +{ + p_reg->OUTSET = set_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) +{ + p_reg->OUTCLR = clr_mask; +} + + +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + + NRFX_ASSERT(start_port + length <= GPIO_COUNT); + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = nrf_gpio_port_in_read(gpio_regs[i]); + p_masks++; + } +} + + +#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = gpio_regs[i]->LATCH; + p_masks++; + } +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (reg->LATCH & (1 << pin_number)) ? 1 : 0; +} + + +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->LATCH = (1 << pin_number); +} + + +#endif +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_GPIO_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpiote.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpiote.h new file mode 100644 index 0000000..8d10d51 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_gpiote.h @@ -0,0 +1,506 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_GPIOTE_H__ +#define NRF_GPIOTE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @defgroup nrf_gpiote_hal GPIOTE HAL +* @{ +* @ingroup nrf_gpiote +* @brief Hardware access layer for managing the GPIOTE peripheral. +*/ + +#ifdef GPIOTE_CONFIG_PORT_Msk +#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk) +#else +#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk +#endif + + /** + * @enum nrf_gpiote_polarity_t + * @brief Polarity for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high. + NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low. + NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle. +} nrf_gpiote_polarity_t; + + + /** + * @enum nrf_gpiote_outinit_t + * @brief Initial output value for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high. + NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low. +} nrf_gpiote_outinit_t; + +/** + * @brief Tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/ + NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/ + NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/ + NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/ + NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/ + NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/ + NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/ +#endif +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/ + NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/ + NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/ + NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/ + NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/ + NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/ + NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/ + NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/ +#endif +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/ + NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/ + NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/ + NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/ + NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/ + NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/ + NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/ + NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/ +#endif + /*lint -restore*/ +} nrf_gpiote_tasks_t; + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/ + NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/ + NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/ + NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/ + NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/ + NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/ + NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/ +#endif + NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/ + /*lint -restore*/ +} nrf_gpiote_events_t; + +/** + * @enum nrf_gpiote_int_t + * @brief GPIOTE interrupts. + */ +typedef enum +{ + NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */ + NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */ + NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */ + NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */ + NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */ + NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */ + NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */ +#endif + NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */ +} nrf_gpiote_int_t; + +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK) +#if (GPIOTE_CH_NUM > 4) +#undef NRF_GPIOTE_INT_IN_MASK +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\ + NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\ + NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK) +#endif + +/** + * @brief Function for activating a specific GPIOTE task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the address of a specific GPIOTE task. + * + * @param[in] task Task. + * + * @returns Address. + */ +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the state of a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event); + +/** + * @brief Function for clearing a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event); + +/** + * @brief Function for getting the address of a specific GPIOTE event. + * + * @param[in] event Event. + * + * @return Address + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event); + +/**@brief Function for enabling interrupts. + * + * @param[in] mask Interrupt mask to be enabled. + */ +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask); + +/**@brief Function for disabling interrupts. + * + * @param[in] mask Interrupt mask to be disabled. + */ +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask); + +/**@brief Function for checking if interrupts are enabled. + * + * @param[in] mask Mask of interrupt flags to check. + * + * @return Mask with enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask); + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * GPIOTE task. + * + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +__STATIC_INLINE void nrf_gpiote_subscribe_set(nrf_gpiote_tasks_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * GPIOTE task. + * + * @param[in] task Task for which to clear the configuration. + */ +__STATIC_INLINE void nrf_gpiote_subscribe_clear(nrf_gpiote_tasks_t task); + +/** + * @brief Function for setting the publish configuration for a given + * GPIOTE event. + * + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +__STATIC_INLINE void nrf_gpiote_publish_set(nrf_gpiote_events_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * GPIOTE event. + * + * @param[in] event Event for which to clear the configuration. + */ +__STATIC_INLINE void nrf_gpiote_publish_clear(nrf_gpiote_events_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +/**@brief Function for enabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE event. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + */ +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity); + +/**@brief Function for getting the pin associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Pin number. + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx); + +/**@brief Function for getting the polarity associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Polarity. + */ +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx); + +/**@brief Function for enabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE task. + * @note Function is not configuring mode field so task is disabled after this function is called. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + * @param[in] init_val Initial value of the pin. + */ +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val); + +/**@brief Function for forcing a specific state on the pin connected to GPIOTE. + * + * @param[in] idx Task-Event index. + * @param[in] init_val Pin state. + */ +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val); + +/**@brief Function for resetting a GPIOTE task event configuration to the default state. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx); + +/**@brief Function for checking if particular Task-Event is enabled. + * + * @param[in] idx Task-Event index. + * + * @retval true If the Task-Event mode is set to Task or Event. + * @retval false If the Task-Event mode is set to Disabled. + */ +__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task) +{ + *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task) +{ + return ((uint32_t)NRF_GPIOTE + task); +} + +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event) +{ + return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false; +} + +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event) +{ + *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event) +{ + return ((uint32_t)NRF_GPIOTE + event); +} + +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask) +{ + NRF_GPIOTE->INTENSET = mask; +} + +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask) +{ + NRF_GPIOTE->INTENCLR = mask; +} + +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask) +{ + return (NRF_GPIOTE->INTENSET & mask); +} + +#if defined(DPPI_PRESENT) +__STATIC_INLINE void nrf_gpiote_subscribe_set(nrf_gpiote_tasks_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) task + 0x80uL)) = + ((uint32_t)channel | GPIOTE_SUBSCRIBE_OUT_EN_Msk); +} + +__STATIC_INLINE void nrf_gpiote_subscribe_clear(nrf_gpiote_tasks_t task) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) task + 0x80uL)) = 0; +} + +__STATIC_INLINE void nrf_gpiote_publish_set(nrf_gpiote_events_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) event + 0x80uL)) = + ((uint32_t)channel | GPIOTE_PUBLISH_IN_EN_Msk); +} + +__STATIC_INLINE void nrf_gpiote_publish_clear(nrf_gpiote_events_t event) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_GPIOTE + (uint32_t) event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx) +{ + return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos); +} + +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx) +{ + return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos); +} + +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx) +{ + uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; +#ifdef NRF51 + /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens + on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the + correct state in GPIOTE but not in the OUT register. */ + /* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */ + NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk); + __NOP(); + __NOP(); + __NOP(); +#endif + NRF_GPIOTE->CONFIG[idx] = final_config; +} + +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task; +} + +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | + GPIOTE_CONFIG_POLARITY_Msk | + GPIOTE_CONFIG_OUTINIT_Msk); + + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) | + ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) + | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] = 0; +} + +__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx) +{ + return (NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.c b/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.c new file mode 100644 index 0000000..cb472af --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.c @@ -0,0 +1,133 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/** + *@file + *@brief NMVC driver implementation + */ + +#include +#include "nrf_nvmc.h" + +static inline void wait_for_flash_ready(void) +{ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;} +} + +void nrf_nvmc_page_erase(uint32_t address) +{ + // Enable erase. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; + __ISB(); + __DSB(); + + // Erase the page + NRF_NVMC->ERASEPAGE = address; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value) +{ + uint32_t byte_shift = address & (uint32_t)0x03; + uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. + uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); + value32 = value32 + ((uint32_t)value << (byte_shift << 3)); + + // Enable write. + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); + + *(uint32_t*)address32 = value32; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_word(uint32_t address, uint32_t value) +{ + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + *(uint32_t*)address = value; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) +{ + uint32_t i; + for (i = 0; i < num_bytes; i++) + { + nrf_nvmc_write_byte(address + i,src[i]); + } +} + +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words) +{ + uint32_t i; + + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + for (i = 0; i < num_words; i++) + { + ((uint32_t*)address)[i] = src[i]; + wait_for_flash_ready(); + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.h new file mode 100644 index 0000000..72d2e49 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_nvmc.h @@ -0,0 +1,119 @@ +/** + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_NVMC_H__ +#define NRF_NVMC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup nrf_nvmc_hal NVMC HAL + * @{ + * @ingroup nrf_nvmc + * @brief Hardware access layer for managing the Non-Volatile Memory Controller (NVMC) peripheral. + * + * This driver allows writing to the non-volatile memory (NVM) regions + * of the chip. In order to write to NVM the controller must be powered + * on and the relevant page must be erased. + * + */ + + +/** + * @brief Erase a page in flash. This is required before writing to any + * address in the page. + * + * @param address Start address of the page. + */ +void nrf_nvmc_page_erase(uint32_t address); + + +/** + * @brief Write a single byte to flash. + * + * The function reads the word containing the byte, and then + * rewrites the entire word. + * + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_byte(uint32_t address , uint8_t value); + + +/** + * @brief Write a 32-bit word to flash. + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_word(uint32_t address, uint32_t value); + + +/** + * @brief Write consecutive bytes to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_bytes Number of bytes in src to write. + */ +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); + + +/** + * @brief Write consecutive words to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_words Number of words in src to write. + */ +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVMC_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_spi.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_spi.h new file mode 100644 index 0000000..2ef3902 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_spi.h @@ -0,0 +1,383 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_SPI_H__ +#define NRF_SPI_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_spi_hal SPI HAL + * @{ + * @ingroup nrf_spi + * @brief Hardware access layer for managing the SPI peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received. + /*lint -restore*/ +} nrf_spi_event_t; + +/** + * @brief SPI interrupts. + */ +typedef enum +{ + NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk, ///< Interrupt on READY event. + NRF_SPI_ALL_INTS_MASK = SPI_INTENSET_READY_Msk ///< All SPI interrupts. +} nrf_spi_int_mask_t; + +/** + * @brief SPI data rates. + */ +typedef enum +{ + NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps. +} nrf_spi_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spi_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spi_bit_order_t; + + +/** + * @brief Function for clearing a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Event to clear. + */ +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for checking the state of a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for getting the address of a specific SPI event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, + nrf_spi_int_mask_t spi_int); + +/** + * @brief Function for enabling the SPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg); + +/** + * @brief Function for disabling the SPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg); + +/** + * @brief Function for configuring SPI pins. + * + * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +/** + * @brief Function for writing data to the SPI transmitter register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] data TX data to send. + */ +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data); + +/** + * @brief Function for reading data from the SPI receiver register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return RX data received. + */ +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg); + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, + nrf_spi_frequency_t frequency); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); +} + +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); +} + +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask) +{ + p_reg->INTENSET = spi_int_mask; +} + +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask) +{ + p_reg->INTENCLR = spi_int_mask; +} + +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, + nrf_spi_int_mask_t spi_int) +{ + return (bool)(p_reg->INTENSET & spi_int); +} + +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg) +{ + p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg) +{ + p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ +#if defined(SPI_PSEL_SCK_CONNECT_Pos) + p_reg->PSEL.SCK = sck_pin; +#else + p_reg->PSELSCK = sck_pin; +#endif + +#if defined(SPI_PSEL_MOSI_CONNECT_Pos) + p_reg->PSEL.MOSI = mosi_pin; +#else + p_reg->PSELMOSI = mosi_pin; +#endif + +#if defined(SPI_PSEL_MISO_CONNECT_Pos) + p_reg->PSEL.MISO = miso_pin; +#else + p_reg->PSELMISO = miso_pin; +#endif +} + +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data) +{ + p_reg->TXD = data; +} + +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg) +{ + return p_reg->RXD; +} + +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, + nrf_spi_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ? + SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPI_MODE_0: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_1: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_2: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_3: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + } + p_reg->CONFIG = config; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SPI_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_spim.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_spim.h new file mode 100644 index 0000000..c85a2bc --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_spim.h @@ -0,0 +1,812 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_SPIM_H__ +#define NRF_SPIM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_spim_hal SPIM HAL + * @{ + * @ingroup nrf_spim + * @brief Hardware access layer for managing the SPIM peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF + +#if defined(SPIM_DCXCNT_DCXCNT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief This value specified in the DCX line configuration causes this line + * to be set low during whole transmission (all transmitted bytes are + * marked as command bytes). Any lower value causes the DCX line to be + * switched from low to high after this number of bytes is transmitted + * (all remaining bytes are marked as data bytes). + */ +#define NRF_SPIM_DCX_CNT_ALL_CMD 0xF +#endif + +#define NRF_SPIM_HW_CSN_PRESENT \ + (NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT)) + +/** + * @brief SPIM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction. + NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction. + NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction. + NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction. + /*lint -restore*/ +} nrf_spim_task_t; + +/** + * @brief SPIM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped. + NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached. + NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached. + NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached. + NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started. + /*lint -restore*/ +} nrf_spim_event_t; + +/** + * @brief SPIM shortcuts. + */ +typedef enum +{ + NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task. + NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk ///< All SPIM shortcuts. +} nrf_spim_short_mask_t; + +/** + * @brief SPIM interrupts. + */ +typedef enum +{ + NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. + NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event. + NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event. + NRF_SPIM_ALL_INTS_MASK = SPIM_INTENSET_STOPPED_Msk | + SPIM_INTENSET_ENDRX_Msk | + SPIM_INTENSET_END_Msk | + SPIM_INTENSET_ENDTX_Msk | + SPIM_INTENSET_STARTED_Msk ///< All SPIM interrupts. +} nrf_spim_int_mask_t; + +/** + * @brief SPI master data rates. + */ +typedef enum +{ + NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps. +#if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__) + NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps. +#endif +#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__) + NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps. +#endif +} nrf_spim_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spim_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spim_bit_order_t; + +#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief SPI CSN pin polarity. + */ +typedef enum +{ + NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high). + NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low). +} nrf_spim_csn_pol_t; +#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for activating a specific SPIM task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_task Task to activate. + */ +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task); + +/** + * @brief Function for getting the address of a specific SPIM task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task); + +/** + * @brief Function for clearing a specific SPIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Event to clear. + */ +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); + +/** + * @brief Function for checking the state of a specific SPIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); + +/** + * @brief Function for getting the address of a specific SPIM event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask); + +/** + * @brief Function for getting shorts setting. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, + nrf_spim_int_mask_t spim_int); + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * SPIM task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +__STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg, + nrf_spim_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * SPIM task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to clear the configuration. + */ +__STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg, + nrf_spim_task_t task); + +/** + * @brief Function for setting the publish configuration for a given + * SPIM event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +__STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg, + nrf_spim_event_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * SPIM event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to clear the configuration. + */ +__STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for enabling the SPIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the SPIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for configuring SPIM pins. + * + * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the SPIM hardware CSN pin. + * + * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pin CSN pin number. + * @param[in] polarity CSN pin polarity. + * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK + * and minimum duration of CSN must stay unselected between transactions. + * The value is specified in number of 64 MHz clock cycles (15.625 ns). + */ +__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, + uint32_t pin, + nrf_spim_csn_pol_t polarity, + uint32_t duration); +#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the SPIM DCX pin. + * + * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] dcx_pin DCX pin number. + */ +__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_pin); + +/** + * @brief Function for configuring the number of command bytes. + * + * Maximum value available for dividing the transmitted bytes into command + * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. + * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter + * causes all transmitted bytes to be marked as command bytes. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] count Number of command bytes preceding the data bytes. + */ +__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, + uint32_t count); +#endif // defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the extended SPIM interface. + * @param p_reg Pointer to the peripheral registers structure. + * @param rxdelay Sample delay for input serial data on MISO, + * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK. + */ +__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, + uint32_t rxdelay); +#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for clearing stall status for RX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for getting stall status for RX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Stall status of RX EasyDMA RAM accesses. + */ +__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg); +#endif // defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for clearing stall status for TX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for getting stall status for TX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Stall status of TX EasyDMA RAM accesses. + */ +__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg); +#endif // defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, + nrf_spim_frequency_t frequency); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] orc Over-read character that is clocked out in case of + * an over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, + uint8_t orc); + +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task); +} + +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event); +} + +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event); +} + +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask) +{ + p_reg->SHORTS |= spim_shorts_mask; +} + +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask) +{ + p_reg->SHORTS &= ~(spim_shorts_mask); +} + +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg) +{ + return p_reg->SHORTS; +} + +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask) +{ + p_reg->INTENSET = spim_int_mask; +} + +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask) +{ + p_reg->INTENCLR = spim_int_mask; +} + +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, + nrf_spim_int_mask_t spim_int) +{ + return (bool)(p_reg->INTENSET & spim_int); +} + +#if defined(DPPI_PRESENT) +__STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg, + nrf_spim_task_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = + ((uint32_t)channel | SPIM_SUBSCRIBE_START_EN_Msk); +} + +__STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg, + nrf_spim_task_t task) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; +} + +__STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg, + nrf_spim_event_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = + ((uint32_t)channel | SPIM_PUBLISH_STARTED_EN_Msk); +} + +__STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t event) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ + p_reg->PSEL.SCK = sck_pin; + p_reg->PSEL.MOSI = mosi_pin; + p_reg->PSEL.MISO = miso_pin; +} + +#if (NRF_SPIM_HW_CSN_PRESENT) +__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, + uint32_t pin, + nrf_spim_csn_pol_t polarity, + uint32_t duration) +{ + p_reg->PSEL.CSN = pin; + p_reg->CSNPOL = polarity; + p_reg->IFTIMING.CSNDUR = duration; +} +#endif // defined(NRF_SPIM_HW_CSN_PRESENT) + +#if defined(SPIM_PSELDCX_CONNECT_Msk) +__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_pin) +{ + p_reg->PSELDCX = dcx_pin; +} + +__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_cnt) +{ + p_reg->DCXCNT = dcx_cnt; +} +#endif // defined(SPIM_PSELDCX_CONNECT_Msk) + +#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) +__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, + uint32_t rxdelay) +{ + p_reg->IFTIMING.RXDELAY = rxdelay; +} +#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) + +#if defined(SPIM_STALLSTAT_RX_Msk) +__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg) +{ + p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk); +} + +__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg) +{ + return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0; +} +#endif // defined(SPIM_STALLSTAT_RX_Msk) + +#if defined(SPIM_STALLSTAT_TX_Msk) +__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg) +{ + p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk); +} + +__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg) +{ + return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0; +} +#endif // defined(SPIM_STALLSTAT_TX_Msk) + +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, + nrf_spim_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ? + SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPIM_MODE_0: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_1: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_2: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_3: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + } + p_reg->CONFIG = config; +} + +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, + uint8_t orc) +{ + p_reg->ORC = orc; +} + + +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->TXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->TXD.LIST = 0; +} + +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->RXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->RXD.LIST = 0; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SPIM_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_systick.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_systick.h new file mode 100644 index 0000000..9c493c9 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_systick.h @@ -0,0 +1,190 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_SYSTICK_H__ +#define NRF_SYSTICK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_systick_hal SYSTICK HAL + * @{ + * @ingroup nrf_systick + * @brief Hardware access layer for managing the SYSTICK peripheral. + * + * SYSTICK is ARM peripheral, not Nordic design. + * It means that it has no Nordic-typical interface with Tasks and Events. + * + * Its usage is limited here to implement simple delays. + * Also keep in mind that this timer would be stopped when CPU is sleeping + * (WFE/WFI instruction is successfully executed). + */ + +/** + * @brief Mask of usable bits in the SysTick value + */ +#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk + +/** + * @brief Flags used by SysTick configuration. + * + * @sa nrf_systick_csr_set + * @sa nrf_systick_csr_get + */ +typedef enum { + NRF_SYSTICK_CSR_COUNTFLAG_MASK = SysTick_CTRL_COUNTFLAG_Msk, /**< Status flag: Returns 1 if timer counted to 0 since the last read of this register. */ + + NRF_SYSTICK_CSR_CLKSOURCE_MASK = SysTick_CTRL_CLKSOURCE_Msk, /**< Configuration bit: Select the SysTick clock source. */ + NRF_SYSTICK_CSR_CLKSOURCE_REF = 0U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select reference clock. */ + NRF_SYSTICK_CSR_CLKSOURCE_CPU = 1U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select CPU clock. */ + + NRF_SYSTICK_CSR_TICKINT_MASK = SysTick_CTRL_TICKINT_Msk, /**< Configuration bit: Enables SysTick exception request. */ + NRF_SYSTICK_CSR_TICKINT_ENABLE = 1U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero does not assert the SysTick exception request. */ + NRF_SYSTICK_CSR_TICKINT_DISABLE = 0U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero to asserts the SysTick exception request. */ + + NRF_SYSTICK_CSR_ENABLE_MASK = SysTick_CTRL_ENABLE_Msk, /**< Configuration bit: Enable the SysTick timer. */ + NRF_SYSTICK_CSR_ENABLE = 1U << SysTick_CTRL_ENABLE_Pos, /**< Configuration value: Counter enabled. */ + NRF_SYSTICK_CSR_DISABLE = 0U << SysTick_CTRL_ENABLE_Pos /**< Configuration value: Counter disabled. */ +} nrf_systick_csr_flags_t; + +/** + * @brief Get Configuration and Status Register + * + * @return Values composed by @ref nrf_systick_csr_flags_t. + * @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read. + */ +__STATIC_INLINE uint32_t nrf_systick_csr_get(void); + +/** + * @brief Set Configuration and Status Register + * + * @param[in] val The value composed from @ref nrf_systick_csr_flags_t. + */ +__STATIC_INLINE void nrf_systick_csr_set(uint32_t val); + +/** + * @brief Get the current reload value. + * + * @return The reload register value. + */ +__STATIC_INLINE uint32_t nrf_systick_load_get(void); + +/** + * @brief Configure the reload value. + * + * @param[in] val The value to set in the reload register. + */ +__STATIC_INLINE void nrf_systick_load_set(uint32_t val); + +/** + * @brief Read the SysTick current value + * + * @return The current SysTick value + * @sa NRF_SYSTICK_VAL_MASK + */ +__STATIC_INLINE uint32_t nrf_systick_val_get(void); + +/** + * @brief Clear the SysTick current value + * + * @note The SysTick does not allow setting current value. + * Any write to VAL register would clear the timer. + */ +__STATIC_INLINE void nrf_systick_val_clear(void); + +/** + * @brief Read the calibration register + * + * @return The calibration register value + */ +__STATIC_INLINE uint32_t nrf_systick_calib_get(void); + + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_systick_csr_get(void) +{ + return SysTick->CTRL; +} + +__STATIC_INLINE void nrf_systick_csr_set(uint32_t val) +{ + SysTick->CTRL = val; +} + +__STATIC_INLINE uint32_t nrf_systick_load_get(void) +{ + return SysTick->LOAD; +} + +__STATIC_INLINE void nrf_systick_load_set(uint32_t val) +{ + SysTick->LOAD = val; +} + +__STATIC_INLINE uint32_t nrf_systick_val_get(void) +{ + return SysTick->VAL; +} + +__STATIC_INLINE void nrf_systick_val_clear(void) +{ + SysTick->VAL = 0; +} + +__STATIC_INLINE uint32_t nrf_systick_calib_get(void) +{ + return SysTick->CALIB; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_SYSTICK_H__ */ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_timer.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_timer.h new file mode 100644 index 0000000..65cad6e --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_timer.h @@ -0,0 +1,712 @@ +/** + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_TIMER_H__ +#define NRF_TIMER_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_timer_hal TIMER HAL + * @{ + * @ingroup nrf_timer + * @brief Hardware access layer for managing the TIMER peripheral. + */ + +/** + * @brief Macro for validating the correctness of the BIT_WIDTH setting. + */ + +#define TIMER_MAX_SIZE(id) NRFX_CONCAT_3(TIMER, id, _MAX_SIZE) + +#define TIMER_BIT_WIDTH_MAX(id, bit_width) \ + (TIMER_MAX_SIZE(id) == 8 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) : \ + (TIMER_MAX_SIZE(id) == 16 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) : \ + (TIMER_MAX_SIZE(id) == 24 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_24) : \ + (TIMER_MAX_SIZE(id) == 32 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_24) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_32) : \ + false)))) + +#if TIMER_COUNT > 3 +#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ + ((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \ + || ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \ + || ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width))) \ + || ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width))) \ + || ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) ) + +#else +#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ + ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \ + || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \ + || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) ) + +#endif + +/** + * @brief Macro for getting the number of capture/compare channels available + * in a given timer instance. + */ +#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM) + +/** + * @brief Timer tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer. + NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer. + NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode). + NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value. + NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer. + NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0. + NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1. + NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2. + NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5. +#endif + /*lint -restore*/ +} nrf_timer_task_t; + +/** + * @brief Timer events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0. + NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1. + NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2. + NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5. +#endif + /*lint -restore*/ +} nrf_timer_event_t; + +/** + * @brief Types of timer shortcuts. + */ +typedef enum +{ + NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5. +#endif + NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5. +#endif +} nrf_timer_short_mask_t; + +/** + * @brief Timer modes. + */ +typedef enum +{ + NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer. + NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter. +#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter. +#endif +} nrf_timer_mode_t; + +/** + * @brief Timer bit width. + */ +typedef enum +{ + NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit. + NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit. + NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit. + NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit. +} nrf_timer_bit_width_t; + +/** + * @brief Timer prescalers. + */ +typedef enum +{ + NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz. + NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz. + NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz. + NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz. + NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz. + NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz. + NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz. + NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz. + NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz. + NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz. +} nrf_timer_frequency_t; + +/** + * @brief Timer capture/compare channels. + */ +typedef enum +{ + NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0. + NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1. + NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2. + NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5. +#endif +} nrf_timer_cc_channel_t; + +/** + * @brief Timer interrupts. + */ +typedef enum +{ + NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0. + NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1. + NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2. + NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5. +#endif +} nrf_timer_int_mask_t; + + +/** + * @brief Function for activating a specific timer task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task); + +/** + * @brief Function for getting the address of a specific timer task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task); + +/** + * @brief Function for clearing a specific timer event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for checking the state of a specific timer event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for getting the address of a specific timer event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, + uint32_t timer_int); + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * TIMER task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +__STATIC_INLINE void nrf_timer_subscribe_set(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * TIMER task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to clear the configuration. + */ +__STATIC_INLINE void nrf_timer_subscribe_clear(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task); + +/** + * @brief Function for setting the publish configuration for a given + * TIMER event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +__STATIC_INLINE void nrf_timer_publish_set(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * TIMER event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to clear the configuration. + */ +__STATIC_INLINE void nrf_timer_publish_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting the timer mode. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] mode Timer mode. + */ +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, + nrf_timer_mode_t mode); + +/** + * @brief Function for retrieving the timer mode. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer mode. + */ +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for setting the timer bit width. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] bit_width Timer bit width. + */ +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, + nrf_timer_bit_width_t bit_width); + +/** + * @brief Function for retrieving the timer bit width. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer bit width. + */ +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for setting the timer frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency Timer frequency. + */ +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for retrieving the timer frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer frequency. + */ +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for writing the capture/compare register for a specified channel. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] cc_channel Requested capture/compare channel. + * @param[in] cc_value Value to write to the capture/compare register. + */ +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value); + +/** + * @brief Function for retrieving the capture/compare value for a specified channel. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] cc_channel Requested capture/compare channel. + * + * @return Value from the requested capture/compare register. + */ +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for getting a specific timer capture task. + * + * @param[in] channel Capture channel. + * + * @return Capture task. + */ +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare event. + * + * @param[in] channel Compare channel. + * + * @return Compare event. + */ +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare interrupt. + * + * @param[in] channel Compare channel. + * + * @return Compare interrupt. + */ +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in microseconds) and timer frequency. + * + * @param[in] time_us Time in microseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in milliseconds) and timer frequency. + * + * @param[in] time_ms Time in milliseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask) +{ + p_reg->SHORTS |= timer_shorts_mask; +} + +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask) +{ + p_reg->SHORTS &= ~(timer_shorts_mask); +} + +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask) +{ + p_reg->INTENSET = timer_int_mask; +} + +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask) +{ + p_reg->INTENCLR = timer_int_mask; +} + +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, + uint32_t timer_int) +{ + return (bool)(p_reg->INTENSET & timer_int); +} + +#if defined(DPPI_PRESENT) +__STATIC_INLINE void nrf_timer_subscribe_set(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = + ((uint32_t)channel | TIMER_SUBSCRIBE_START_EN_Msk); +} + +__STATIC_INLINE void nrf_timer_subscribe_clear(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; +} + +__STATIC_INLINE void nrf_timer_publish_set(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = + ((uint32_t)channel | TIMER_PUBLISH_COMPARE_EN_Msk); +} + +__STATIC_INLINE void nrf_timer_publish_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, + nrf_timer_mode_t mode) +{ + p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) | + ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk); +} + +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_mode_t)(p_reg->MODE); +} + +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, + nrf_timer_bit_width_t bit_width) +{ + p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) | + ((bit_width << TIMER_BITMODE_BITMODE_Pos) & + TIMER_BITMODE_BITMODE_Msk); +} + +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_bit_width_t)(p_reg->BITMODE); +} + +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, + nrf_timer_frequency_t frequency) +{ + p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) | + ((frequency << TIMER_PRESCALER_PRESCALER_Pos) & + TIMER_PRESCALER_PRESCALER_Msk); +} + +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_frequency_t)(p_reg->PRESCALER); +} + +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value) +{ + p_reg->CC[cc_channel] = cc_value; +} + +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel) +{ + return (uint32_t)p_reg->CC[cc_channel]; +} + +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel) +{ + return (nrf_timer_task_t) + ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel) +{ + return (nrf_timer_event_t) + ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel) +{ + return (nrf_timer_int_mask_t) + ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel); +} + +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16 MHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + uint64_t ticks = ((time_us * 16ULL) >> prescaler); + NRFX_ASSERT(ticks <= UINT32_MAX); + return (uint32_t)ticks; +} + +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16000 kHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + uint64_t ticks = ((time_ms * 16000ULL) >> prescaler); + NRFX_ASSERT(ticks <= UINT32_MAX); + return (uint32_t)ticks; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_TIMER_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_uart.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_uart.h new file mode 100644 index 0000000..dfe475c --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_uart.h @@ -0,0 +1,526 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_UART_H__ +#define NRF_UART_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_uart_hal UART HAL + * @{ + * @ingroup nrf_uart + * @brief Hardware access layer for managing the UART peripheral. + */ + +#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @enum nrf_uart_task_t + * @brief UART tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */ + NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */ + NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */ + NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */ + NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */ + /*lint -restore*/ +} nrf_uart_task_t; + +/** + * @enum nrf_uart_event_t + * @brief UART events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */ + NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */ + NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */ + NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */ + NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */ + NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */ + /*lint -restore*/ +} nrf_uart_event_t; + +/** + * @enum nrf_uart_int_mask_t + * @brief UART interrupts. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */ + NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */ + NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */ + NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */ + NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */ + NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */ + /*lint -restore*/ +} nrf_uart_int_mask_t; + +/** + * @enum nrf_uart_baudrate_t + * @brief Baudrates supported by UART. + */ +typedef enum +{ + NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */ + NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */ + NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */ + NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */ + NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */ + NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */ + NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */ + NRF_UART_BAUDRATE_31250 = UART_BAUDRATE_BAUDRATE_Baud31250, /**< 31250 baud. */ + NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */ + NRF_UART_BAUDRATE_56000 = UART_BAUDRATE_BAUDRATE_Baud56000, /**< 56000 baud. */ + NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */ + NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */ + NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */ + NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */ + NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */ + NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */ + NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */ + NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */ +} nrf_uart_baudrate_t; + +/** + * @enum nrf_uart_error_mask_t + * @brief Types of UART error masks. + */ +typedef enum +{ + NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */ + NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */ + NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */ + NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */ +} nrf_uart_error_mask_t; + +/** + * @enum nrf_uart_parity_t + * @brief Types of UART parity modes. + */ +typedef enum +{ + NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */ + NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */ +} nrf_uart_parity_t; + +/** + * @enum nrf_uart_hwfc_t + * @brief Types of UART flow control modes. + */ +typedef enum +{ + NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */ + NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */ +} nrf_uart_hwfc_t; + +/** + * @brief Function for clearing a specific UART event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for checking the state of a specific UART event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for returning the address of a specific UART event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event); + +/** + * @brief Function for enabling a specific interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg); + +/** + * @brief Function for enabling UART. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg); + +/** + * @brief Function for disabling UART. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for reading RX data. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Received byte. + */ +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for setting Tx data. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param txd Byte. + */ +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd); + +/** + * @brief Function for starting an UART task. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + */ +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for configuring UART. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc); + +/** + * @brief Function for setting UART baudrate. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif + +} + +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ +#if defined(UART_PSEL_RXD_CONNECT_Pos) + p_reg->PSEL.RXD = pselrxd; +#else + p_reg->PSELRXD = pselrxd; +#endif +#if defined(UART_PSEL_TXD_CONNECT_Pos) + p_reg->PSEL.TXD = pseltxd; +#else + p_reg->PSELTXD = pseltxd; +#endif +} + +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_TXD_CONNECT_Pos) + return p_reg->PSEL.TXD; +#else + return p_reg->PSELTXD; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RXD_CONNECT_Pos) + return p_reg->PSEL.RXD; +#else + return p_reg->PSELRXD; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + return p_reg->PSEL.RTS; +#else + return p_reg->PSELRTS; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + return p_reg->PSEL.CTS; +#else + return p_reg->PSELCTS; +#endif +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + p_reg->PSEL.RTS = pselrts; +#else + p_reg->PSELRTS = pselrts; +#endif + +#if defined(UART_PSEL_RTS_CONNECT_Pos) + p_reg->PSEL.CTS = pselcts; +#else + p_reg->PSELCTS = pselcts; +#endif +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg) +{ + return p_reg->RXD; +} + +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd) +{ + p_reg->TXD = txd; +} + +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif //NRF_UART_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/hal/nrf_uarte.h b/HAL_Driver/sdk/modules/nrfx/hal/nrf_uarte.h new file mode 100644 index 0000000..5b0cdf1 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/hal/nrf_uarte.h @@ -0,0 +1,655 @@ +/** + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_UARTE_H__ +#define NRF_UARTE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @defgroup nrf_uarte_hal UARTE HAL + * @{ + * @ingroup nrf_uarte + * @brief Hardware access layer for managing the UARTE peripheral. + */ + +/** + * @enum nrf_uarte_task_t + * @brief UARTE tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver. + NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver. + NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter. + NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter. + NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer. + /*lint -restore*/ +} nrf_uarte_task_t; + +/** + * @enum nrf_uarte_event_t + * @brief UARTE events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated. + NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated. + NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM). + NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up. + NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD. + NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted. + NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected. + NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout. + NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started. + NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started. + NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped. + /*lint -restore*/ +} nrf_uarte_event_t; + +/** + * @brief Types of UARTE shortcuts. + */ +typedef enum +{ + NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task. + NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task. +} nrf_uarte_short_t; + + +/** + * @enum nrf_uarte_int_mask_t + * @brief UARTE interrupts. + */ +typedef enum +{ + NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event. + NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event. + NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event. + NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. + NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event. + NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event. + NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. + NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. + NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event. +} nrf_uarte_int_mask_t; + +/** + * @enum nrf_uarte_baudrate_t + * @brief Baudrates supported by UARTE. + */ +typedef enum +{ + NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. + NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. + NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. + NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. + NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. + NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. + NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. + NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud. + NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. + NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud. + NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. + NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. + NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. + NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. + NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. + NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. + NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. + NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud. +} nrf_uarte_baudrate_t; + +/** + * @enum nrf_uarte_error_mask_t + * @brief Types of UARTE error masks. + */ +typedef enum +{ + NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error. + NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error. + NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error. + NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error. +} nrf_uarte_error_mask_t; + +/** + * @enum nrf_uarte_parity_t + * @brief Types of UARTE parity modes. + */ +typedef enum +{ + NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded. + NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included. +} nrf_uarte_parity_t; + +/** + * @enum nrf_uarte_hwfc_t + * @brief Types of UARTE flow control modes. + */ +typedef enum +{ + NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled. + NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< HW flow control enabled. +} nrf_uarte_hwfc_t; + + +/** + * @brief Function for clearing a specific UARTE event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for checking the state of a specific UARTE event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for returning the address of a specific UARTE event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event); + +/** + * @brief Function for enabling UARTE shortcuts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for disabling UARTE shortcuts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for enabling UARTE interrupts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Instance. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the subscribe configuration for a given + * UARTE task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to set the configuration. + * @param[in] channel Channel through which to subscribe events. + */ +__STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg, + nrf_uarte_task_t task, + uint8_t channel); + +/** + * @brief Function for clearing the subscribe configuration for a given + * UARTE task. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] task Task for which to clear the configuration. + */ +__STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg, + nrf_uarte_task_t task); + +/** + * @brief Function for setting the publish configuration for a given + * UARTE event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to set the configuration. + * @param[in] channel Channel through which to publish the event. + */ +__STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event, + uint8_t channel); + +/** + * @brief Function for clearing the publish configuration for a given + * UARTE event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] event Event for which to clear the configuration. + */ +__STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event); +#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for enabling UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for disabling UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for starting an UARTE task. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + */ +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for configuring UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc); + + +/** + * @brief Function for setting UARTE baudrate. + * + * @param p_reg Instance. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Instance. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for getting number of bytes transmitted in the last transaction. + * + * @param[in] p_reg Instance. + * + * @retval Amount of bytes transmitted. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @retval Amount of bytes received. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif + +} + +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +#if defined(DPPI_PRESENT) +__STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg, + nrf_uarte_task_t task, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = + ((uint32_t)channel | UARTE_SUBSCRIBE_STARTRX_EN_Msk); +} + +__STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg, + nrf_uarte_task_t task) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; +} + +__STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event, + uint8_t channel) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = + ((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk); +} + +__STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event) +{ + *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0; +} +#endif // defined(DPPI_PRESENT) + +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ + p_reg->PSEL.TXD = pseltxd; + p_reg->PSEL.RXD = pselrxd; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.TXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RTS; +} + +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.CTS; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ + p_reg->PSEL.RTS = pselrts; + p_reg->PSEL.CTS = pselcts; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} + +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->TXD.AMOUNT; +} + +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->RXD.AMOUNT; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif //NRF_UARTE_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/compiler_abstraction.h b/HAL_Driver/sdk/modules/nrfx/mdk/compiler_abstraction.h new file mode 100644 index 0000000..5764c73 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/compiler_abstraction.h @@ -0,0 +1,179 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __current_sp() + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + + #define GET_SP() __current_sp() + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __get_SP() + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp __ASM("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #define GET_SP() __get_MSP() + +#endif + +/*lint --flb "Leave library region" */ + +#endif diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf.h new file mode 100644 index 0000000..1190a48 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf.h @@ -0,0 +1,120 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 24 +#define MDK_MICRO_VERSION 1 + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + +/* Define NRF91_SERIES for common use in nRF91 series devices. */ +#if defined (NRF9160_XXAA) + #ifndef NRF91_SERIES + #define NRF91_SERIES + #endif +#endif + +#if defined(_WIN32) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf specific files when building for PC host */ +#else + + /* Device selection for device includes. */ + #if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + + #elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" + #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" + #elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + + #elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + + #else + #error "Device must be defined. See nrf.h." + #endif /* NRF51, NRF52810_XXAA, NRF52811_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA, NRF9160_XXAA */ + + #include "compiler_abstraction.h" + +#endif /* _WIN32 || __unix || __APPLE__ */ + +#endif /* NRF_H */ + diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h new file mode 100644 index 0000000..ee5ff42 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf51_to_nrf52840.h @@ -0,0 +1,1342 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52840_H +#define NRF51_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif + + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52840 headers. */ +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif + + +/* REFSEL register redefined enumerated values and added some more. */ +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif + + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840.h new file mode 100644 index 0000000..8e09921 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840.h @@ -0,0 +1,2935 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52840.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:48:12 + * from File 'nrf52840.svd', + * last modified on Friday, 08.02.2019 15:48:07 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52840 + * @{ + */ + + +#ifndef NRF52840_H +#define NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + PWM3_IRQn = 45, /*!< 45 PWM3 */ + SPIM3_IRQn = 47 /*!< 47 SPIM3 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52840.h" /*!< nrf52840 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) + */ +typedef struct { + __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ + __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ + __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ + __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ + __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ + __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ + __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ + __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ +} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ +} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge + of SCK and minimum duration CSN must stay + high between transactions */ +} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or + below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event + monitoring of a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written + to output RAM buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM + buffer since the previous START task */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief ACL_ACL [ACL] (Unspecified) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned + start address of region n to protect */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect + counting from address ACL[n].ADDR. Write + '0' as no effect. */ + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR + and size ACL[n].SIZE */ + __IM uint32_t RESERVED; +} ACL_ACL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n + detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n + detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral + region n detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral + region n detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt + in region n, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt + in region n, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region + n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_HALTED [HALTED] (Unspecified) + */ +typedef struct { + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ + __IM uint32_t RESERVED; + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ +} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief USBD_SIZE [SIZE] (Unspecified) + */ +typedef struct { + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received + last in the data stage of this OUT endpoint */ + __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT + data endpoint */ +} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ + + +/** + * @brief USBD_EPIN [EPIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOIN [ISOIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief USBD_EPOUT [EPOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOOUT [ISOOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_READ [READ] (Unspecified) + */ +typedef struct { + __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ + __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ +} QSPI_READ_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_WRITE [WRITE] (Unspecified) + */ +typedef struct { + __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ +} QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_ERASE [ERASE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ + __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ +} QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief QSPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ + __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ + __IM uint32_t RESERVED; + __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ + __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ + __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ + __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ +} QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ + __IM uint32_t RESERVED3[21]; + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature + n */ + __IM uint32_t RESERVED5[42]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED6[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ + __IM uint32_t RESERVED7[488]; + __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ +} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ + __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply + voltage in high voltage mode */ +} NRF_UICR_Type; /*!< Size = 776 (0x308) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready + to process new tasks */ + __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready + to process new tasks */ + __IM uint32_t RESERVED3[117]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering + the TASKS_HFCLKSTART task. */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED9[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ +} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ + __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ + __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ + __IM uint32_t RESERVED3[119]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ + __IM uint32_t RESERVED7[49]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ + __IM uint32_t RESERVED11; + __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ + __IM uint32_t RESERVED12[47]; + __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ + __IM uint32_t RESERVED13[175]; + __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register. */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and + Ieee802154_250Kbit modes when last bit is + sent on air. */ + __IM uint32_t RESERVED4[36]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[59]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED9; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED10; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED12[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED13; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED15[611]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA 0 (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write + one to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[61]; + __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields + in this register is set to STALL by hardware + whenever a stall occurres and can be cleared + (set to NOSTALL) by the CPU. */ + __IM uint32_t RESERVED10[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED11; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[2]; + __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ + __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ + __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ + __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ + __IM uint32_t RESERVED15[19]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have + been transmitted in the case when RXD.MAXCNT + is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED12[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED15[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ + __IM uint32_t RESERVED10[3]; + __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ + __IM uint32_t RESERVED11[6]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD + data storage each */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. + This setting must be done before the NFCT + peripheral is enabled. */ + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n] and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer + in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the configuration, multiple conversions + might be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is + applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly. */ + __IM uint32_t RESERVED4[7]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ ACL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< (@ 0x4001E000) ACL Structure */ + __IM uint32_t RESERVED[512]; + __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ +} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ + __IM uint32_t RESERVED4; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the STOPPED + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USBD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal serial bus device (USBD) + */ + +typedef struct { /*!< (@ 0x40027000) USBD Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR + and EPIN[n].MAXCNT registers values, and + enables endpoint IN n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers + values, and enables sending data on ISO + endpoint */ + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR + and EPOUT[n].MAXCNT registers values, and + enables endpoint n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers + values, and enables receiving of data on + ISO endpoint */ + __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint + 0 */ + __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined + in the DPDMVALUE register */ + __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state + (USB engine takes control) */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected + on USB lines */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, + or EPOUT[n].PTR and EPOUT[n].MAXCNT registers + have been captured on all endpoints reported + in the EPSTATUS register */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The RAM buffer can be + accessed safely by software. */ + __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place + on the control endpoint */ + __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The + RAM buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The RAM buffer can be + accessed safely by software. */ + __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The + RAM buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition + has been detected on USB lines */ + __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific + events has occurred. Check EVENTCAUSE register + to find the cause. */ + __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) + on the control endpoint */ + __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, + indicated by the EPDATASTATUS register */ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ + __IM uint32_t RESERVED5[7]; + __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ + __IM uint32_t RESERVED6; + __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA + registers have been captured */ + __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an + acknowledged data transfer has occurred + (EPDATA event) */ + __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ + __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ + __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ + __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ + __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ + __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ + __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ + __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ + __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ + __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ + __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by + the DPDMDRIVE task. The DPDMNODRIVE task + reverts the control of the lines to MAC + IP (no forcing). */ + __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ + __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ + __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ + __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ + __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ + __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame + counter */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during + USB suspend */ + __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint + to an IN token when no data is ready to + be sent */ + __IM uint32_t RESERVED10[51]; + __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ + __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ + __IM uint32_t RESERVED11[21]; + __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ + __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ +} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External flash interface (QSPI) + */ + +typedef struct { /*!< (@ 0x40029000) QSPI Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ + __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to + internal RAM */ + __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external + flash memory */ + __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ + __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be + generated as a response to any QSPI task. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected + in PSELn registers */ + __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ + __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ + __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ + __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ + __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute + in Place operation. */ + __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ + __IM uint32_t RESERVED3[46]; + __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ + __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep + power-down mode (DPM). */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ + __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ + __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ + __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ +} NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ + + + +/* =========================================================================================================================== */ +/* ================ CC_HOST_RGF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) + */ + +typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ + __IM uint32_t RESERVED[1678]; + __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. + When this register is set, K_PRTL can not + be used and a zeroed key will be used instead. + The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. Reading from this address + returns the K_DR valid status indicating + if K_DR is successfully retained. */ + __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The + value of this register is saved in the CRYPTOCELL + AO power domain. */ + __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL + subsystem */ +} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPTOCELL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ + __IM uint32_t RESERVED[320]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ +} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_CC_HOST_RGF_BASE 0x5002A000UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) +#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52840_H */ + + +/** @} */ /* End of group nrf52840 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_bitfields.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_bitfields.h new file mode 100644 index 0000000..a6e2894 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_bitfields.h @@ -0,0 +1,17413 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52840_BITS_H +#define __NRF52840_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_TASKS_START */ +/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ + +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ +#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_TASKS_STOP */ +/* Description: Stop resolving addresses */ + +/* Bit 0 : Stop resolving addresses */ +#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_EVENTS_END */ +/* Description: Address resolution procedure complete */ + +/* Bit 0 : Address resolution procedure complete */ +#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_RESOLVED */ +/* Description: Address resolved */ + +/* Bit 0 : Address resolved */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_NOTRESOLVED */ +/* Description: Address not resolved */ + +/* Bit 0 : Address not resolved */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event END */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event END */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: ACL */ +/* Description: Access control lists */ + +/* Register: ACL_ACL_ADDR */ +/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ + +/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: ACL_ACL_SIZE */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ + +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ +#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: ACL_ACL_PERM */ +/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ + +/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ + +/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_TASKS_KSGEN */ +/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ + +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_CRYPT */ +/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ + +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_STOP */ +/* Description: Stop encryption/decryption */ + +/* Bit 0 : Stop encryption/decryption */ +#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_RATEOVERRIDE */ +/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ + +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_EVENTS_ENDKSGEN */ +/* Description: Key-stream generation complete */ + +/* Bit 0 : Key-stream generation complete */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ENDCRYPT */ +/* Description: Encrypt/decrypt complete */ + +/* Bit 0 : Encrypt/decrypt complete */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ERROR */ +/* Description: Deprecated register - CCM error event */ + +/* Bit 0 : Deprecated field - CCM error event */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CC_HOST_RGF */ +/* Description: CRYPTOCELL HOST_RGF interface */ + +/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ +/* Description: AES hardware key select */ + +/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ + +/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ +/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ + +/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ +/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 63:32 */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ +/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 95:64 */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ +/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 127:96 */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_LCS */ +/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ + +/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ + +/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFXO crystal oscillator */ + +/* Bit 0 : Start HFXO crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFXO crystal oscillator */ + +/* Bit 0 : Stop HFXO crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK */ + +/* Bit 0 : Start LFCLK */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK */ + +/* Bit 0 : Stop LFCLK */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CAL */ +/* Description: Start calibration of LFRC */ + +/* Bit 0 : Start calibration of LFRC */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTART */ +/* Description: Start calibration timer */ + +/* Bit 0 : Start calibration timer */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTOP */ +/* Description: Stop calibration timer */ + +/* Bit 0 : Stop calibration timer */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFXO crystal oscillator started */ + +/* Bit 0 : HFXO crystal oscillator started */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : LFCLK started */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_DONE */ +/* Description: Calibration of LFRC completed */ + +/* Bit 0 : Calibration of LFRC completed */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTTO */ +/* Description: Calibration timer timeout */ + +/* Bit 0 : Calibration timer timeout */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTSTARTED */ +/* Description: Calibration timer has been started and is ready to process new tasks */ + +/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTSTOPPED */ +/* Description: Calibration timer has been stopped and is ready to process new tasks */ + +/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ +#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ +#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DONE */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ +#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ +#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DONE */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_HFXODEBOUNCE */ +/* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */ + +/* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the trace port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */ + +/* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */ + +/* Register: CLOCK_LFRCMODE */ +/* Description: LFRC mode configuration */ + +/* Bit 16 : Active LFRC mode. This field is read only. */ +#define CLOCK_LFRCMODE_STATUS_Pos (16UL) /*!< Position of STATUS field. */ +#define CLOCK_LFRCMODE_STATUS_Msk (0x1UL << CLOCK_LFRCMODE_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFRCMODE_STATUS_Normal (0UL) /*!< Normal mode */ +#define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */ + +/* Bit 0 : Set LFRC mode */ +#define CLOCK_LFRCMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CLOCK_LFRCMODE_MODE_Msk (0x1UL << CLOCK_LFRCMODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CLOCK_LFRCMODE_MODE_Normal (0UL) /*!< Normal mode */ +#define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : Start comparator */ +#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : Stop comparator */ +#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : Sample comparator value */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_EVENTS_READY */ +/* Description: COMP is ready and output is valid */ + +/* Bit 0 : COMP is ready and output is valid */ +#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : Downward crossing */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : Upward crossing */ +#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : Downward or upward crossing */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event CROSS and task STOP */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event UP and task STOP */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DOWN and task STOP */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event READY and task STOP */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task SAMPLE */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for event CROSS */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event UP */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event DOWN */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event READY */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event UP */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event UP */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: CRYPTOCELL */ +/* Description: ARM TrustZone CryptoCell register interface */ + +/* Register: CRYPTOCELL_ENABLE */ +/* Description: Enable CRYPTOCELL subsystem */ + +/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ +#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_TASKS_STARTECB */ +/* Description: Start ECB block encrypt */ + +/* Bit 0 : Start ECB block encrypt */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_TASKS_STOPECB */ +/* Description: Abort a possible executing ECB operation */ + +/* Bit 0 : Abort a possible executing ECB operation */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_EVENTS_ENDECB */ +/* Description: ECB block encrypt complete */ + +/* Bit 0 : ECB block encrypt complete */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_EVENTS_ERRORECB */ +/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ + +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory information configuration registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection: Encryption root, word n */ + +/* Bits 31..0 : Encryption root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection: Identity Root, word n */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection: Device address n */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Build code (hardware version and production configuration) */ + +/* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ +#define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_PRODTEST */ +/* Description: Description collection: Production test signature n */ + +/* Bits 31..0 : Production test signature n */ +#define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */ +#define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: Y-intercept B0 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: Y-intercept B1 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: Y-intercept B2 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: Y-intercept B3 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: Y-intercept B4 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: Y-intercept B5 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + +/* Register: FICR_TRNG90B_BYTES */ +/* Description: Amount of bytes for the required entropy bits */ + +/* Bits 31..0 : Amount of bytes for the required entropy bits */ +#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ +#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ + +/* Register: FICR_TRNG90B_RCCUTOFF */ +/* Description: Repetition counter cutoff */ + +/* Bits 31..0 : Repetition counter cutoff */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ + +/* Register: FICR_TRNG90B_APCUTOFF */ +/* Description: Adaptive proportion cutoff */ + +/* Bits 31..0 : Adaptive proportion cutoff */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ + +/* Register: FICR_TRNG90B_STARTUP */ +/* Description: Amount of bytes for the startup tests */ + +/* Bits 31..0 : Amount of bytes for the startup tests */ +#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ +#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ + +/* Register: FICR_TRNG90B_ROSC1 */ +/* Description: Sample count for ring oscillator 1 */ + +/* Bits 31..0 : Sample count for ring oscillator 1 */ +#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ +#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ + +/* Register: FICR_TRNG90B_ROSC2 */ +/* Description: Sample count for ring oscillator 2 */ + +/* Bits 31..0 : Sample count for ring oscillator 2 */ +#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ +#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ + +/* Register: FICR_TRNG90B_ROSC3 */ +/* Description: Sample count for ring oscillator 3 */ + +/* Bits 31..0 : Sample count for ring oscillator 3 */ +#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ +#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ + +/* Register: FICR_TRNG90B_ROSC4 */ +/* Description: Sample count for ring oscillator 4 */ + +/* Bits 31..0 : Sample count for ring oscillator 4 */ +#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ +#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for event PORT */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for event PORT */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bit 13 : Port number */ +#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ +#define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_TASKS_START */ +/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ + +/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ +#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: I2S_TASKS_STOP */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ + +/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ +#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: I2S_EVENTS_RXPTRUPD */ +/* Description: The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ + +/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_EVENTS_STOPPED */ +/* Description: I2S transfer stopped. */ + +/* Bit 0 : I2S transfer stopped. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_EVENTS_TXPTRUPD */ +/* Description: The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ + +/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event STOPPED */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : Start comparator */ +#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: LPCOMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : Stop comparator */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: LPCOMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : Sample comparator value */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: LPCOMP_EVENTS_READY */ +/* Description: LPCOMP is ready and output is valid */ + +/* Bit 0 : LPCOMP is ready and output is valid */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: LPCOMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : Downward crossing */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ + +/* Register: LPCOMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : Upward crossing */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ + +/* Register: LPCOMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : Downward or upward crossing */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event CROSS and task STOP */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event UP and task STOP */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DOWN and task STOP */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event READY and task STOP */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task SAMPLE */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event UP */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event UP */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_EVENTS_REGION_WA */ +/* Description: Description cluster: Write access to region n detected */ + +/* Bit 0 : Write access to region n detected */ +#define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */ + +/* Register: MWU_EVENTS_REGION_RA */ +/* Description: Description cluster: Read access to region n detected */ + +/* Bit 0 : Read access to region n detected */ +#define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */ + +/* Register: MWU_EVENTS_PREGION_WA */ +/* Description: Description cluster: Write access to peripheral region n detected */ + +/* Bit 0 : Write access to peripheral region n detected */ +#define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */ + +/* Register: MWU_EVENTS_PREGION_RA */ +/* Description: Description cluster: Read access to peripheral region n detected */ + +/* Bit 0 : Read access to peripheral region n detected */ +#define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster: Start address for region n */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster: End address of region n */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster: Subregions of region n */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_TASKS_ACTIVATE */ +/* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ + +/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_DISABLE */ +/* Description: Disable NFCT peripheral */ + +/* Bit 0 : Disable NFCT peripheral */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_SENSE */ +/* Description: Enable NFC sense field mode, change state to sense mode */ + +/* Bit 0 : Enable NFC sense field mode, change state to sense mode */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_STARTTX */ +/* Description: Start transmission of an outgoing frame, change state to transmit */ + +/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_ENABLERXDATA */ +/* Description: Initializes the EasyDMA for receive. */ + +/* Bit 0 : Initializes the EasyDMA for receive. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_GOIDLE */ +/* Description: Force state machine to IDLE state */ + +/* Bit 0 : Force state machine to IDLE state */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_TASKS_GOSLEEP */ +/* Description: Force state machine to SLEEP_A state */ + +/* Bit 0 : Force state machine to SLEEP_A state */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */ + +/* Register: NFCT_EVENTS_READY */ +/* Description: The NFCT peripheral is ready to receive and send frames */ + +/* Bit 0 : The NFCT peripheral is ready to receive and send frames */ +#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_FIELDDETECTED */ +/* Description: Remote NFC field detected */ + +/* Bit 0 : Remote NFC field detected */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_FIELDLOST */ +/* Description: Remote NFC field lost */ + +/* Bit 0 : Remote NFC field lost */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_TXFRAMESTART */ +/* Description: Marks the start of the first symbol of a transmitted frame */ + +/* Bit 0 : Marks the start of the first symbol of a transmitted frame */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_TXFRAMEEND */ +/* Description: Marks the end of the last transmitted on-air symbol of a frame */ + +/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_RXFRAMESTART */ +/* Description: Marks the end of the first symbol of a received frame */ + +/* Bit 0 : Marks the end of the first symbol of a received frame */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_RXFRAMEEND */ +/* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ + +/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_ERROR */ +/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ + +/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_RXERROR */ +/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ + +/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_ENDRX */ +/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + +/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_ENDTX */ +/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ + +/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ +/* Description: Auto collision resolution process has started */ + +/* Bit 0 : Auto collision resolution process has started */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_COLLISION */ +/* Description: NFC auto collision resolution error reported. */ + +/* Bit 0 : NFC auto collision resolution error reported. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_SELECTED */ +/* Description: NFC auto collision resolution successfully completed */ + +/* Bit 0 : NFC auto collision resolution successfully completed */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_EVENTS_STARTED */ +/* Description: EasyDMA is ready to receive or send frames. */ + +/* Bit 0 : EasyDMA is ready to receive or send frames. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for event STARTED */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event SELECTED */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event COLLISION */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event ENDTX */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event ENDRX */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event RXERROR */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event ERROR */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event FIELDLOST */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event READY */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to enable interrupt for event STARTED */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event SELECTED */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COLLISION */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event ENDTX */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event ENDRX */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event RXERROR */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event ERROR */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to disable interrupt for event STARTED */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event SELECTED */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COLLISION */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event ENDTX */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event ENDRX */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event RXERROR */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event ERROR */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frame */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid end of frame (EoF) detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_NFCTAGSTATE */ +/* Description: NfcTag state register */ + +/* Bits 2..0 : NfcTag state */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */ + +/* Register: NFCT_SLEEPSTATE */ +/* Description: Sleep state during automatic collision resolution */ + +/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */ + +/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */ + +/* Bit 1 : Discarding unused bits at start or end of a frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */ + +/* Bit 0 : Indicates if parity is added to the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */ + +/* Bit 0 : Indicates if parity expected in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_AUTOCOLRESCONFIG */ +/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */ + +/* Bit 0 : Enables/disables auto collision resolution */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_READYNEXT */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC can accept a new write operation */ +#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ +#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in code area */ + +/* Bits 31..0 : Register for starting erase of a page in code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing user information configuration registers */ + +/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ERASEPAGEPARTIAL */ +/* Description: Register for partial erase of a page in code area */ + +/* Bits 31..0 : Register for starting partial erase of a page in code area */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_TASKS_START */ +/* Description: Starts continuous PDM transfer */ + +/* Bit 0 : Starts continuous PDM transfer */ +#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_TASKS_STOP */ +/* Description: Stops PDM transfer */ + +/* Bit 0 : Stops PDM transfer */ +#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_EVENTS_STARTED */ +/* Description: PDM transfer has started */ + +/* Bit 0 : PDM transfer has started */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_STOPPED */ +/* Description: PDM transfer has finished */ + +/* Bit 0 : PDM transfer has finished */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_END */ +/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ + +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ +#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for event END */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event END */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event END */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ +#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_RATIO */ +/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ + +/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ +#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ +#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable constant latency mode */ + +/* Bit 0 : Enable constant latency mode */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable low power mode (variable latency) */ + +/* Bit 0 : Enable low power mode (variable latency) */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : Power failure warning */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : CPU entered WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : CPU exited WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBDETECTED */ +/* Description: Voltage supply detected on VBUS */ + +/* Bit 0 : Voltage supply detected on VBUS */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBREMOVED */ +/* Description: Voltage supply removed from VBUS */ + +/* Bit 0 : Voltage supply removed from VBUS */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_USBPWRRDY */ +/* Description: USB 3.3 V supply ready */ + +/* Bit 0 : USB 3.3 V supply ready */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ +#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ +#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ +#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ +#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ +#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ +#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */ +#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ +#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ +#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_USBREGSTATUS */ +/* Description: USB supply status */ + +/* Bit 1 : USB supply output settling time elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */ + +/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */ +#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */ +#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power-fail comparator configuration */ + +/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ +#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */ +#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */ +#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */ +#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */ +#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */ +#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ + +/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure warning */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: Enable DC/DC converter for REG1 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG1 stage. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_DCDCEN0 */ +/* Description: Enable DC/DC converter for REG0 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG0 stage. */ +#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_MAINREGSTATUS */ +/* Description: Main supply status */ + +/* Bit 0 : Main supply status */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster: RAMn power control register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ +#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is off */ +#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is off */ +#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is off */ +#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is off */ +#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is off */ +#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is off */ +#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is off */ +#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is off */ +#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is off */ +#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is off */ +#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is off */ +#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is off */ +#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is off */ +#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 on or off in System ON mode. */ +#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 on or off in System ON mode. */ +#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 on or off in System ON mode. */ +#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 on or off in System ON mode. */ +#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 on or off in System ON mode. */ +#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 on or off in System ON mode. */ +#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 on or off in System ON mode. */ +#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 on or off in System ON mode. */ +#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 on or off in System ON mode. */ +#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 on or off in System ON mode. */ +#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 on or off in System ON mode. */ +#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 on or off in System ON mode. */ +#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 on or off in System ON mode. */ +#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 on or off in System ON mode. */ +#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster: RAMn power control set register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster: RAMn power control clear register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */ + +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */ + +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */ + +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */ + +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */ + +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */ + +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */ + +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */ + +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */ + +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */ + +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */ + +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */ + +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ + +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_TASKS_CHG_EN */ +/* Description: Description cluster: Enable channel group n */ + +/* Bit 0 : Enable channel group n */ +#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_TASKS_CHG_DIS */ +/* Description: Description cluster: Disable channel group n */ + +/* Bit 0 : Disable channel group n */ +#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster: Channel n event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection: Channel group n */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse width modulation unit 0 */ + +/* Register: PWM_TASKS_STOP */ +/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ +#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_SEQSTART */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ + +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_NEXTSTEP */ +/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ + +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_EVENTS_STOPPED */ +/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ + +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQSTARTED */ +/* Description: Description collection: First PWM period started on sequence n */ + +/* Bit 0 : First PWM period started on sequence n */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQEND */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_PWMPERIODEND */ +/* Description: Emitted at the end of each PWM period */ + +/* Bit 0 : Emitted at the end of each PWM period */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_LOOPSDONE */ +/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Prescaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Number of playbacks of a loop */ + +/* Bits 15..0 : Number of playbacks of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ + +/* Bits 31..0 : Beginning address in RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection: Output pin select for PWM channel n */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : Task starting the quadrature decoder */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : Task stopping the quadrature decoder */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : Read and clear ACC and ACCDBL */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : Read and clear ACC */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : Read and clear ACCDBL */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : Non-null report ready */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : ACC or ACCDBL register overflow */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : Double displacement(s) detected */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : QDEC has been stopped */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: QSPI */ +/* Description: External flash interface */ + +/* Register: QSPI_TASKS_ACTIVATE */ +/* Description: Activate QSPI interface */ + +/* Bit 0 : Activate QSPI interface */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ + +/* Register: QSPI_TASKS_READSTART */ +/* Description: Start transfer from external flash memory to internal RAM */ + +/* Bit 0 : Start transfer from external flash memory to internal RAM */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: QSPI_TASKS_WRITESTART */ +/* Description: Start transfer from internal RAM to external flash memory */ + +/* Bit 0 : Start transfer from internal RAM to external flash memory */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: QSPI_TASKS_ERASESTART */ +/* Description: Start external flash memory erase operation */ + +/* Bit 0 : Start external flash memory erase operation */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: QSPI_TASKS_DEACTIVATE */ +/* Description: Deactivate QSPI interface */ + +/* Bit 0 : Deactivate QSPI interface */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */ + +/* Register: QSPI_EVENTS_READY */ +/* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ + +/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ +#define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: QSPI_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 0 : Enable or disable interrupt for event READY */ +#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: QSPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: QSPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: QSPI_ENABLE */ +/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */ + +/* Bit 0 : Enable or disable QSPI */ +#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */ +#define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */ + +/* Register: QSPI_READ_SRC */ +/* Description: Flash memory source address */ + +/* Bits 31..0 : Word-aligned flash memory source address. */ +#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_READ_DST */ +/* Description: RAM destination address */ + +/* Bits 31..0 : Word-aligned RAM destination address. */ +#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_READ_CNT */ +/* Description: Read transfer length */ + +/* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_WRITE_DST */ +/* Description: Flash destination address */ + +/* Bits 31..0 : Word-aligned flash destination address. */ +#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_WRITE_SRC */ +/* Description: RAM source address */ + +/* Bits 31..0 : Word-aligned RAM source address. */ +#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_WRITE_CNT */ +/* Description: Write transfer length */ + +/* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_ERASE_PTR */ +/* Description: Start address of flash block to be erased */ + +/* Bits 31..0 : Word-aligned start address of block to be erased. */ +#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: QSPI_ERASE_LEN */ +/* Description: Size of block to be erased. */ + +/* Bits 1..0 : LEN */ +#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */ +#define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */ +#define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */ +#define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */ + +/* Register: QSPI_PSEL_SCK */ +/* Description: Pin select for serial clock SCK */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_CSN */ +/* Description: Pin select for chip select signal CSN. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO0 */ +/* Description: Pin select for serial data MOSI/IO0. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO1 */ +/* Description: Pin select for serial data MISO/IO1. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO2 */ +/* Description: Pin select for serial data IO2. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO3 */ +/* Description: Pin select for serial data IO3. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_XIPOFFSET */ +/* Description: Address offset into the external memory for Execute in Place operation. */ + +/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */ + +/* Register: QSPI_IFCONFIG0 */ +/* Description: Interface configuration. */ + +/* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */ +#define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */ +#define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */ +#define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL) /*!< 256 bytes. */ +#define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL) /*!< 512 bytes. */ + +/* Bit 7 : Enable deep power-down mode (DPM) feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */ + +/* Bit 6 : Addressing mode. */ +#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */ +#define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */ + +/* Bits 5..3 : Configure number of data lines and opcode used for writing. */ +#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */ +#define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */ + +/* Bits 2..0 : Configure number of data lines and opcode used for reading. */ +#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */ +#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */ +#define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */ +#define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */ +#define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */ +#define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */ +#define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */ + +/* Register: QSPI_IFCONFIG1 */ +/* Description: Interface configuration. */ + +/* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */ +#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */ +#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */ + +/* Bit 25 : Select SPI mode. */ +#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ + +/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ +#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */ +#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */ + +/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */ +#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */ +#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */ + +/* Register: QSPI_STATUS */ +/* Description: Status register. */ + +/* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */ +#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */ +#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */ + +/* Bit 3 : Ready status. */ +#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */ +#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */ +#define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */ + +/* Bit 2 : Deep power-down mode (DPM) status of external flash. */ +#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */ +#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */ +#define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */ +#define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */ + +/* Register: QSPI_DPMDUR */ +/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */ + +/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */ +#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */ + +/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */ +#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */ + +/* Register: QSPI_ADDRCONF */ +/* Description: Extended address configuration. */ + +/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */ +#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 26 : Wait for write complete before sending command. */ +#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bits 25..24 : Extended addressing mode. */ +#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */ +#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */ +#define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */ +#define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */ +#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */ +#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */ + +/* Bits 23..16 : Byte 1 following byte 0. */ +#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */ +#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 15..8 : Byte 0 following opcode. */ +#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */ +#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */ +#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRCONF */ +/* Description: Custom instruction configuration register. */ + +/* Bit 17 : Stop (finalize) long frame transaction */ +#define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */ +#define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */ +#define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */ + +/* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */ +#define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */ +#define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */ +#define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */ +#define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */ + +/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 14 : Wait for write complete before sending command. */ +#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */ +#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */ + +/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */ +#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */ + +/* Bits 11..8 : Length of custom instruction in number of bytes. */ +#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */ +#define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */ +#define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ +#define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ +#define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ +#define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ +#define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ +#define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ +#define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ + +/* Bits 7..0 : Opcode of Custom instruction. */ +#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRDAT0 */ +/* Description: Custom instruction data register 0. */ + +/* Bits 31..24 : Data byte 3 */ +#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */ +#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */ + +/* Bits 23..16 : Data byte 2 */ +#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */ +#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */ + +/* Bits 15..8 : Data byte 1 */ +#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */ +#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 7..0 : Data byte 0 */ +#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */ +#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Register: QSPI_CINSTRDAT1 */ +/* Description: Custom instruction data register 1. */ + +/* Bits 31..24 : Data byte 7 */ +#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */ +#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */ + +/* Bits 23..16 : Data byte 6 */ +#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */ +#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */ + +/* Bits 15..8 : Data byte 5 */ +#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */ +#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */ + +/* Bits 7..0 : Data byte 4 */ +#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */ +#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */ + +/* Register: QSPI_IFTIMING */ +/* Description: SPI interface timing. */ + +/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */ +#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */ +#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz radio */ + +/* Register: RADIO_TASKS_TXEN */ +/* Description: Enable RADIO in TX mode */ + +/* Bit 0 : Enable RADIO in TX mode */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RXEN */ +/* Description: Enable RADIO in RX mode */ + +/* Bit 0 : Enable RADIO in RX mode */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_START */ +/* Description: Start RADIO */ + +/* Bit 0 : Start RADIO */ +#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_STOP */ +/* Description: Stop RADIO */ + +/* Bit 0 : Stop RADIO */ +#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_DISABLE */ +/* Description: Disable RADIO */ + +/* Bit 0 : Disable RADIO */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTART */ +/* Description: Start the RSSI and take one single sample of the receive signal strength */ + +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTOP */ +/* Description: Stop the RSSI measurement */ + +/* Bit 0 : Stop the RSSI measurement */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTART */ +/* Description: Start the bit counter */ + +/* Bit 0 : Start the bit counter */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTOP */ +/* Description: Stop the bit counter */ + +/* Bit 0 : Stop the bit counter */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTART */ +/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTOP */ +/* Description: Stop the energy detect measurement */ + +/* Bit 0 : Stop the energy detect measurement */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTART */ +/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTOP */ +/* Description: Stop the clear channel assessment */ + +/* Bit 0 : Stop the clear channel assessment */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_EVENTS_READY */ +/* Description: RADIO has ramped up and is ready to be started */ + +/* Bit 0 : RADIO has ramped up and is ready to be started */ +#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_ADDRESS */ +/* Description: Address sent or received */ + +/* Bit 0 : Address sent or received */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PAYLOAD */ +/* Description: Packet payload sent or received */ + +/* Bit 0 : Packet payload sent or received */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_END */ +/* Description: Packet sent or received */ + +/* Bit 0 : Packet sent or received */ +#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DISABLED */ +/* Description: RADIO has been disabled */ + +/* Bit 0 : RADIO has been disabled */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMATCH */ +/* Description: A device address match occurred on the last received packet */ + +/* Bit 0 : A device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMISS */ +/* Description: No device address match occurred on the last received packet */ + +/* Bit 0 : No device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RSSIEND */ +/* Description: Sampling of receive signal strength complete */ + +/* Bit 0 : Sampling of receive signal strength complete */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_BCMATCH */ +/* Description: Bit counter reached bit count value */ + +/* Bit 0 : Bit counter reached bit count value */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCOK */ +/* Description: Packet received with CRC ok */ + +/* Bit 0 : Packet received with CRC ok */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCERROR */ +/* Description: Packet received with CRC error */ + +/* Bit 0 : Packet received with CRC error */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_FRAMESTART */ +/* Description: IEEE 802.15.4 length field received */ + +/* Bit 0 : IEEE 802.15.4 length field received */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDEND */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ + +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDSTOPPED */ +/* Description: The sampling of energy detection has stopped */ + +/* Bit 0 : The sampling of energy detection has stopped */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCAIDLE */ +/* Description: Wireless medium in idle - clear to send */ + +/* Bit 0 : Wireless medium in idle - clear to send */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCABUSY */ +/* Description: Wireless medium busy - do not send */ + +/* Bit 0 : Wireless medium busy - do not send */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCASTOPPED */ +/* Description: The CCA has stopped */ + +/* Bit 0 : The CCA has stopped */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RATEBOOST */ +/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ + +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_TXREADY */ +/* Description: RADIO has ramped up and is ready to be started TX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RXREADY */ +/* Description: RADIO has ramped up and is ready to be started RX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_MHRMATCH */ +/* Description: MAC header match found */ + +/* Bit 0 : MAC header match found */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PHYEND */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ + +/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 21 : Shortcut between event PHYEND and task START */ +#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ +#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 19 : Shortcut between event RXREADY and task START */ +#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 18 : Shortcut between event TXREADY and task START */ +#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ +#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ +#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 15 : Shortcut between event READY and task EDSTART */ +#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ +#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event END and task START */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event END and task DISABLE */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task START */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ +#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ +#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ +#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ +#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ +#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ +#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ +#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ +#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ +#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ +#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ +#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event END */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ +#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ +#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ +#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ +#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ +#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ +#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ +#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ +#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ +#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ +#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ +#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event END */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PDUSTAT */ +/* Description: Payload status */ + +/* Bits 2..1 : Status on what rate packet is received with in Long Range */ +#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */ +#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */ + +/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bits 30..29 : Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ +#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + +/* Bit 26 : Indicates if LENGTH field contains CRC or not */ +#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ +#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ + +/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ +#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ + +/* Bits 23..22 : Length of code indicator - long range */ +#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ +#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Interframe spacing in us */ + +/* Bits 9..0 : Interframe spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection: Device address base segment n */ + +/* Bits 31..0 : Device address base segment n */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection: Device address prefix n */ + +/* Bits 15..0 : Device address prefix n */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_SFD */ +/* Description: IEEE 802.15.4 start of frame delimiter */ + +/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ +#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ +#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + +/* Register: RADIO_EDCNT */ +/* Description: IEEE 802.15.4 energy detect loop count */ + +/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ +#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ +#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* Register: RADIO_EDSAMPLE */ +/* Description: IEEE 802.15.4 energy detect level */ + +/* Bits 7..0 : IEEE 802.15.4 energy detect level */ +#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ +#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + +/* Register: RADIO_CCACTRL */ +/* Description: IEEE 802.15.4 clear channel assessment control */ + +/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ +#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ +#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + +/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ +#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ +#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ +#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* Bits 2..0 : CCA mode of operation */ +#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_TASKS_START */ +/* Description: Task starting the random number generator */ + +/* Bit 0 : Task starting the random number generator */ +#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_TASKS_STOP */ +/* Description: Task stopping the random number generator */ + +/* Bit 0 : Task stopping the random number generator */ +#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_EVENTS_VALRDY */ +/* Description: Event being generated for every new random number written to the VALUE register */ + +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event VALRDY and task STOP */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC COUNTER */ + +/* Bit 0 : Start RTC COUNTER */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC COUNTER */ + +/* Bit 0 : Stop RTC COUNTER */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC COUNTER */ + +/* Bit 0 : Clear RTC COUNTER */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set COUNTER to 0xFFFFF0 */ + +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on COUNTER increment */ + +/* Bit 0 : Event on COUNTER increment */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on COUNTER overflow */ + +/* Bit 0 : Event on COUNTER overflow */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TICK */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TICK */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ + +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ + +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ + +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ + +/* Bit 1 : Enable or disable event routing for event OVRFLW */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ + +/* Bit 0 : Enable or disable event routing for event TICK */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for event TICK */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for event TICK */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Successive approximation register (SAR) analog-to-digital converter */ + +/* Register: SAADC_TASKS_START */ +/* Description: Starts the SAADC and prepares the result buffer in RAM */ + +/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */ +#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_SAMPLE */ +/* Description: Takes one SAADC sample */ + +/* Bit 0 : Takes one SAADC sample */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_STOP */ +/* Description: Stops the SAADC and terminates all on-going conversions */ + +/* Bit 0 : Stops the SAADC and terminates all on-going conversions */ +#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_CALIBRATEOFFSET */ +/* Description: Starts offset auto-calibration */ + +/* Bit 0 : Starts offset auto-calibration */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_EVENTS_STARTED */ +/* Description: The SAADC has started */ + +/* Bit 0 : The SAADC has started */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_END */ +/* Description: The SAADC has filled up the result buffer */ + +/* Bit 0 : The SAADC has filled up the result buffer */ +#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_DONE */ +/* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ + +/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_RESULTDONE */ +/* Description: Result ready for transfer to RAM */ + +/* Bit 0 : Result ready for transfer to RAM */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CALIBRATEDONE */ +/* Description: Calibration is complete */ + +/* Bit 0 : Calibration is complete */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_STOPPED */ +/* Description: The SAADC has stopped */ + +/* Bit 0 : The SAADC has stopped */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITH */ +/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */ + +/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITL */ +/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */ + +/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event STOPPED */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event DONE */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event END */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event DONE */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event DONE */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable SAADC */ + +/* Bit 0 : Enable or disable SAADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster: Input configuration for CH[n] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster: High/low limits for event monitoring of a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of 16-bit samples to be written to output RAM buffer */ + +/* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */ + +/* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_EVENTS_READY */ +/* Description: TXD byte sent and RXD byte received */ + +/* Bit 0 : TXD byte sent and RXD byte received */ +#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event READY */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event READY */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : Start SPI transaction */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : Stop SPI transaction */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : Suspend SPI transaction */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : Resume SPI transaction */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : SPI transaction has stopped */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : End of RXD buffer and TXD buffer reached */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : End of TXD buffer reached */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : Transaction started */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 17 : Shortcut between event END and task START */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event END */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event END */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_STALLSTAT */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ + +/* Bit 1 : Stall status for EasyDMA RAM writes */ +#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ +#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */ +#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */ + +/* Bit 0 : Stall status for EasyDMA RAM reads */ +#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */ +#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */ +#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_CSN */ +/* Description: Pin select for CSN */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_IFTIMING_RXDELAY */ +/* Description: Sample delay for input serial data on MISO */ + +/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + +/* Register: SPIM_IFTIMING_CSNDUR */ +/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */ + +/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ + +/* Register: SPIM_CSNPOL */ +/* Description: Polarity of CSN output */ + +/* Bit 0 : Polarity of CSN output */ +#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */ +#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */ +#define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */ +#define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */ + +/* Register: SPIM_PSELDCX */ +/* Description: Pin select for DCX signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_DCXCNT */ +/* Description: DCX configuration */ + +/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */ +#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */ +#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */ + +/* Register: SPIM_ORC */ +/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ + +/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : Acquire SPI semaphore */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : Granted transaction completed */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : Semaphore acquired */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 2 : Shortcut between event END and task ACQUIRE */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 15..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 15..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_TASKS_START */ +/* Description: Start temperature measurement */ + +/* Bit 0 : Start temperature measurement */ +#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_TASKS_STOP */ +/* Description: Stop temperature measurement */ + +/* Bit 0 : Stop temperature measurement */ +#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_EVENTS_DATARDY */ +/* Description: Temperature measurement complete, data ready */ + +/* Bit 0 : Temperature measurement complete, data ready */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : Start Timer */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : Stop Timer */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : Increment Timer (Counter mode only) */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : Clear time */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : Deprecated field - Shut down timer */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection: Capture Timer value to CC[n] register */ + +/* Bit 0 : Capture Timer value to CC[n] register */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_RXDREADY */ +/* Description: TWI RXD byte received */ + +/* Bit 0 : TWI RXD byte received */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_TXDSENT */ +/* Description: TWI TXD byte sent */ + +/* Bit 0 : TWI TXD byte sent */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_BB */ +/* Description: TWI byte boundary, generated before each byte that is sent or received */ + +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ +#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_SUSPENDED */ +/* Description: TWI entered the suspended state */ + +/* Bit 0 : TWI entered the suspended state */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 1 : Shortcut between event BB and task STOP */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event BB and task SUSPEND */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event BB */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event BB */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : Byte boundary, starting to receive the last byte */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : Byte boundary, starting to transmit the last byte */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 12 : Shortcut between event LASTRX and task STOP */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event LASTTX and task STOP */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event LASTTX */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event LASTRX */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : Prepare the TWI slave to respond to a write command */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : Prepare the TWI slave to respond to a read command */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : Write command received */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : Read command received */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 14 : Shortcut between event READ and task SUSPEND */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for event READ */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event WRITE */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for event READ */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for event READ */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 15..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 15..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_SUSPEND */ +/* Description: Suspend UART */ + +/* Bit 0 : Suspend UART */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXDRDY */ +/* Description: Data received in RXD */ + +/* Bit 0 : Data received in RXD */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event CTS and task STARTRX */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA 0 */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : Flush RX FIFO into RX buffer */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : Receive buffer is filled up */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : Last TX byte transmitted */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : UART receiver has started */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : UART transmitter has started */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : Transmitter stopped */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event RXTO */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDTX */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDRX */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event NCTS */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event CTS */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number onto which nRESET is exposed */ +#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable access port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + +/* Register: UICR_DEBUGCTRL */ +/* Description: Processor debug control */ + +/* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */ +#define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ + +/* Bits 7..0 : Configure CPU non-intrusive debug features */ +#define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */ +#define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */ +#define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */ +#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ + +/* Register: UICR_REGOUT0 */ +/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ + +/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ +#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ +#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ +#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */ +#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */ +#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */ +#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */ +#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */ +#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */ + + +/* Peripheral: USBD */ +/* Description: Universal serial bus device */ + +/* Register: USBD_TASKS_STARTEPIN */ +/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ + +/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTISOIN */ +/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ + +/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTEPOUT */ +/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ + +/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_STARTISOOUT */ +/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ + +/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0RCVOUT */ +/* Description: Allows OUT data stage on control endpoint 0 */ + +/* Bit 0 : Allows OUT data stage on control endpoint 0 */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0STATUS */ +/* Description: Allows status stage on control endpoint 0 */ + +/* Bit 0 : Allows status stage on control endpoint 0 */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_EP0STALL */ +/* Description: Stalls data and status stage on control endpoint 0 */ + +/* Bit 0 : Stalls data and status stage on control endpoint 0 */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_DPDMDRIVE */ +/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ + +/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_TASKS_DPDMNODRIVE */ +/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ + +/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ + +/* Register: USBD_EVENTS_USBRESET */ +/* Description: Signals that a USB reset condition has been detected on USB lines */ + +/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_STARTED */ +/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ + +/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDEPIN */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EP0DATADONE */ +/* Description: An acknowledged data transfer has taken place on the control endpoint */ + +/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDISOIN */ +/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDEPOUT */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_ENDISOOUT */ +/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_SOF */ +/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ + +/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_USBEVENT */ +/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ + +/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EP0SETUP */ +/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ + +/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_EVENTS_EPDATA */ +/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ + +/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ + +/* Register: USBD_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: USBD_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event EPDATA */ +#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ +#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ + +/* Bit 22 : Enable or disable interrupt for event USBEVENT */ +#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ + +/* Bit 21 : Enable or disable interrupt for event SOF */ +#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ +#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ +#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ +#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ +#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ +#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ +#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ +#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ +#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ +#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ +#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ +#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ +#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ +#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ +#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ +#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ +#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ +#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ +#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ +#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STARTED */ +#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event USBRESET */ +#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */ + +/* Register: USBD_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ +#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ +#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ +#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for event SOF */ +#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ +#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ +#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ +#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ +#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ +#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ +#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ +#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ +#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ +#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ +#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ +#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ +#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ +#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ +#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ +#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ +#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ +#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ +#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ +#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STARTED */ +#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ +#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */ + +/* Register: USBD_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ +#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ +#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ +#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for event SOF */ +#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ +#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ +#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ +#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ +#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ +#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ +#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ +#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ +#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ +#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ +#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ +#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ +#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ +#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ +#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ +#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ +#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ +#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ +#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ +#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STARTED */ +#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ +#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ + +/* Register: USBD_EVENTCAUSE */ +/* Description: Details on what caused the USBEVENT event */ + +/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */ +#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ +#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */ +#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */ +#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */ + +/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */ + +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */ +#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ +#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ + +/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */ +#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ +#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */ + +/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ + +/* Register: USBD_HALTED_EPIN */ +/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_HALTED_EPOUT */ +/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_EPSTATUS */ +/* Description: Provides information on which endpoint's EasyDMA registers have been captured */ + +/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Register: USBD_EPDATASTATUS */ +/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */ + +/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Register: USBD_USBADDR */ +/* Description: Device USB address */ + +/* Bits 6..0 : Device USB address */ +#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: USBD_BMREQUESTTYPE */ +/* Description: SETUP data, byte 0, bmRequestType */ + +/* Bit 7 : Data transfer direction */ +#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */ +#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */ + +/* Bits 6..5 : Data transfer type */ +#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */ +#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */ +#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */ + +/* Bits 4..0 : Data transfer type */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */ + +/* Register: USBD_BREQUEST */ +/* Description: SETUP data, byte 1, bRequest */ + +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */ +#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ +#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */ +#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */ + +/* Register: USBD_WVALUEL */ +/* Description: SETUP data, byte 2, LSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */ +#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */ +#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */ + +/* Register: USBD_WVALUEH */ +/* Description: SETUP data, byte 3, MSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */ +#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */ +#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */ + +/* Register: USBD_WINDEXL */ +/* Description: SETUP data, byte 4, LSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */ +#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */ +#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */ + +/* Register: USBD_WINDEXH */ +/* Description: SETUP data, byte 5, MSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */ +#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */ +#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */ + +/* Register: USBD_WLENGTHL */ +/* Description: SETUP data, byte 6, LSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */ +#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */ +#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */ + +/* Register: USBD_WLENGTHH */ +/* Description: SETUP data, byte 7, MSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */ +#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */ +#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ + +/* Register: USBD_SIZE_EPOUT */ +/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ + +/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ +#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_SIZE_ISOOUT */ +/* Description: Number of bytes received last on this ISO OUT data endpoint */ + +/* Bit 16 : Zero-length data packet received */ +#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ +#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ + +/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */ +#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_ENABLE */ +/* Description: Enable USB */ + +/* Bit 0 : Enable USB */ +#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */ +#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */ + +/* Register: USBD_USBPULLUP */ +/* Description: Control of the USB pull-up */ + +/* Bit 0 : Control of the USB pull-up on the D+ line */ +#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */ +#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ + +/* Register: USBD_DPDMVALUE */ +/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ + +/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */ +#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ +#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ + +/* Register: USBD_DTOGGLE */ +/* Description: Data toggle control and status */ + +/* Bits 9..8 : Data toggle value */ +#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */ +#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */ +#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select bulk endpoint number */ +#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_EPINEN */ +/* Description: Endpoint IN enable */ + +/* Bit 8 : Enable ISO IN endpoint */ +#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */ + +/* Bit 7 : Enable IN endpoint 7 */ +#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */ +#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */ + +/* Bit 6 : Enable IN endpoint 6 */ +#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */ +#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */ + +/* Bit 5 : Enable IN endpoint 5 */ +#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */ +#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */ + +/* Bit 4 : Enable IN endpoint 4 */ +#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */ +#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */ + +/* Bit 3 : Enable IN endpoint 3 */ +#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */ +#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */ + +/* Bit 2 : Enable IN endpoint 2 */ +#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */ +#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */ + +/* Bit 1 : Enable IN endpoint 1 */ +#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */ +#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */ + +/* Bit 0 : Enable IN endpoint 0 */ +#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */ +#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */ + +/* Register: USBD_EPOUTEN */ +/* Description: Endpoint OUT enable */ + +/* Bit 8 : Enable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */ + +/* Bit 7 : Enable OUT endpoint 7 */ +#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */ + +/* Bit 6 : Enable OUT endpoint 6 */ +#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */ + +/* Bit 5 : Enable OUT endpoint 5 */ +#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */ + +/* Bit 4 : Enable OUT endpoint 4 */ +#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */ + +/* Bit 3 : Enable OUT endpoint 3 */ +#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */ + +/* Bit 2 : Enable OUT endpoint 2 */ +#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */ + +/* Bit 1 : Enable OUT endpoint 1 */ +#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */ + +/* Bit 0 : Enable OUT endpoint 0 */ +#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */ + +/* Register: USBD_EPSTALL */ +/* Description: STALL endpoints */ + +/* Bit 8 : Stall selected endpoint */ +#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */ +#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */ +#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */ +#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select endpoint number */ +#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_ISOSPLIT */ +/* Description: Controls the split of ISO buffers */ + +/* Bits 15..0 : Controls the split of ISO buffers */ +#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ + +/* Register: USBD_FRAMECNTR */ +/* Description: Returns the current value of the start of frame counter */ + +/* Bits 10..0 : Returns the current value of the start of frame counter */ +#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */ +#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ + +/* Register: USBD_LOWPOWER */ +/* Description: Controls USBD peripheral low power mode during USB suspend */ + +/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */ +#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */ +#define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */ + +/* Register: USBD_ISOINCONFIG */ +/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ + +/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ +#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */ +#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ + +/* Register: USBD_EPIN_PTR */ +/* Description: Description cluster: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPIN_MAXCNT */ +/* Description: Description cluster: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPIN_AMOUNT */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOIN_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOIN_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOIN_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_EPOUT_PTR */ +/* Description: Description cluster: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPOUT_MAXCNT */ +/* Description: Description cluster: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPOUT_AMOUNT */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOOUT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOOUT_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOOUT_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : Start the watchdog */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : Watchdog timeout */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_peripherals.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_peripherals.h new file mode 100644 index 0000000..9a25f39 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52840_peripherals.h @@ -0,0 +1,314 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52840_PERIPHERALS_H +#define _NRF52840_PERIPHERALS_H + + +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 9 + +#define POWER_FEATURE_VDDH_PRESENT + +/* Floating Point Unit */ +#define FPU_PRESENT +#define FPU_COUNT 1 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* Memory Watch Unit */ +#define MWU_PRESENT +#define MWU_COUNT 1 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 2 + +#define P0_PIN_NUM 32 +#define P1_PIN_NUM 16 + +/* ACL */ +#define ACL_PRESENT + +#define ACL_REGIONS_COUNT 8 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 8 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* NFC Tag */ +#define NFCT_PRESENT +#define NFCT_COUNT 1 + +#define NFCT_EASYDMA_MAXCNT_SIZE 9 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 5 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 +#define TIMER3_MAX_SIZE 32 +#define TIMER4_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 +#define TIMER3_CC_NUM 6 +#define TIMER4_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 3 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 +#define RTC2_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 3 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 4 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 +#define SPIM2_MAX_DATARATE 8 +#define SPIM3_MAX_DATARATE 32 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 +#define SPIM2_FEATURE_DCX_PRESENT 0 +#define SPIM3_FEATURE_DCX_PRESENT 1 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 +#define SPIM2_FEATURE_RXDELAY_PRESENT 0 +#define SPIM3_FEATURE_RXDELAY_PRESENT 1 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 16 +#define SPIM1_EASYDMA_MAXCNT_SIZE 16 +#define SPIM2_EASYDMA_MAXCNT_SIZE 16 +#define SPIM3_EASYDMA_MAXCNT_SIZE 16 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 3 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 16 +#define SPIS1_EASYDMA_MAXCNT_SIZE 16 +#define SPIS2_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 2 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 16 +#define TWIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 2 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 16 +#define TWIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 2 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 16 +#define UARTE1_EASYDMA_MAXCNT_SIZE 16 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +#define SAADC_CH_NUM 8 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 16 + +#define LPCOMP_FEATURE_HYST_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 4 + +#define PWM0_CH_NUM 4 +#define PWM1_CH_NUM 4 +#define PWM2_CH_NUM 4 +#define PWM3_CH_NUM 4 + +#define PWM0_EASYDMA_MAXCNT_SIZE 15 +#define PWM1_EASYDMA_MAXCNT_SIZE 15 +#define PWM2_EASYDMA_MAXCNT_SIZE 15 +#define PWM3_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + +/* Inter-IC Sound Interface */ +#define I2S_PRESENT +#define I2S_COUNT 1 + +#define I2S_EASYDMA_MAXCNT_SIZE 14 + +/* Universal Serial Bus Device */ +#define USBD_PRESENT +#define USBD_COUNT 1 + +#define USBD_EASYDMA_MAXCNT_SIZE 7 + +/* ARM TrustZone Cryptocell 310 */ +#define CRYPTOCELL_PRESENT +#define CRYPTOCELL_COUNT 1 + +/* Quad SPI */ +#define QSPI_PRESENT +#define QSPI_COUNT 1 + +#define QSPI_EASYDMA_MAXCNT_SIZE 20 + +#endif // _NRF52840_PERIPHERALS_H diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_common.ld b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_common.ld new file mode 100644 index 0000000..51f43d2 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_common.ld @@ -0,0 +1,170 @@ +/* Deprecated linker script for Nordic Semiconductor nRF52 devices, + * please use nrfx_common.ld. This version exists for backwards + * compatibility. + * + * Version: Sourcery G++ 4.5-1 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + PROVIDE(end = .); + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Check if text sections + data exceeds FLASH limit */ + DataInitFlashUsed = __bss_start__ - __data_start__; + CodeFlashUsed = __etext - ORIGIN(FLASH); + TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; + ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") + +} diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h new file mode 100644 index 0000000..377cf5e --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf52_to_nrf52840.h @@ -0,0 +1,161 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52840_H +#define NRF52_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif + + +/* LPCOMP */ +/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ +#ifndef LPCOMP_HYST_HYST_NoHyst + #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#endif +#ifndef LPCOMP_HYST_HYST_Hyst50mV + #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#endif + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/nrf_peripherals.h b/HAL_Driver/sdk/modules/nrfx/mdk/nrf_peripherals.h new file mode 100644 index 0000000..34247f8 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/nrf_peripherals.h @@ -0,0 +1,77 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_PERIPHERALS_H__ +#define NRF_PERIPHERALS_H__ + +/*lint ++flb "Enter library region */ + +#if defined(_WIN32) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf specific files when building for PC host */ +#else + + #if defined(NRF51) + #include "nrf51_peripherals.h" + + #elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" + #elif defined(NRF52811_XXAA) + #include "nrf52811_peripherals.h" + #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" + #elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" + + #elif defined(NRF9160_XXAA) + #include "nrf9160_peripherals.h" + + #else + #error "Device must be defined. See nrf.h." + #endif +#endif + +/*lint --flb "Leave library region" */ + +#endif // NRF_PERIPHERALS_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.c b/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.c new file mode 100644 index 0000000..a830388 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.c @@ -0,0 +1,300 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "system_nrf52840.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_36(void); +static bool errata_66(void); +static bool errata_98(void); +static bool errata_103(void); +static bool errata_115(void); +static bool errata_120(void); +static bool errata_136(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_98()){ + *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; + } + + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_120()){ + *(volatile uint32_t *)0x40029640ul = 0x200ul; + } + + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_36(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; +} + + +static bool errata_66(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; +} + + +static bool errata_98(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_103(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_115(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_120(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_136(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x3ul){ + return true; + } + } + + /* Apply by default for unknown devices until errata is confirmed fixed. */ + return true; +} + +/*lint --flb "Leave library region" */ diff --git a/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.h b/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.h new file mode 100644 index 0000000..9ce00cc --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/mdk/system_nrf52840.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52840_H +#define SYSTEM_NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52840_H */ diff --git a/HAL_Driver/sdk/modules/nrfx/nrfx.h b/HAL_Driver/sdk/modules/nrfx/nrfx.h new file mode 100644 index 0000000..188cae4 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/nrfx.h @@ -0,0 +1,49 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_H__ +#define NRFX_H__ + +#include +#include +#include +#include + +#endif // NRFX_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.c b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.c new file mode 100644 index 0000000..ba735b1 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.c @@ -0,0 +1,395 @@ +/** + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "nrfx_atomic.h" + +#ifndef NRFX_ATOMIC_USE_BUILT_IN + #define NRFX_ATOMIC_USE_BUILT_IN 0 +#endif // NRFX_ATOMIC_USE_BUILT_IN + +#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) +#define NRFX_ATOMIC_STREX_LDREX_PRESENT +#endif + +#if (NRFX_ATOMIC_USE_BUILT_IN == 0) && defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) +#include "nrfx_atomic_internal.h" +#endif + +uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_exchange_n(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data = value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif // NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + __atomic_store_n(p_data, value, __ATOMIC_SEQ_CST); + return value; +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(mov, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data = value; + NRFX_CRITICAL_SECTION_EXIT(); + return value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_fetch_or(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(orr, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data |= value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_or_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(orr, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data |= value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_fetch_and(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(and, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data &= value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_and_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(and, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data &= value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_fetch_xor(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(eor, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data ^= value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_xor_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(eor, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data ^= value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_fetch_add(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(add, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data += value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_add_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(add, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data += value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_fetch_sub(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(sub, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data -= value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_sub(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_sub_fetch(p_data, value, __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(sub, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data -= value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +bool nrfx_atomic_u32_cmp_exch(nrfx_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t desired) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + return __atomic_compare_exchange(p_data, + p_expected, + &desired, + 1, + __ATOMIC_SEQ_CST, + __ATOMIC_SEQ_CST); +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + return nrfx_atomic_internal_cmp_exch(p_data, p_expected, desired); +#else + bool result; + NRFX_CRITICAL_SECTION_ENTER(); + if (*p_data == *p_expected) + { + *p_data = desired; + result = true; + } + else + { + *p_expected = *p_data; + result = false; + } + NRFX_CRITICAL_SECTION_EXIT(); + return result; +#endif +} + +uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + uint32_t expected = *p_data; + uint32_t new_val; + do { + if (expected >= value) + { + new_val = expected - value; + } + else + { + new_val = expected; + } + } while (!__atomic_compare_exchange(p_data, &expected, &new_val, + 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)); + return expected; +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); + (void) new_val; + return old_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + uint32_t old_val = *p_data; + *p_data -= value; + NRFX_CRITICAL_SECTION_EXIT(); + return old_val; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value) +{ +#if NRFX_ATOMIC_USE_BUILT_IN + uint32_t expected = *p_data; + uint32_t new_val; + do { + if (expected >= value) + { + new_val = expected - value; + } + else + { + new_val = expected; + } + } while (!__atomic_compare_exchange(p_data, &expected, &new_val, + 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)); + return new_val; +#elif defined(NRFX_ATOMIC_STREX_LDREX_PRESENT) + uint32_t old_val; + uint32_t new_val; + NRFX_ATOMIC_OP(sub_hs, old_val, new_val, p_data, value); + (void) old_val; + return new_val; +#else + NRFX_CRITICAL_SECTION_ENTER(); + *p_data -= value; + uint32_t new_value = *p_data; + NRFX_CRITICAL_SECTION_EXIT(); + return new_value; +#endif //NRFX_ATOMIC_USE_BUILT_IN +} + +uint32_t nrfx_atomic_flag_set_fetch(nrfx_atomic_flag_t * p_data) +{ + return nrfx_atomic_u32_fetch_or(p_data, 1); +} + +uint32_t nrfx_atomic_flag_set(nrfx_atomic_flag_t * p_data) +{ + return nrfx_atomic_u32_or(p_data, 1); +} + +uint32_t nrfx_atomic_flag_clear_fetch(nrfx_atomic_flag_t * p_data) +{ + return nrfx_atomic_u32_fetch_and(p_data, 0); +} + +uint32_t nrfx_atomic_flag_clear(nrfx_atomic_flag_t * p_data) +{ + return nrfx_atomic_u32_and(p_data, 0); +} diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.h b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.h new file mode 100644 index 0000000..eed6836 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic.h @@ -0,0 +1,288 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_ATOMIC_H__ +#define NRFX_ATOMIC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_atomic Atomic operations API + * @ingroup nrfx + * @{ + * + * @brief This module implements C11 stdatomic.h simplified API. + * + * At this point, only Cortex-M3 and M4 cores are supported (LDREX/STREX instructions). + * Atomic types are limited to @ref nrfx_atomic_u32_t and @ref nrfx_atomic_flag_t. + */ + + +/** + * @brief Atomic 32-bit unsigned type. + */ +typedef volatile uint32_t nrfx_atomic_u32_t; + +/** + * @brief Atomic 1-bit flag type (technically 32-bit). + */ +typedef volatile uint32_t nrfx_atomic_flag_t; + +/** + * @brief Function for storing a value to an atomic object and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_store(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for storing a value to an atomic object and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_store(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical OR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_or(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical OR operation on an atomic object + * and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the OR operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_or(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical AND operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_and(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical AND operation on an atomic object + * and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the AND operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_and(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical XOR operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_xor(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical XOR operation on an atomic object + * and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the XOR operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_xor(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running an arithmetic ADD operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_add(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running an arithmetic ADD operation on an atomic object + * and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the ADD operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_add(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running an arithmetic SUB operation on an atomic object + * and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Old value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_sub(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running an arithmetic SUB operation on an atomic object + * and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_sub(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for atomic conditional value replacement. + * + * Atomically compares the value pointed to by @p p_data with the value pointed to by @p p_expected. + * If those are equal, replaces the former with desired. Otherwise, loads the actual value + * pointed to by @p p_data into @p *p_expected. + * + * @param p_data Atomic memory pointer to test and modify. + * @param p_expected Pointer to the test value. + * @param desired Value to be stored to atomic memory. + * + * @retval true @p *p_data was equal to @p *p_expected. + * @retval false @p *p_data was not equal to @p *p_expected. + */ +bool nrfx_atomic_u32_cmp_exch(nrfx_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t desired); + +/** + * @brief Function for running an arithmetic SUB operation on an atomic object + * if object >= value, and returning its previous value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return Previous value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_fetch_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running an arithmetic SUB operation on an atomic object + * if object >= value, and returning its new value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of the second operand in the SUB operation. + * + * @return New value stored in the atomic object. + */ +uint32_t nrfx_atomic_u32_sub_hs(nrfx_atomic_u32_t * p_data, uint32_t value); + +/** + * @brief Function for running a logical one bit flag set operation + * on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic flag memory pointer. + * + * @return Previous flag value. + */ +uint32_t nrfx_atomic_flag_set_fetch(nrfx_atomic_flag_t * p_data); + +/** + * @brief Function for running a logical one bit flag set operation + * on an atomic object and returning its new value. + * + * @param[in] p_data Atomic flag memory pointer. + * + * @return New flag value. + */ +uint32_t nrfx_atomic_flag_set(nrfx_atomic_flag_t * p_data); + +/** + * @brief Function for running a logical one bit flag clear operation + * on an atomic object and returning its previous value. + * + * @param[in] p_data Atomic flag memory pointer. + * + * @return Previous flag value. + */ +uint32_t nrfx_atomic_flag_clear_fetch(nrfx_atomic_flag_t * p_data); + +/** + * @brief Function for running a logical one bit flag clear operation + * on an atomic object and returning its new value. + * + * @param[in] p_data Atomic flag memory pointer. + * + * @return New flag value. + */ +uint32_t nrfx_atomic_flag_clear(nrfx_atomic_flag_t * p_data); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_ATOMIC_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic_internal.h b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic_internal.h new file mode 100644 index 0000000..1e6be21 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_atomic_internal.h @@ -0,0 +1,334 @@ +/** + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_ATOMIC_INTERNAL_H__ +#define NRFX_ATOMIC_INTERNAL_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Only Cortex-M cores > 3 support LDREX/STREX instructions. */ +#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) == 0 +#error "Unsupported core version" +#endif + +#if defined ( __CC_ARM ) +static __asm uint32_t nrfx_atomic_internal_mov(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + /* The base standard specifies that arguments are passed in core registers r0-r3 and on the stack. + * Registers r4 and r5 must be saved on the stack. Note that only even number of register pushes are + * allowed. This is a requirement of the Procedure Call Standard for the ARM Architecture [AAPCS]. + */ + push {r4, r5} + mov r4, r0 + +loop_mov + ldrex r0, [r4] + mov r5, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_mov + + str r5, [r2] + pop {r4, r5} + bx lr +} + + +static __asm uint32_t nrfx_atomic_internal_orr(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_orr + ldrex r0, [r4] + orr r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_orr + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrfx_atomic_internal_and(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_and + ldrex r0, [r4] + and r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_and + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrfx_atomic_internal_eor(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_eor + ldrex r0, [r4] + eor r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_eor + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrfx_atomic_internal_add(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_add + ldrex r0, [r4] + add r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_add + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm uint32_t nrfx_atomic_internal_sub(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_sub + ldrex r0, [r4] + sub r5, r0, r1 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_sub + + str r5, [r2] + pop {r4, r5} + bx lr +} + +static __asm bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t value) +{ +#define RET_REG r0 +#define P_EXPC r1 +#define VALUE r2 +#define STR_RES r3 +#define P_DATA r4 +#define EXPC_VAL r5 +#define ACT_VAL r6 + + push {r4-r6} + mov P_DATA, r0 + mov RET_REG, #0 + +loop_cmp_exch + ldrex ACT_VAL, [P_DATA] + ldr EXPC_VAL, [P_EXPC] + cmp ACT_VAL, EXPC_VAL + ittee eq + strexeq STR_RES, VALUE, [P_DATA] + moveq RET_REG, #1 + strexne STR_RES, ACT_VAL, [P_DATA] + strne ACT_VAL, [P_EXPC] + cmp STR_RES, #0 + itt ne + movne RET_REG, #0 + bne loop_cmp_exch + + pop {r4-r6} + bx lr + +#undef RET_REG +#undef P_EXPC +#undef VALUE +#undef STR_RES +#undef P_DATA +#undef EXPC_VAL +#undef ACT_VAL +} + +static __asm uint32_t nrfx_atomic_internal_sub_hs(nrfx_atomic_u32_t * p_ptr, + uint32_t value, + uint32_t * p_new) +{ + push {r4, r5} + mov r4, r0 + +loop_sub_ge + ldrex r0, [r4] + cmp r0, r1 + ite hs + subhs r5, r0, r1 + movlo r5, r0 + strex r3, r5, [r4] + cmp r3, #0 + bne loop_sub_ge + + str r5, [r2] + pop {r4, r5} + bx lr +} + + +#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ + old_val = nrfx_atomic_internal_##asm_op(ptr, value, &new_val) + +#elif defined ( __ICCARM__ ) || defined ( __GNUC__ ) + +/** + * @brief Atomic operation generic macro. + * + * @param[in] asm_op Operation: mov, orr, and, eor, add, sub. + * @param[out] old_val Atomic object output (uint32_t), value before operation. + * @param[out] new_val Atomic object output (uint32_t), value after operation. + * @param[in] value Atomic operation operand. + */ +#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \ +{ \ + uint32_t tmp_reg; \ + __ASM volatile( \ + "1: ldrex %["#old_val"], [%["#ptr"]]\n" \ + NRFX_ATOMIC_OP_##asm_op(new_val, old_val, value) \ + " strex %[tmp_reg], %["#new_val"], [%["#ptr"]]\n" \ + " teq %[tmp_reg], #0\n" \ + " bne.n 1b" \ + : \ + [old_val] "=&r" (old_val), \ + [new_val] "=&r" (new_val), \ + [tmp_reg] "=&r" (tmp_reg) \ + : \ + [ptr] "r" (ptr), \ + [value] "r" (value) \ + : "cc"); \ + (void)tmp_reg; \ +} + +#define NRFX_ATOMIC_OP_mov(new_val, old_val, value) "mov %["#new_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_orr(new_val, old_val, value) "orr %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_and(new_val, old_val, value) "and %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_eor(new_val, old_val, value) "eor %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_add(new_val, old_val, value) "add %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_sub(new_val, old_val, value) "sub %["#new_val"], %["#old_val"], %["#value"]\n" +#define NRFX_ATOMIC_OP_sub_hs(new_val, old_val, value) \ + "cmp %["#old_val"], %["#value"]\n " \ + "ite hs\n" \ + "subhs %["#new_val"], %["#old_val"], %["#value"]\n" \ + "movlo %["#new_val"], %["#old_val"]\n" + +static inline bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data, + uint32_t * p_expected, + uint32_t value) +{ + bool res = false; + /* Temporary register used in the inline asm code for getting the result + * of the strex* operations (no need to initialize it). + */ + uint32_t tmp_reg; + uint32_t act_val = 0; + uint32_t exp_val = 0; + __ASM volatile( + "1: ldrex %[act_val], [%[ptr]]\n" + " ldr %[exp_val], [%[expc]]\n" + " cmp %[act_val], %[exp_val]\n" + " ittee eq\n" + " strexeq %[tmp_reg], %[value], [%[ptr]]\n" + " moveq %[res], #1\n" + " strexne %[tmp_reg], %[act_val], [%[ptr]]\n" + " strne %[act_val], [%[expc]]\n" + " cmp %[tmp_reg], #0\n" + " itt ne\n" + " movne %[res], #0\n" + " bne.n 1b" + : + [res] "=&r" (res), + [exp_val] "=&r" (exp_val), + [act_val] "=&r" (act_val), + [tmp_reg] "=&r" (tmp_reg) + : + "0" (res), + "1" (exp_val), + "2" (act_val), + [expc] "r" (p_expected), + [ptr] "r" (p_data), + [value] "r" (value) + : "cc"); + (void)tmp_reg; + return res; +} + +#else +#error "Unsupported compiler" +#endif + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_ATOMIC_INTERNAL_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_coredep.h b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_coredep.h new file mode 100644 index 0000000..b3b7df7 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_coredep.h @@ -0,0 +1,184 @@ +/** + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_COREDEP_H__ +#define NRFX_COREDEP_H__ + +/** + * @defgroup nrfx_coredep Core-dependent functionality + * @{ + * @ingroup nrfx + * @brief Module containing functions with core-dependent implementation, like delay. + */ + +#if defined(__NRFX_DOXYGEN__) + +/** @brief Core frequency (in MHz). */ +#define NRFX_DELAY_CPU_FREQ_MHZ +/** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */ +#define NRFX_DELAY_DWT_PRESENT +/** + * @brief Number of cycles consumed by one iteration of the internal loop + * in the function @ref nrfx_coredep_delay_us. + * + * This value can be specified externally (for example, when the SoC is emulated). + */ +#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES + +#elif defined(NRF51) + #define NRFX_DELAY_CPU_FREQ_MHZ 16 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#elif defined(NRF52840_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#elif defined(NRF9160_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#else + #error "Unknown device." +#endif + +/** + * @brief Function for delaying execution for a number of microseconds. + * + * The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to + * maximum uint32_t capacity divided by frequency. For example: + * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds) + * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds) + * + * @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES + * + * @param time_us Number of microseconds to wait. + */ +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if NRFX_CHECK(NRFX_DELAY_DWT_BASED) + +#if !NRFX_DELAY_DWT_PRESENT +#error "DWT unit not present in the SoC that is used." +#endif + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + + // Save the current state of the DEMCR register to be able to restore it before exiting + // this function. Enable the trace and debug blocks (including DWT). + uint32_t core_debug = CoreDebug->DEMCR; + CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; + + // Save the current state of the CTRL register in the DWT block. Make sure + // that the cycle counter is enabled. + uint32_t dwt_ctrl = DWT->CTRL; + DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; + + // Store start value of the cycle counter. + uint32_t cyccnt_initial = DWT->CYCCNT; + + // Delay required time. + while ((DWT->CYCCNT - cyccnt_initial) < time_cycles) + {} + + // Restore preserved registers. + DWT->CTRL = dwt_ctrl; + CoreDebug->DEMCR = core_debug; +} +#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED) + + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + + // Allow overriding the number of cycles per loop iteration, in case it is + // needed to adjust this number externally (for example, when the SoC is + // emulated). + #ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES + #if defined(NRF51) + // The loop takes 4 cycles: 1 for SUBS, 3 for BHI. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4 + #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) + // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states + // for each instruction. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7 + #else + // The loop takes 3 cycles: 1 for SUBS, 2 for BHI. + #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3 + #endif + #endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES + // Align the machine code, so that it can be cached properly and no extra + // wait states appear. + __ALIGN(16) + static const uint16_t delay_machine_code[] = { + 0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + + typedef void (* delay_func_t)(uint32_t); + const delay_func_t delay_cycles = + // Set LSB to 1 to execute the code in the Thumb mode. + (delay_func_t)((((uint32_t)delay_machine_code) | 1)); + uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + delay_cycles(cycles); +} + +#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY) + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRFX_COREDEP_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs.h b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs.h new file mode 100644 index 0000000..6204df1 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs.h @@ -0,0 +1,60 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_H__ +#define NRFX_IRQS_H__ + +#if defined(NRF51) + #include +#elif defined(NRF52810_XXAA) + #include +#elif defined(NRF52811_XXAA) + #include +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #include +#elif defined(NRF52840_XXAA) + #include +#elif defined(NRF9160_XXAA) + #include +#else + #error "Unknown device." +#endif + +#endif // NRFX_IRQS_H__ diff --git a/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h new file mode 100644 index 0000000..04f4665 --- /dev/null +++ b/HAL_Driver/sdk/modules/nrfx/soc/nrfx_irqs_nrf52840.h @@ -0,0 +1,210 @@ +/** + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRFX_IRQS_NRF52840_H__ +#define NRFX_IRQS_NRF52840_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif + +// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif + +// NFCT_IRQn +#define nrfx_nfct_irq_handler NFCT_IRQHandler + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_LPCOMP_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler +#else +#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler +#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler +#endif + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_EGU2_IRQn +#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler + +// SWI3_EGU3_IRQn +#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler + +// SWI4_EGU4_IRQn +#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler + +// SWI5_EGU5_IRQn +#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler + +// TIMER3_IRQn +#define nrfx_timer_3_irq_handler TIMER3_IRQHandler + +// TIMER4_IRQn +#define nrfx_timer_4_irq_handler TIMER4_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + +// MWU_IRQn + +// PWM1_IRQn +#define nrfx_pwm_1_irq_handler PWM1_IRQHandler + +// PWM2_IRQn +#define nrfx_pwm_2_irq_handler PWM2_IRQHandler + +// SPIM2_SPIS2_SPI2_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#else +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#endif + +// RTC2_IRQn +#define nrfx_rtc_2_irq_handler RTC2_IRQHandler + +// I2S_IRQn +#define nrfx_i2s_irq_handler I2S_IRQHandler + +// FPU_IRQn + +// USBD_IRQn +#define nrfx_usbd_irq_handler USBD_IRQHandler + +// UARTE1_IRQn +#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler + +// QSPI_IRQn +#define nrfx_qspi_irq_handler QSPI_IRQHandler + +// CRYPTOCELL_IRQn + +// PWM3_IRQn +#define nrfx_pwm_3_irq_handler PWM3_IRQHandler + +// SPIM3_IRQn +#define nrfx_spim_3_irq_handler SPIM3_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52840_H__ diff --git a/HAL_Driver/spi_gcc_nrf52.ld b/HAL_Driver/spi_gcc_nrf52.ld new file mode 100644 index 0000000..c08bc8e --- /dev/null +++ b/HAL_Driver/spi_gcc_nrf52.ld @@ -0,0 +1,102 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x80000 + FLASH_STORAGE (rx) : ORIGIN = 0x80000, LENGTH = 0x80000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 +} + +GROUP ( + libc_nano.a + libm.a + libgcc.a +) + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +__stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 0x3000; +_eheap = ORIGIN(RAM) + LENGTH(RAM) - 4; + +_fs_storage_start = ORIGIN(FLASH_STORAGE); +_fs_storage_size = LENGTH(FLASH_STORAGE); + + +SECTIONS +{ + .fs_data : + { + PROVIDE(__start_fs_data = .); + KEEP(*(.fs_data)) + PROVIDE(__stop_fs_data = .); + } > RAM +} INSERT AFTER .data; + +SECTIONS +{ + .pwr_mgmt_data : + { + PROVIDE(__start_pwr_mgmt_data = .); + KEEP(*(SORT(.pwr_mgmt_data*))) + PROVIDE(__stop_pwr_mgmt_data = .); + } > FLASH + + .rodata.host_cmd_handlers : ALIGN(4) + { + __host_cmd_handlers_start = .; + KEEP(*(.host_cmd_handlers)) /* Host command handlers section */ + __host_cmd_handlers_end = .; + } >FLASH + +} INSERT AFTER .text + +SECTIONS +{ + . = ALIGN(4); + .mem_section_dummy_ram : + { + } + .log_dynamic_data : + { + PROVIDE(__start_log_dynamic_data = .); + KEEP(*(SORT(.log_dynamic_data*))) + PROVIDE(__stop_log_dynamic_data = .); + } > RAM + .log_filter_data : + { + PROVIDE(__start_log_filter_data = .); + KEEP(*(SORT(.log_filter_data*))) + PROVIDE(__stop_log_filter_data = .); + } > RAM + +} INSERT AFTER .data; + +SECTIONS +{ + .mem_section_dummy_rom : + { + } + .log_const_data : + { + PROVIDE(__start_log_const_data = .); + KEEP(*(SORT(.log_const_data*))) + PROVIDE(__stop_log_const_data = .); + } > FLASH + .log_backends : + { + PROVIDE(__start_log_backends = .); + KEEP(*(SORT(.log_backends*))) + PROVIDE(__stop_log_backends = .); + } > FLASH + .nrf_balloc : + { + PROVIDE(__start_nrf_balloc = .); + KEEP(*(.nrf_balloc)) + PROVIDE(__stop_nrf_balloc = .); + } > FLASH + +} INSERT AFTER .text + +INCLUDE "nrf52_common.ld" diff --git a/HAL_Driver/src/board_hal.c b/HAL_Driver/src/board_hal.c new file mode 100755 index 0000000..11d49ec --- /dev/null +++ b/HAL_Driver/src/board_hal.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019 Fingerprint Cards AB + * + * All rights are reserved. + * Proprietary and confidential. + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Any use is subject to an appropriate license granted by Fingerprint Cards AB. + */ + +/** + * @file sensor.c + * @brief Sensor control functions. + */ + +#include +#include + +#include "nrf_gpio.h" +#include "nrf_drv_spi.h" +#include "app_util_platform.h" +#include "nrf_gpio.h" +#include "nrf_delay.h" +#include "boards.h" +#include "app_error.h" +#include +#define NRF_LOG_MODULE_NAME APP +#include "nrf_log.h" +#include "nrf_log_ctrl.h" +#include "nrf_gpiote.h" +#include "nrf_drv_gpiote.h" + +#include "platform_spi.h" +// #include "fpc_timebase.h" + +#define FPC_PIN_RESET ARDUINO_2_PIN +#define FPC_PIN_INTERRUPT ARDUINO_A2_PIN + +static volatile bool sensor_interrupt = false; + +static void nordic_bmlite_gpio_init (void); + +void nordic_board_init(uint32_t speed_hz) +{ + + if (NRF_UICR->REGOUT0 != UICR_REGOUT0_VOUT_3V3) + { + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->REGOUT0 = UICR_REGOUT0_VOUT_3V3; + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + } + NRF_USBD->ENABLE = 1; + + nordic_bmlite_gpio_init(); + nordic_bmlite_spi_init(speed_hz); +} + +void nordic_bmlite_reset(bool state) +{ + if(!state) { + nrf_drv_gpiote_out_set(FPC_PIN_RESET); + } else { + nrf_drv_gpiote_out_clear(FPC_PIN_RESET); + } +} + +bool nordic_bmlite_get_status(void) +{ + return nrf_drv_gpiote_in_is_set(FPC_PIN_INTERRUPT); +} + +static void nordic_bmlite_gpio_init(void) +{ + ret_code_t err_code; + err_code = nrf_drv_gpiote_init(); + APP_ERROR_CHECK(err_code); + nrf_drv_gpiote_out_config_t out_config = GPIOTE_CONFIG_OUT_SIMPLE(true); + err_code = nrf_drv_gpiote_out_init(FPC_PIN_RESET, &out_config); + APP_ERROR_CHECK(err_code); + nrf_drv_gpiote_out_task_enable(FPC_PIN_RESET); //Enable task for output pin (toggle) + + nrf_drv_gpiote_in_config_t config = GPIOTE_CONFIG_IN_SENSE_LOTOHI(true); + err_code = nrf_drv_gpiote_in_init(FPC_PIN_INTERRUPT, &config, NULL); + APP_ERROR_CHECK(err_code); + nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_IN_0); + return; +} + diff --git a/HAL_Driver/src/gcc_startup_nrf52840.S b/HAL_Driver/src/gcc_startup_nrf52840.S new file mode 100644 index 0000000..98ef8dc --- /dev/null +++ b/HAL_Driver/src/gcc_startup_nrf52840.S @@ -0,0 +1,410 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + + .syntax unified + .arch armv7e-m + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 8192 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 8192 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMon_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + .long NFCT_IRQHandler + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_LPCOMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_EGU2_IRQHandler + .long SWI3_EGU3_IRQHandler + .long SWI4_EGU4_IRQHandler + .long SWI5_EGU5_IRQHandler + .long TIMER3_IRQHandler + .long TIMER4_IRQHandler + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long MWU_IRQHandler + .long PWM1_IRQHandler + .long PWM2_IRQHandler + .long SPIM2_SPIS2_SPI2_IRQHandler + .long RTC2_IRQHandler + .long I2S_IRQHandler + .long FPU_IRQHandler + .long USBD_IRQHandler + .long UARTE1_IRQHandler + .long QSPI_IRQHandler + .long CRYPTOCELL_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long PWM3_IRQHandler + .long 0 /*Reserved */ + .long SPIM3_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to. + * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__bss_start__ + + subs r3, r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler + IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler + IRQ NFCT_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_LPCOMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_EGU2_IRQHandler + IRQ SWI3_EGU3_IRQHandler + IRQ SWI4_EGU4_IRQHandler + IRQ SWI5_EGU5_IRQHandler + IRQ TIMER3_IRQHandler + IRQ TIMER4_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + IRQ MWU_IRQHandler + IRQ PWM1_IRQHandler + IRQ PWM2_IRQHandler + IRQ SPIM2_SPIS2_SPI2_IRQHandler + IRQ RTC2_IRQHandler + IRQ I2S_IRQHandler + IRQ FPU_IRQHandler + IRQ USBD_IRQHandler + IRQ UARTE1_IRQHandler + IRQ QSPI_IRQHandler + IRQ CRYPTOCELL_IRQHandler + IRQ PWM3_IRQHandler + IRQ SPIM3_IRQHandler + + .end diff --git a/HAL_Driver/src/platform.c b/HAL_Driver/src/platform.c new file mode 100644 index 0000000..c814aff --- /dev/null +++ b/HAL_Driver/src/platform.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 Fingerprint Cards AB + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file platform.c + * @brief Platform specific functions + */ + + +#include "fpc_com_result.h" +#include "platform.h" +#include "bmlite.h" +#include "boards.h" +#include "platform_spi.h" +#include "btns_leds.h" + +bool platform_init(uint32_t speed_hz) +{ + nordic_board_init(4000000); + platform_timebase_init(); + bsp_board_init(BSP_INIT_LEDS | BSP_INIT_BUTTONS); + + platform_bmlite_reset(); + return true; +} + +uint32_t platform_get_time(void) +{ + return platform_timebase_get_tick(); +} + +void platform_bmlite_reset(void) +{ + nordic_bmlite_reset(true); + platform_timebase_busy_wait(100); + nordic_bmlite_reset(false); + platform_timebase_busy_wait(100); +} + +fpc_com_result_t platform_bmlite_send(uint16_t size, const uint8_t *data, uint32_t timeout, + void *session) +{ + uint8_t buff[size]; + + return nordic_bmlite_spi_write_read((uint8_t *)data, buff, size, false); +} + +fpc_com_result_t platform_bmlite_receive(uint16_t size, uint8_t *data, uint32_t timeout, + void *session) +{ + volatile uint32_t start_time = platform_get_time(); + volatile uint32_t curr_time = start_time; + while (!nordic_bmlite_get_status() && + (curr_time = platform_get_time()) - start_time < timeout) { + } + if(curr_time - start_time >= timeout) { + return FPC_COM_RESULT_TIMEOUT; + } + + uint8_t buff[size]; + return nordic_bmlite_spi_write_read(buff, data, size, false); +} + +void platform_halt_if_debug(void) +{ + // Stop here if debugger is attached. + __BKPT(0xFC); +} + +void platform_sw_reset(void) +{ + NVIC_SystemReset(); + while(1); +} + +void platform_set_led(platform_led_status_t color) +{ + board_set_led(color); +} + +uint32_t platform_get_button_press_time(void) +{ + return board_get_button_press_time(); +} diff --git a/HAL_Driver/src/platform_btns_leds.c b/HAL_Driver/src/platform_btns_leds.c new file mode 100644 index 0000000..072baf1 --- /dev/null +++ b/HAL_Driver/src/platform_btns_leds.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2019 Fingerprint Cards AB + * + * All rights are reserved. + * Proprietary and confidential. + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Any use is subject to an appropriate license granted by Fingerprint Cards AB. + */ + +/** + * @file btns_leds.c + * @brief Sensor control functions. + */ + +#include "boards.h" +#include "btns_leds.h" + +#include +#include +#include + +/** LED ON time in ms */ +#define LED_SOLID_ON_TIME_MS 700 + +/** LED blink time in ms */ +#define LED_BLINK_TIME_MS 200 + +/** Board button used for app control */ +#define BMLITE_BUTTON 3 + +static uint32_t btn_press_start; +static uint32_t btn_pressed; + +static void _board_set_leds(uint8_t color) +{ + uint32_t i; + + for(i=0; i<4; i++) { + if (color & 1) { + bsp_board_led_on(i); + } else { + bsp_board_led_off(i); + } + color = color >> 1; + } +} + +void board_set_led(platform_led_status_t color) +{ + _board_set_leds(color); + // if (status == FPC_HAL_LED_STATUS_OFF) { + // board_set_leds(0); + // } else if (status == FPC_HAL_LED_STATUS_SOLID) { + // board_set_leds(color); + // platform_timebase_busy_wait(LED_SOLID_ON_TIME_MS); + // board_set_leds(0); + // } else if (status == FPC_HAL_LED_STATUS_ON) { + // board_set_leds(color); + // } else { + // uint32_t led_status = (uint32_t)(status - FPC_HAL_LED_STATUS_ONE_BLINK + 1); + // for (uint32_t i = 0; i < (led_status * 2); i++) { + // if (i % 2 == 0) { + // board_set_leds(0x8 + color); + // } else { + // board_set_leds(0x8); + // } + // platform_timebase_busy_wait(LED_BLINK_TIME_MS); + // } + // } +} + +uint32_t board_get_button_press_time() +{ + uint32_t time = 0; + if (bsp_board_button_state_get(BMLITE_BUTTON)) { + if (btn_pressed == 0) { + btn_press_start = platform_timebase_get_tick(); + btn_pressed = 1; + } + } else { // Btn released + if (btn_pressed) { + uint32_t curr_time = platform_timebase_get_tick(); + if (curr_time > btn_press_start) { + time = curr_time - btn_press_start; + } else { + time = curr_time + ~btn_press_start + 1; + } + btn_pressed = 0; + } + } + return time; +} diff --git a/HAL_Driver/src/platform_spi.c b/HAL_Driver/src/platform_spi.c new file mode 100755 index 0000000..6de0c20 --- /dev/null +++ b/HAL_Driver/src/platform_spi.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2019 Fingerprint Cards AB + * + * All rights are reserved. + * Proprietary and confidential. + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Any use is subject to an appropriate license granted by Fingerprint Cards AB. + */ + +/** + * @file spi.c + * @brief SPI functions + */ + +#include +#include +#include + +#include "nrf_drv_spi.h" +#include "app_util_platform.h" +#include "nrf_gpio.h" +#include "nrf_delay.h" +#include "boards.h" +#include "app_error.h" +#include +#define NRF_LOG_MODULE_NAME APP +#include "nrf_log.h" +#include "nrf_log_ctrl.h" +#include "nrf_gpiote.h" +#include "nrf_drv_gpiote.h" + +#include "platform.h" +#include "fpc_bep_types.h" + + +#define SPI_INSTANCE 0 /**< SPI instance index. */ + +#define BMLITE_CS_PIN ARDUINO_8_PIN +#define BMLITE_MISO_PIN ARDUINO_12_PIN +#define BMLITE_MOSI_PIN ARDUINO_11_PIN +#define BMLITE_CLK_PIN ARDUINO_13_PIN + +static const nrf_drv_spi_t spi = NRF_DRV_SPI_INSTANCE(SPI_INSTANCE); /**< SPI instance. */ +static volatile bool spi_xfer_done; /**< Flag used to indicate that SPI instance completed the transfer. */ +static uint8_t *m_tx_buf; +static uint8_t *m_rx_buf; + +nrf_drv_spi_config_t spi_config = NRF_DRV_SPI_DEFAULT_CONFIG; + +/** + * @brief SPI user event handler. + * @param event + */ +static void spi_event_handler(nrf_drv_spi_evt_t const * p_event, + void * p_context) +{ + if( p_event->type == NRF_DRV_SPI_EVENT_DONE) { + spi_xfer_done = true; + } +} + +static void spi_write_read(uint8_t *write, uint8_t *read, size_t size, bool leave_cs_asserted) +{ + + spi_xfer_done = false; + m_tx_buf = write; + m_rx_buf = read; + + nrf_drv_gpiote_out_clear(BMLITE_CS_PIN); + + APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, m_tx_buf, size, m_rx_buf, size)); + + while (!spi_xfer_done) + { + __WFE(); + } + + if(!leave_cs_asserted) + nrf_drv_gpiote_out_set(BMLITE_CS_PIN); + +} + +fpc_bep_result_t nordic_bmlite_spi_write_read(uint8_t *write, uint8_t *read, size_t size, + bool leave_cs_asserted) +{ + + uint8_t num_of_rounds = size/255, i; + uint8_t *p_write = write, *p_read = read; + + for(i=0; i + +#include "nrf_drv_systick.h" +#include "nrf.h" +#include "nrf_drv_timer.h" +#include "nrfx_config.h" + +const nrf_drv_timer_t TIMER_LED = NRF_DRV_TIMER_INSTANCE(0); + +static volatile uint32_t systick; + +/** + * @brief Handler for timer events. + */ +static void timer_event_handler(nrf_timer_event_t event_type, void* p_context) +{ + + switch (event_type) + { + case NRF_TIMER_EVENT_COMPARE0: + systick++; + break; + + default: + //Do nothing. + break; + } +} + + +void platform_timebase_init(void) +{ + uint32_t time_ms = 1; //Time (in miliseconds) between consecutive compare events. + uint32_t time_ticks; + uint32_t err_code = NRF_SUCCESS; + + nrf_drv_timer_config_t timer_cfg = NRF_DRV_TIMER_DEFAULT_CONFIG; + err_code = nrf_drv_timer_init(&TIMER_LED, &timer_cfg, timer_event_handler); + APP_ERROR_CHECK(err_code); + + time_ticks = nrf_drv_timer_ms_to_ticks(&TIMER_LED, time_ms); + + nrf_drv_timer_extended_compare( + &TIMER_LED, NRF_TIMER_CC_CHANNEL0, time_ticks, NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK, true); + + nrf_drv_timer_enable(&TIMER_LED); + +} + +void platform_timebase_busy_wait(uint32_t delay) +{ + uint32_t start; + uint32_t delay_internal = 0; + + /* Ensure minimum delay or skip if delay is zero*/ + if (delay) { + delay_internal = delay + 1; + start = systick; + while ((systick - start) < delay_internal) { + } + } +} + +uint32_t platform_timebase_get_tick(void) +{ + return systick; +} diff --git a/hcp/LICENSE.txt b/hcp/LICENSE.txt new file mode 100644 index 0000000..298f0e2 --- /dev/null +++ b/hcp/LICENSE.txt @@ -0,0 +1,174 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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+[(P)43(a)6(y)-24(l)22(o)-8(a)5(d)]TJ +ET + Q +Q +1 0.85098 0.396078 rg +147.809 47.195 49.16 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +147.809 -49.489 49.16 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 159.842909 61.961803 Tm +/f-0-0 1 Tf +[(S)-11(e)29(q)-11( )27(N)42(r)]TJ +ET + Q +Q +1 0.85098 0.396078 rg +98.648 47.195 49.16 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +98.648 -49.489 49.16 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 115.938789 61.961803 Tm +/f-0-0 1 Tf +[(S)-11(i)21(z)-3(e)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +49.48 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +49.48 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 66.705993 85.530543 Tm +/f-0-0 1 Tf +[(S)-12(i)20(z)-4(e)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +98.641 70.656 270.359 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +98.641 -74.089 270.359 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 219.043665 85.530543 Tm +/f-0-0 1 Tf +[(P)42(a)5(y)-25(l)21(o)-9(a)4(d)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +369 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +369 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 386.387476 85.530543 Tm +/f-0-0 1 Tf +(CRC)Tj +ET + Q +Q +0.572549 0.803922 0.862745 rg +0.324 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +0.324 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 9.300251 85.530543 Tm +/f-0-0 1 Tf +[(Ch)57(a)4(n)-11(n)-12(e)29(l)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +49.48 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +49.48 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 66.705993 85.530543 Tm +/f-0-0 1 Tf +[(S)-12(i)20(z)-4(e)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +98.641 70.656 270.359 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +98.641 -74.089 270.359 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 219.043665 85.530543 Tm +/f-0-0 1 Tf +[(P)42(a)5(y)-25(l)21(o)-9(a)4(d)]TJ +ET + Q +Q +0.572549 0.803922 0.862745 rg +369 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +369 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 386.387476 85.530543 Tm +/f-0-0 1 Tf +(CRC)Tj +ET + Q +Q +0.572549 0.803922 0.862745 rg +0.324 70.656 49.156 23.422 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +0.324 -74.089 49.156 -24.56 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.777186 0 0 -9.324124 9.300251 85.530543 Tm +/f-0-0 1 Tf +[(Ch)57(a)4(n)-11(n)-12(e)29(l)]TJ +ET + Q +Q +0.976471 0.768627 0.6 rg +246.133 0.309 122.902 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +246.133 -0.324 122.902 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 300.010043 14.886347 Tm +/f-0-0 1 Tf +[(H)22(C)4(P)]TJ +ET + Q +Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0.486275 g +0.216789 w +2 J +0 j +[] 0.0 d +2 M q 1 0 0 -0.953661 0 0 cm +369.008 -0.324 m 448.926 -0.324 l 452.316 -0.324 455.066 -3.08 455.066 +-6.472 c 455.066 -9.867 457.824 -12.62 461.215 -12.62 c 457.824 -12.62 455.066 + -15.368 455.066 -18.756 c 455.066 -22.156 452.316 -24.904 448.926 -24.904 + c 369.008 -24.904 l S Q + Q +Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 465.229321 14.886347 Tm +/f-0-0 1 Tf +[(H)22(C)4(P)]TJ +ET + Q +Q +0.768627 0.839216 0.627451 rg +0.324 94.078 417.875 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +0.324 -98.649 417.875 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 191.832303 109.057934 Tm +/f-0-0 1 Tf +[(L)21(i)22(n)-11(k)43( )-38(D)10(a)6(t)63(a)]TJ +ET + Q +Q +0.768627 0.839216 0.627451 rg +0.324 94.078 417.875 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +0.324 -98.649 417.875 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 191.832303 109.057934 Tm +/f-0-0 1 Tf +[(L)21(i)22(n)-11(k)43( )-38(D)10(a)6(t)63(a)]TJ +ET + Q +Q +0.74902 g +246.133 23.754 122.902 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +246.133 -24.908 122.902 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 271.289829 38.438547 Tm +/f-0-0 1 Tf +[(Cl)24(e)29(a)6(r)12(te)27(x)21(t )-42(/)31( )27(S)-12(e)29(c)28(u)-13 +(r)13(i)22(ty)]TJ +ET + Q +Q +0.74902 g +246.133 23.754 122.902 23.441 re f* +0 g +0.650367 w +1 J +1 j +[] 0.0 d +10 M q 1 0 0 -0.953661 0 0 cm +246.133 -24.908 122.902 -24.58 re S Q +q +0 0 532 118 re W n +[ 1 0 0 1 0 0 ] concat + q +0 g +BT +9.798866 0 0 -9.344799 271.289829 38.438547 Tm +/f-0-0 1 Tf +[(Cl)24(e)29(a)6(r)12(te)27(x)21(t )-42(/)31( )27(S)-12(e)29(c)28(u)-13 +(r)13(i)22(ty)]TJ +ET + Q +Q +Q Q +showpage +%%Trailer +end +%%EOF diff --git a/hcp/doc/img/stack.pdf b/hcp/doc/img/stack.pdf new file mode 100644 index 0000000..29e3d6f Binary files /dev/null and b/hcp/doc/img/stack.pdf differ diff --git a/hcp/doc/img/stack.svg b/hcp/doc/img/stack.svg new file mode 100644 index 0000000..9ae1aaf --- /dev/null +++ b/hcp/doc/img/stack.svg @@ -0,0 +1,236 @@ + + + + + + + + + + + + + + Layer Structure + + + + Side brace.23 + Physical Layer + + + + + + + + + + + + + + + + + + + Physical Layer + + Side brace.24 + Link Layer + + + + + + + + + + + + + + + + + + + Link Layer + + Side brace.25 + Transport Layer + + + + + + + + + + + + + + + + + + + Transport Layer + + Side brace.26 + Application Layer + + + + + + + + + + + + + + + + + + + Application Layer + + Ark.32 + + Ark.6 + Seq Len + + + + Seq Len + + Ark.7 + Payload + + + + Payload + + Ark.30 + Seq Nr + + + + Seq Nr + + Ark.31 + Size + + + + Size + + + Ark.33 + + Ark.3 + Size + + + + Size + + Ark.4 + Payload + + + + Payload + + Ark.5 + CRC + + + + CRC + + Ark.29 + Channel + + + + Channel + + + Ark.34 + HCP + + + + HCP + + Side brace.35 + HCP + + + + + + + + + + + + + + + + + + + HCP + + Ark.37 + + Ark.2 + Link Data + + + + Link Data + + + Ark.38 + + Ark.1 + Cleartext / Security + + + + Cleartext / Security + + + diff --git a/hcp/doc/md/1_stack.md b/hcp/doc/md/1_stack.md new file mode 100644 index 0000000..212e7a8 --- /dev/null +++ b/hcp/doc/md/1_stack.md @@ -0,0 +1,49 @@ +\page stack FPC embedded stack + +The communication stack implemented on the embedded devices by FPC follows the following +specification. + +\image html stack.svg "HCP embedded stack" +\image latex stack.eps "HCP embedded stack" + +\section phy Physical + +The physical layer have a fixed size buffer of 256 bytes. + +\section link Link + +The link layer handles packet consistency. + +Each packet received is acknowledged on the link layer, if an error occurs no retransmission is +done on this level, instead the error is propagated upwards. + +Channel | Size | Payload | CRC | +------- | ------- | ---------- | ------- | +2 bytes | 2 bytes | size bytes | 4 bytes | + +All fields are using unsigned data types. + +\section tsp Transport + +The transport layer handles packet segmentation. + +As the PHY MTU is 256 bytes the maximum payload per segment is 242 bytes. + +Errors are propagated upwards. + +Size | Seq Nr | Seq Len | Payload | +------- | ------- | ------- | ---------- | +2 bytes | 2 bytes | 2 bytes | size bytes | + +All fields are using unsigned data types. + +\section app Application + +The application layer is a optional security layer, the default implementation is clear text +(unsecure). + +If a security solution is used it will be part of that products documentation. + +\section hcp HCP + +The HCP frame is described in the \link hcpf HCP frame format section. diff --git a/hcp/doc/md/2_hcpframe.md b/hcp/doc/md/2_hcpframe.md new file mode 100644 index 0000000..2e50317 --- /dev/null +++ b/hcp/doc/md/2_hcpframe.md @@ -0,0 +1,28 @@ +\page hcpf HCP frame format + +The Host Communication Protocol (HCP) describes a general way of sending commands and information +between devices. + +\image html hcp.svg "HCP frame format" +\image latex hcp.eps "HCP frame format" + +\section cmd Command + +The Commands define the general action that is going to be executed. However, each command +can have several Arguments each with data attached. + +| CMD | Num Args | Payload | +| ------- | -------- | -------- | +| 2 bytes | 2 bytes | xx bytes | + +All fields are using unsigned data types. + +\section arg Argument + +The Argument is used as a complement to the command if it is needed and can contain arbitrary data. + +| ARG | Size | Data | +| ------- | --------| ---------- | +| 2 bytes | 2 bytes | size bytes | + +All fields are using unsigned data types. diff --git a/hcp/doc/md/4_biometrics.md b/hcp/doc/md/4_biometrics.md new file mode 100644 index 0000000..6a57d7c --- /dev/null +++ b/hcp/doc/md/4_biometrics.md @@ -0,0 +1,89 @@ +\page bio Biometrics + +\section capture_b Capture + +@startuml +Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout] +... Wait for finger down... +rnote over BioMcu : fpc_bep_capture +hnote over BioMcu : image +BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result] +@enduml +*** + +\section extract_b Extract + +@startuml +group Capture +Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout] +... Wait for finger down... +rnote over BioMcu : fpc_bep_capture +hnote over BioMcu : image +BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result] +end +Host --> BioMcu: CMD_IMAGE \nARG_EXTRACT +rnote over BioMcu : fpc_bep_image_extract +hnote over BioMcu : template +BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] +@enduml +*** + +\section enroll_b Enroll + +@startuml +Host --> BioMcu: CMD_ENROLL \nARG_START +rnote over BioMcu : fpc_bep_enroll_start +hnote over BioMcu : session +BioMcu --> Host: CMD_ENROLL \nARG_RESULT[bep_result] +||| +loop Enroll Image +group Capture +Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout] +... Wait for finger down... +rnote over BioMcu : fpc_bep_capture +hnote over BioMcu : image +BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result] +end +||| +Host --> BioMcu: CMD_ENROLL \nARG_ADD +rnote over BioMcu : fpc_bep_enroll +rnote over BioMcu : count +BioMcu --> Host: CMD_ENROLL \nARG_COUNT[count] \nARG_RESULT[bep_result] +Host --> BioMcu: CMD_WAIT \nARG_FINGER_UP \nARG_TIMEOUT[timeout] +... Wait for finger up... +BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result] +end +||| +Host --> BioMcu: CMD_ENROLL \nARG_FINISH +rnote over BioMcu : fpc_bep_enroll_finish +hnote over BioMcu : enroll template +BioMcu --> Host: CMD_ENROLL \nARG_RESULT[bep_result] +@enduml +*** + +\section identify_b Identify + +@startuml +group Capture +Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout] +... Wait for finger down... +rnote over BioMcu : fpc_bep_capture +hnote over BioMcu : image +BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result] +end +||| +group Extract +Host --> BioMcu: CMD_IMAGE \nARG_EXTRACT +rnote over BioMcu : fpc_bep_image_extract +hnote over BioMcu : template +BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] +end +||| +Host --> BioMcu: CMD_IDENTIFY +rnote over BioMcu : fpc_template_storage_get_all +rnote over BioMcu : fpc_bep_identify +hnote over BioMcu : id +BioMcu --> Host: CMD_IDENTIFY \nARG_MATCH \nARG_ID[id] \nARG_RESULT[bep_result] +hnote over Host: id +@enduml +*** diff --git a/hcp/doc/md/5_image.md b/hcp/doc/md/5_image.md new file mode 100644 index 0000000..150e284 --- /dev/null +++ b/hcp/doc/md/5_image.md @@ -0,0 +1,36 @@ +\page image Image handling + +\section create_i Create + +@startuml +Host --> BioMcu: CMD_IMAGE \nARG_CREATE +hnote over BioMcu : image +BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] +@enduml +*** + +\section upload_i Upload + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : image +Host --> BioMcu: CMD_IMAGE \nARG_UPLOAD +BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] \nARG_DATA[image] +hnote over Host : image +@enduml +*** + +\section download_i Download + +@startuml +participant Host +participant BioMcu + +hnote over Host : image +Host --> BioMcu: CMD_IMAGE \nARG_DOWNLOAD \nARG_DATA[image] +hnote over BioMcu : image +BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] +@enduml +*** diff --git a/hcp/doc/md/6_template.md b/hcp/doc/md/6_template.md new file mode 100644 index 0000000..1c1adc6 --- /dev/null +++ b/hcp/doc/md/6_template.md @@ -0,0 +1,40 @@ +\page template Template handling + +\section upload_t Upload + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : template +Host --> BioMcu: CMD_TEMPLATE \nARG_UPLOAD +BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result] \nARG_DATA[template] +hnote over Host : template +@enduml +*** + +\section download_t Download + +@startuml +participant Host +participant BioMcu + +hnote over Host : template +Host --> BioMcu: CMD_TEMPLATE \nARG_DOWNLOAD \nARG_DATA[template] +hnote over BioMcu : template +BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result] +@enduml +*** + +\section save_t Save + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : template +Host --> BioMcu: CMD_TEMPLATE \nARG_SAVE \nARG_ID[id] +hnote over BioMcu : template[id] (nvm) +BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result] +@enduml +*** diff --git a/hcp/doc/md/7_storage.md b/hcp/doc/md/7_storage.md new file mode 100644 index 0000000..a86ef60 --- /dev/null +++ b/hcp/doc/md/7_storage.md @@ -0,0 +1,69 @@ +\page storage Storage handling + +\section delete_id Delete ID + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : template[id] (nvm) +Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_DELETE \nARG_ID[id] +rnote over BioMcu : fpc_template_storage_remove +BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] +@enduml +*** + +\section delete_all Delete All + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : template[] (nvm) +Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_DELETE \nARG_ALL +rnote over BioMcu : fpc_template_storage_remove_all +BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] +@enduml +*** + +\section upload_s Upload + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : template[id] (nvm) +Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_UPLOAD \nARG_ID[id] +rnote over BioMcu : fpc_template_storage_get +hnote over BioMcu : template (ram) +BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] + +@enduml +*** + +\section count_s Count + +@startuml +participant Host +participant BioMcu + +Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_COUNT +rnote over BioMcu : fpc_template_storage_get_count +BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] \nARG_COUNT[template_count] + +@enduml +*** + +\section get_id Get IDs + +@startuml +participant Host +participant BioMcu + +hnote over BioMcu : ids[] (nvm) +Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_ID +rnote over BioMcu : fpc_template_storage_get_all_ids +BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] \nARG_DATA[ids] + +@enduml +*** \ No newline at end of file diff --git a/hcp/doc/md/8_sensor.md b/hcp/doc/md/8_sensor.md new file mode 100644 index 0000000..df4627c --- /dev/null +++ b/hcp/doc/md/8_sensor.md @@ -0,0 +1,28 @@ +\page sensor Sensor operations + +\section wait_up_s Wait for finger up + +@startuml +Host --> BioMcu: CMD_WAIT \nARG_FINGER_UP \nARG_TIMEOUT[timeout] +... Wait for finger up... +BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result] +@enduml +*** + +\section wait_down_s Wait for finger down + +@startuml +Host --> BioMcu: CMD_WAIT \nARG_FINGER_DOWN \nARG_TIMEOUT[timeout] +... Wait for finger down... +BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result] +@enduml +*** + +\section sensor_reset_s Reset sensor + +@startuml +Host --> BioMcu : CMD_SENSOR \nARG_RESET +rnote over BioMcu : fpc_bep_sensor_reset +BioMcu --> Host : CMD_SENSOR \nARG_RESULT[bep_result] +@enduml +*** diff --git a/hcp/doc/md/9_device.md b/hcp/doc/md/9_device.md new file mode 100644 index 0000000..c9c6f71 --- /dev/null +++ b/hcp/doc/md/9_device.md @@ -0,0 +1,10 @@ +\page device Device operations + +\section reset_d Reset device + +@startuml +Host --> BioMcu: CMD_RESET +BioMcu --> Host: CMD_RESET \nARG_RESULT[bep_result] +rnote over BioMcu: Reset +@enduml +*** diff --git a/hcp/doxygen/HCP.html b/hcp/doxygen/HCP.html new file mode 100644 index 0000000..7449175 --- /dev/null +++ b/hcp/doxygen/HCP.html @@ -0,0 +1,13 @@ + + + + + + +

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1 \page stack FPC embedded stack
2 
3 The communication stack implemented on the embedded devices by FPC follows the following
4 specification.
5 
6 \image html stack.svg "HCP embedded stack"
7 \image latex stack.eps "HCP embedded stack"
8 
9 \section phy Physical
10 
11 The physical layer have a fixed size buffer of 256 bytes.
12 
13 \section link Link
14 
15 The link layer handles packet consistency.
16 
17 Each packet received is acknowledged on the link layer, if an error occurs no retransmission is
18 done on this level, instead the error is propagated upwards.
19 
20 Channel | Size | Payload | CRC |
21 ------- | ------- | ---------- | ------- |
22 2 bytes | 2 bytes | size bytes | 4 bytes |
23 
24 All fields are using unsigned data types.
25 
26 \section tsp Transport
27 
28 The transport layer handles packet segmentation.
29 
30 As the PHY MTU is 256 bytes the maximum payload per segment is 242 bytes.
31 
32 Errors are propagated upwards.
33 
34 Size | Seq Nr | Seq Len | Payload |
35 ------- | ------- | ------- | ---------- |
36 2 bytes | 2 bytes | 2 bytes | size bytes |
37 
38 All fields are using unsigned data types.
39 
40 \section app Application
41 
42 The application layer is a optional security layer, the default implementation is clear text
43 (unsecure).
44 
45 If a security solution is used it will be part of that products documentation.
46 
47 \section hcp HCP
48 
49 The HCP frame is described in the \link hcpf HCP frame format section.
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1 \page hcpf HCP frame format
2 
3 The Host Communication Protocol (HCP) describes a general way of sending commands and information
4 between devices.
5 
6 \image html hcp.svg "HCP frame format"
7 \image latex hcp.eps "HCP frame format"
8 
9 \section cmd Command
10 
11 The Commands define the general action that is going to be executed. However, each command
12 can have several Arguments each with data attached.
13 
14 | CMD | Num Args | Payload |
15 | ------- | -------- | -------- |
16 | 2 bytes | 2 bytes | xx bytes |
17 
18 All fields are using unsigned data types.
19 
20 \section arg Argument
21 
22 The Argument is used as a complement to the command if it is needed and can contain arbitrary data.
23 
24 | ARG | Size | Data |
25 | ------- | --------| ---------- |
26 | 2 bytes | 2 bytes | size bytes |
27 
28 All fields are using unsigned data types.
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1 \page bio Biometrics
2 
3 \section capture_b Capture
4 
5 @startuml
6 Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout]
7 ... Wait for finger down...
8 rnote over BioMcu : fpc_bep_capture
9 hnote over BioMcu : image
10 BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result]
11 @enduml
12 ***
13 
14 \section extract_b Extract
15 
16 @startuml
17 group Capture
18 Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout]
19 ... Wait for finger down...
20 rnote over BioMcu : fpc_bep_capture
21 hnote over BioMcu : image
22 BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result]
23 end
24 Host --> BioMcu: CMD_IMAGE \nARG_EXTRACT
25 rnote over BioMcu : fpc_bep_image_extract
26 hnote over BioMcu : template
27 BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result]
28 @enduml
29 ***
30 
31 \section enroll_b Enroll
32 
33 @startuml
34 Host --> BioMcu: CMD_ENROLL \nARG_START
35 rnote over BioMcu : fpc_bep_enroll_start
36 hnote over BioMcu : session
37 BioMcu --> Host: CMD_ENROLL \nARG_RESULT[bep_result]
38 |||
39 loop Enroll Image
40 group Capture
41 Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout]
42 ... Wait for finger down...
43 rnote over BioMcu : fpc_bep_capture
44 hnote over BioMcu : image
45 BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result]
46 end
47 |||
48 Host --> BioMcu: CMD_ENROLL \nARG_ADD
49 rnote over BioMcu : fpc_bep_enroll
50 rnote over BioMcu : count
51 BioMcu --> Host: CMD_ENROLL \nARG_COUNT[count] \nARG_RESULT[bep_result]
52 Host --> BioMcu: CMD_WAIT \nARG_FINGER_UP \nARG_TIMEOUT[timeout]
53 ... Wait for finger up...
54 BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result]
55 end
56 |||
57 Host --> BioMcu: CMD_ENROLL \nARG_FINISH
58 rnote over BioMcu : fpc_bep_enroll_finish
59 hnote over BioMcu : enroll template
60 BioMcu --> Host: CMD_ENROLL \nARG_RESULT[bep_result]
61 @enduml
62 ***
63 
64 \section identify_b Identify
65 
66 @startuml
67 group Capture
68 Host --> BioMcu: CMD_CAPTURE \nARG_TIMEOUT[timeout]
69 ... Wait for finger down...
70 rnote over BioMcu : fpc_bep_capture
71 hnote over BioMcu : image
72 BioMcu --> Host: CMD_CAPTURE \nARG_RESULT[bep_result]
73 end
74 |||
75 group Extract
76 Host --> BioMcu: CMD_IMAGE \nARG_EXTRACT
77 rnote over BioMcu : fpc_bep_image_extract
78 hnote over BioMcu : template
79 BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result]
80 end
81 |||
82 Host --> BioMcu: CMD_IDENTIFY
83 rnote over BioMcu : fpc_template_storage_get_all
84 rnote over BioMcu : fpc_bep_identify
85 hnote over BioMcu : id
86 BioMcu --> Host: CMD_IDENTIFY \nARG_MATCH \nARG_ID[id] \nARG_RESULT[bep_result]
87 hnote over Host: id
88 @enduml
89 ***
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1 \page image Image handling
2 
3 \section create_i Create
4 
5 @startuml
6 Host --> BioMcu: CMD_IMAGE \nARG_CREATE
7 hnote over BioMcu : image
8 BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result]
9 @enduml
10 ***
11 
12 \section upload_i Upload
13 
14 @startuml
15 participant Host
16 participant BioMcu
17 
18 hnote over BioMcu : image
19 Host --> BioMcu: CMD_IMAGE \nARG_UPLOAD
20 BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result] \nARG_DATA[image]
21 hnote over Host : image
22 @enduml
23 ***
24 
25 \section download_i Download
26 
27 @startuml
28 participant Host
29 participant BioMcu
30 
31 hnote over Host : image
32 Host --> BioMcu: CMD_IMAGE \nARG_DOWNLOAD \nARG_DATA[image]
33 hnote over BioMcu : image
34 BioMcu --> Host: CMD_IMAGE \nARG_RESULT[bep_result]
35 @enduml
36 ***
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1 \page template Template handling
2 
3 \section upload_t Upload
4 
5 @startuml
6 participant Host
7 participant BioMcu
8 
9 hnote over BioMcu : template
10 Host --> BioMcu: CMD_TEMPLATE \nARG_UPLOAD
11 BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result] \nARG_DATA[template]
12 hnote over Host : template
13 @enduml
14 ***
15 
16 \section download_t Download
17 
18 @startuml
19 participant Host
20 participant BioMcu
21 
22 hnote over Host : template
23 Host --> BioMcu: CMD_TEMPLATE \nARG_DOWNLOAD \nARG_DATA[template]
24 hnote over BioMcu : template
25 BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result]
26 @enduml
27 ***
28 
29 \section save_t Save
30 
31 @startuml
32 participant Host
33 participant BioMcu
34 
35 hnote over BioMcu : template
36 Host --> BioMcu: CMD_TEMPLATE \nARG_SAVE \nARG_ID[id]
37 hnote over BioMcu : template[id] (nvm)
38 BioMcu --> Host: CMD_TEMPLATE \nARG_RESULT[bep_result]
39 @enduml
40 ***
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1 \page storage Storage handling
2 
3 \section delete_id Delete ID
4 
5 @startuml
6 participant Host
7 participant BioMcu
8 
9 hnote over BioMcu : template[id] (nvm)
10 Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_DELETE \nARG_ID[id]
11 rnote over BioMcu : fpc_template_storage_remove
12 BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result]
13 @enduml
14 ***
15 
16 \section delete_all Delete All
17 
18 @startuml
19 participant Host
20 participant BioMcu
21 
22 hnote over BioMcu : template[] (nvm)
23 Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_DELETE \nARG_ALL
24 rnote over BioMcu : fpc_template_storage_remove_all
25 BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result]
26 @enduml
27 ***
28 
29 \section upload_s Upload
30 
31 @startuml
32 participant Host
33 participant BioMcu
34 
35 hnote over BioMcu : template[id] (nvm)
36 Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_UPLOAD \nARG_ID[id]
37 rnote over BioMcu : fpc_template_storage_get
38 hnote over BioMcu : template (ram)
39 BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result]
40 
41 @enduml
42 ***
43 
44 \section count_s Count
45 
46 @startuml
47 participant Host
48 participant BioMcu
49 
50 Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_COUNT
51 rnote over BioMcu : fpc_template_storage_get_count
52 BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] \nARG_COUNT[template_count]
53 
54 @enduml
55 ***
56 
57 \section get_id Get IDs
58 
59 @startuml
60 participant Host
61 participant BioMcu
62 
63 hnote over BioMcu : ids[] (nvm)
64 Host --> BioMcu: CMD_STORAGE_TEMPLATE \nARG_ID
65 rnote over BioMcu : fpc_template_storage_get_all_ids
66 BioMcu --> Host: CMD_STORAGE_TEMPLATE \nARG_RESULT[bep_result] \nARG_DATA[ids]
67 
68 @enduml
69 ***
+
+ + + + diff --git a/hcp/doxygen/html/8__sensor_8md.html b/hcp/doxygen/html/8__sensor_8md.html new file mode 100644 index 0000000..e284b37 --- /dev/null +++ b/hcp/doxygen/html/8__sensor_8md.html @@ -0,0 +1,86 @@ + + + + + + +Host Communication Protocol: doc/md/8_sensor.md File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
doc/md/8_sensor.md File Reference
+
+
+ +

Go to the source code of this file.

+
+
+ + + + diff --git a/hcp/doxygen/html/8__sensor_8md_source.html b/hcp/doxygen/html/8__sensor_8md_source.html new file mode 100644 index 0000000..d665b32 --- /dev/null +++ b/hcp/doxygen/html/8__sensor_8md_source.html @@ -0,0 +1,84 @@ + + + + + + +Host Communication Protocol: doc/md/8_sensor.md Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
doc/md/8_sensor.md
+
+
+Go to the documentation of this file.
1 \page sensor Sensor operations
2 
3 \section wait_up_s Wait for finger up
4 
5 @startuml
6 Host --> BioMcu: CMD_WAIT \nARG_FINGER_UP \nARG_TIMEOUT[timeout]
7 ... Wait for finger up...
8 BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result]
9 @enduml
10 ***
11 
12 \section wait_down_s Wait for finger down
13 
14 @startuml
15 Host --> BioMcu: CMD_WAIT \nARG_FINGER_DOWN \nARG_TIMEOUT[timeout]
16 ... Wait for finger down...
17 BioMcu --> Host: CMD_WAIT \nARG_RESULT[bep_result]
18 @enduml
19 ***
20 
21 \section sensor_reset_s Reset sensor
22 
23 @startuml
24 Host --> BioMcu : CMD_SENSOR \nARG_RESET
25 rnote over BioMcu : fpc_bep_sensor_reset
26 BioMcu --> Host : CMD_SENSOR \nARG_RESULT[bep_result]
27 @enduml
28 ***
+
+ + + + diff --git a/hcp/doxygen/html/9__device_8md.html b/hcp/doxygen/html/9__device_8md.html new file mode 100644 index 0000000..34a3526 --- /dev/null +++ b/hcp/doxygen/html/9__device_8md.html @@ -0,0 +1,86 @@ + + + + + + +Host Communication Protocol: doc/md/9_device.md File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
doc/md/9_device.md File Reference
+
+
+ +

Go to the source code of this file.

+
+
+ + + + diff --git a/hcp/doxygen/html/9__device_8md_source.html b/hcp/doxygen/html/9__device_8md_source.html new file mode 100644 index 0000000..ff87129 --- /dev/null +++ b/hcp/doxygen/html/9__device_8md_source.html @@ -0,0 +1,84 @@ + + + + + + +Host Communication Protocol: doc/md/9_device.md Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
doc/md/9_device.md
+
+
+Go to the documentation of this file.
1 \page device Device operations
2 
3 \section reset_d Reset device
4 
5 @startuml
6 Host --> BioMcu: CMD_RESET
7 BioMcu --> Host: CMD_RESET \nARG_RESULT[bep_result]
8 rnote over BioMcu: Reset
9 @enduml
10 ***
+
+ + + + diff --git a/hcp/doxygen/html/annotated.html b/hcp/doxygen/html/annotated.html new file mode 100644 index 0000000..2be5b26 --- /dev/null +++ b/hcp/doxygen/html/annotated.html @@ -0,0 +1,94 @@ + + + + + + +Host Communication Protocol: Data Structures + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
+ + + + + + + +
 Cfpc_com_chain
 Cfpc_com_chain_private
 Cfpc_com_packet_link
 Cfpc_com_packet_transport
 Cfpc_hcp_arg_dataCommand Argument
 Cfpc_hcp_packetApplication Command Packet
+
+
+
+ + + + diff --git a/hcp/doxygen/html/annotated_dup.js b/hcp/doxygen/html/annotated_dup.js new file mode 100644 index 0000000..d5950a0 --- /dev/null +++ b/hcp/doxygen/html/annotated_dup.js @@ -0,0 +1,9 @@ +var annotated_dup = +[ + [ "fpc_com_chain", "structfpc__com__chain.html", "structfpc__com__chain" ], + [ "fpc_com_chain_private", "structfpc__com__chain__private.html", "structfpc__com__chain__private" ], + [ "fpc_com_packet_link", "structfpc__com__packet__link.html", "structfpc__com__packet__link" ], + [ "fpc_com_packet_transport", "structfpc__com__packet__transport.html", "structfpc__com__packet__transport" ], + [ "fpc_hcp_arg_data", "structfpc__hcp__arg__data.html", "structfpc__hcp__arg__data" ], + [ "fpc_hcp_packet", "structfpc__hcp__packet.html", "structfpc__hcp__packet" ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/arrowdown.png b/hcp/doxygen/html/arrowdown.png new file mode 100644 index 0000000..0b63f6d Binary files /dev/null and b/hcp/doxygen/html/arrowdown.png differ diff --git a/hcp/doxygen/html/arrowright.png b/hcp/doxygen/html/arrowright.png new file mode 100644 index 0000000..c6ee22f Binary files /dev/null and b/hcp/doxygen/html/arrowright.png differ diff --git a/hcp/doxygen/html/bc_s.png b/hcp/doxygen/html/bc_s.png new file mode 100644 index 0000000..224b29a Binary files /dev/null and b/hcp/doxygen/html/bc_s.png differ diff --git a/hcp/doxygen/html/bdwn.png b/hcp/doxygen/html/bdwn.png new file mode 100644 index 0000000..940a0b9 Binary files /dev/null and b/hcp/doxygen/html/bdwn.png differ diff --git a/hcp/doxygen/html/bio.html b/hcp/doxygen/html/bio.html new file mode 100644 index 0000000..6cb56ad --- /dev/null +++ b/hcp/doxygen/html/bio.html @@ -0,0 +1,90 @@ + + + + + + +Host Communication Protocol: Biometrics + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + +
+
+ +
+
+
+ +
+
+
+
Biometrics
+
+
+

+Capture

+
+

+Extract

+
+

+Enroll

+
+

+Identify

+
+
+
+ + + + diff --git a/hcp/doxygen/html/classes.html b/hcp/doxygen/html/classes.html new file mode 100644 index 0000000..4f3072a --- /dev/null +++ b/hcp/doxygen/html/classes.html @@ -0,0 +1,93 @@ + + + + + + +Host Communication Protocol: Data Structure Index + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
Data Structure Index
+
+
+
F
+ + + + + +
  f  
+		fpc_com_chain_private   fpc_com_packet_transport   fpc_hcp_packet   
fpc_com_packet_link   fpc_hcp_arg_data   
fpc_com_chain   
+
F
+
+
+ + + + diff --git a/hcp/doxygen/html/closed.png b/hcp/doxygen/html/closed.png new file mode 100644 index 0000000..98cc2c9 Binary files /dev/null and b/hcp/doxygen/html/closed.png differ diff --git a/hcp/doxygen/html/device.html b/hcp/doxygen/html/device.html new file mode 100644 index 0000000..7a316ec --- /dev/null +++ b/hcp/doxygen/html/device.html @@ -0,0 +1,81 @@ + + + + + + +Host Communication Protocol: Device operations + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + +
+
+ +
+
+
+ +
+
+
+
Device operations
+
+
+

+Reset device

+
+
+
+ + + + diff --git a/hcp/doxygen/html/dir_000001_000000.html b/hcp/doxygen/html/dir_000001_000000.html new file mode 100644 index 0000000..cf9d79f --- /dev/null +++ b/hcp/doxygen/html/dir_000001_000000.html @@ -0,0 +1,74 @@ + + + + + + +Host Communication Protocol: src -> inc Relation + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + +
+
+ +
+
+
+ +
+
+

src → inc Relation

File in srcIncludes file in inc
fpc_com_link.cfpc_com_link.h
fpc_com_transport.cfpc_com_link.h
fpc_com_transport.cfpc_com_transport.h
fpc_hcp.cfpc_hcp.h
+
+ + + + diff --git a/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.html b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.html new file mode 100644 index 0000000..0ad6e8b --- /dev/null +++ b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.html @@ -0,0 +1,103 @@ + + + + + + +Host Communication Protocol: src Directory Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
src Directory Reference
+
+
+
+Directory dependency graph for src:
+
+
+
+
+ + + + + + + + + + + +

+Files

file  fpc_com_link.c [code]
 Communication link layer implementation.
 
file  fpc_com_transport.c [code]
 Communication transport layer implementation.
 
file  fpc_hcp.c [code]
 Host Communication Protocol implementation.
 
+
+
+ + + + diff --git a/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.js b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.js new file mode 100644 index 0000000..a4b8e35 --- /dev/null +++ b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba.js @@ -0,0 +1,6 @@ +var dir_68267d1309a1af8e8297ef4c3efbcdba = +[ + [ "fpc_com_link.c", "fpc__com__link_8c.html", "fpc__com__link_8c" ], + [ "fpc_com_transport.c", "fpc__com__transport_8c.html", "fpc__com__transport_8c" ], + [ "fpc_hcp.c", "fpc__hcp_8c.html", "fpc__hcp_8c" ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.map b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.map new file mode 100644 index 0000000..75b1903 --- /dev/null +++ b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.map @@ -0,0 +1,5 @@ + + + + + diff --git a/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.md5 b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.md5 new file mode 100644 index 0000000..76e9230 --- /dev/null +++ b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.md5 @@ -0,0 +1 @@ +078edd713872194e35fdc26e1b4695d3 \ No newline at end of file diff --git a/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.svg b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.svg new file mode 100644 index 0000000..c0f984a --- /dev/null +++ b/hcp/doxygen/html/dir_68267d1309a1af8e8297ef4c3efbcdba_dep.svg @@ -0,0 +1,38 @@ + + + + + + +src + + +dir_68267d1309a1af8e8297ef4c3efbcdba + + +src + + + + +dir_bfccd401955b95cf8c75461437045ac0 + + +inc + + + + +dir_68267d1309a1af8e8297ef4c3efbcdba->dir_bfccd401955b95cf8c75461437045ac0 + + + +4 + + + + + diff --git a/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.html b/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.html new file mode 100644 index 0000000..3347207 --- /dev/null +++ b/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.html @@ -0,0 +1,109 @@ + + + + + + +Host Communication Protocol: inc Directory Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
inc Directory Reference
+
+
+ + + + + + + + + + + + + + + + + + + + + + + +

+Files

file  fpc_com_chain.h [code]
 Communication chain type definitions.
 
file  fpc_com_link.h [code]
 Communication link interface.
 
file  fpc_com_packets.h [code]
 Communication packet type definitions.
 
file  fpc_com_result.h [code]
 Communication result type definitions.
 
file  fpc_com_transport.h [code]
 Communication transport interface.
 
file  fpc_hcp.h [code]
 Host Communication Protocol interface.
 
file  fpc_hcp_common.h [code]
 Host Communication Protocol common type definitions.
 
+
+
+ + + + diff --git a/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.js b/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.js new file mode 100644 index 0000000..1177085 --- /dev/null +++ b/hcp/doxygen/html/dir_bfccd401955b95cf8c75461437045ac0.js @@ -0,0 +1,10 @@ +var dir_bfccd401955b95cf8c75461437045ac0 = +[ + [ "fpc_com_chain.h", "fpc__com__chain_8h.html", "fpc__com__chain_8h" ], + [ "fpc_com_link.h", "fpc__com__link_8h.html", "fpc__com__link_8h" ], + [ "fpc_com_packets.h", "fpc__com__packets_8h.html", "fpc__com__packets_8h" ], + [ "fpc_com_result.h", "fpc__com__result_8h.html", "fpc__com__result_8h" ], + [ "fpc_com_transport.h", "fpc__com__transport_8h.html", "fpc__com__transport_8h" ], + [ "fpc_hcp.h", "fpc__hcp_8h.html", "fpc__hcp_8h" ], + [ "fpc_hcp_common.h", "fpc__hcp__common_8h.html", "fpc__hcp__common_8h" ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/doc.png b/hcp/doxygen/html/doc.png new file mode 100644 index 0000000..17edabf Binary files /dev/null and b/hcp/doxygen/html/doc.png differ diff --git a/hcp/doxygen/html/doxygen.css b/hcp/doxygen/html/doxygen.css new file mode 100644 index 0000000..1425ec5 --- /dev/null +++ b/hcp/doxygen/html/doxygen.css @@ -0,0 +1,1475 @@ +/* The standard CSS for doxygen 1.8.11 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #879ECB; + color: #354C7B; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +p.starttd { + margin-top: 0px; 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+ -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line:after { + content:"\000A"; + white-space: pre; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah, span.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000 110%); +} + +div.classindex ul { + list-style: none; + padding-left: 0; +} + +div.classindex span.ai { + display: inline-block; +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C4CFE5; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C4CFE5; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EEF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9CAFD4; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4A6AAA; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4665A2; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4665A2; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A3B4D7; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 0px 6px 0px; + color: #253555; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A8B8D9; + border-left: 1px solid #A8B8D9; + border-right: 1px solid #A8B8D9; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #728DC1; + border-top:1px solid #5373B4; + border-left:1px solid #5373B4; + border-right:1px solid #C4CFE5; + border-bottom:1px solid #C4CFE5; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view inside a (index) page */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #9CAFD4; + border-bottom: 1px solid #9CAFD4; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3D578C; +} + +.arrow { + color: #9CAFD4; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; + cursor: pointer; + font-size: 80%; + display: inline-block; + width: 16px; + height: 22px; +} + +.icon { + font-family: Arial, Helvetica; + font-weight: bold; + font-size: 12px; + height: 14px; + width: 16px; + display: inline-block; + background-color: #728DC1; + color: white; + text-align: center; + border-radius: 4px; + margin-left: 2px; + margin-right: 2px; +} + +.icona { + width: 24px; + height: 22px; + display: inline-block; +} + +.iconfopen { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderopen.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.iconfclosed { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('folderclosed.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +.icondoc { + width: 24px; + height: 18px; + margin-bottom: 4px; + background-image:url('doc.png'); + background-position: 0px -4px; + background-repeat: repeat-y; + vertical-align:top; + display: inline-block; +} + +table.directory { + font: 400 14px Roboto,sans-serif; +} + +/* @end */ + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #2A3D61; +} + +table.doxtable caption { + caption-side: top; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #374F7F; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A8B8D9; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A8B8D9; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E8F2; + font-size: 90%; + color: #253555; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A8B8D9; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#8AA0CC; + border:solid 1px #C2CDE4; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#364D7C; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #283A5D; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6884BD; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#364D7C; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +table.classindex +{ + margin: 10px; + white-space: nowrap; + margin-left: 3%; + margin-right: 3%; + width: 94%; + border: 0; + border-spacing: 0; + padding: 0; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C4CFE5; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectalign +{ + vertical-align: middle; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5373B4; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #90A5CE; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#334975; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D8DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 8px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4665A2; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.s:after, #powerTip.s:before, +#powerTip.w:after, #powerTip.w:before, +#powerTip.e:after, #powerTip.e:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.nw:after, #powerTip.nw:before, +#powerTip.sw:after, #powerTip.sw:before { + border: solid transparent; + content: " "; + height: 0; + width: 0; + position: absolute; +} + +#powerTip.n:after, #powerTip.s:after, +#powerTip.w:after, #powerTip.e:after, +#powerTip.nw:after, #powerTip.ne:after, +#powerTip.sw:after, #powerTip.se:after { + border-color: rgba(255, 255, 255, 0); +} + +#powerTip.n:before, #powerTip.s:before, +#powerTip.w:before, #powerTip.e:before, +#powerTip.nw:before, #powerTip.ne:before, +#powerTip.sw:before, #powerTip.se:before { + border-color: rgba(128, 128, 128, 0); +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.nw:after, #powerTip.nw:before { + top: 100%; +} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/hcp/doxygen/html/doxygen.png b/hcp/doxygen/html/doxygen.png new file mode 100644 index 0000000..3ff17d8 Binary files /dev/null and b/hcp/doxygen/html/doxygen.png differ diff --git a/hcp/doxygen/html/dynsections.js b/hcp/doxygen/html/dynsections.js new file mode 100644 index 0000000..1e6bf07 --- /dev/null +++ b/hcp/doxygen/html/dynsections.js @@ -0,0 +1,104 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} + +function toggleLevel(level) +{ + $('table.directory tr').each(function() { + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + + +Host Communication Protocol: File List + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
File List
+
+
+
Here is a list of all files with brief descriptions:
+
[detail level 12]
+ + + + + + + + + + + + +
 ▼ inc
 fpc_com_chain.hCommunication chain type definitions
 fpc_com_link.hCommunication link interface
 fpc_com_packets.hCommunication packet type definitions
 fpc_com_result.hCommunication result type definitions
 fpc_com_transport.hCommunication transport interface
 fpc_hcp.hHost Communication Protocol interface
 fpc_hcp_common.hHost Communication Protocol common type definitions
 ▼ src
 fpc_com_link.cCommunication link layer implementation
 fpc_com_transport.cCommunication transport layer implementation
 fpc_hcp.cHost Communication Protocol implementation
+
+
+
+ + + + diff --git a/hcp/doxygen/html/files.js b/hcp/doxygen/html/files.js new file mode 100644 index 0000000..0a216ca --- /dev/null +++ b/hcp/doxygen/html/files.js @@ -0,0 +1,5 @@ +var files = +[ + [ "inc", "dir_bfccd401955b95cf8c75461437045ac0.html", "dir_bfccd401955b95cf8c75461437045ac0" ], + [ "src", "dir_68267d1309a1af8e8297ef4c3efbcdba.html", "dir_68267d1309a1af8e8297ef4c3efbcdba" ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/folderclosed.png b/hcp/doxygen/html/folderclosed.png new file mode 100644 index 0000000..bb8ab35 Binary files /dev/null and b/hcp/doxygen/html/folderclosed.png differ diff --git a/hcp/doxygen/html/folderopen.png b/hcp/doxygen/html/folderopen.png new file mode 100644 index 0000000..d6c7f67 Binary files /dev/null and b/hcp/doxygen/html/folderopen.png differ diff --git a/hcp/doxygen/html/fpc__com__chain_8h.html b/hcp/doxygen/html/fpc__com__chain_8h.html new file mode 100644 index 0000000..c91c9e8 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h.html @@ -0,0 +1,197 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_chain.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Structures | +Typedefs | +Enumerations
+
+
fpc_com_chain.h File Reference
+
+
+ +

Communication chain type definitions. +More...

+
#include <stdint.h>
+#include "fpc_com_result.h"
+#include "fpc_hcp_common.h"
+#include "fpc_com_packets.h"
+
+Include dependency graph for fpc_com_chain.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + +

+Data Structures

struct  fpc_com_chain_private
 
struct  fpc_com_chain
 
+ + + + + + + +

+Typedefs

typedef struct fpc_com_chain_private fpc_com_chain_private_t
 Communication chain private variables. More...
 
typedef struct fpc_com_chain fpc_com_chain_t
 Communication chain. More...
 
+ + + + +

+Enumerations

enum  fpc_com_chain_dir_t {
+  FPC_COM_CHAIN_TX = 0, +
+  FPC_COM_CHAIN_RX = 1 +
+ }
 Communication chain direction type. More...
 
+

Detailed Description

+

Communication chain type definitions.

+ +

Definition in file fpc_com_chain.h.

+

Typedef Documentation

+ +
+
+ + + + +
typedef struct fpc_com_chain_private fpc_com_chain_private_t
+
+ +

Communication chain private variables.

+ +

Definition at line 34 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
typedef struct fpc_com_chain fpc_com_chain_t
+
+ +

Communication chain.

+ +

Definition at line 48 of file fpc_com_chain.h.

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum fpc_com_chain_dir_t
+
+ +

Communication chain direction type.

+ + + +
Enumerator
FPC_COM_CHAIN_TX  +
FPC_COM_CHAIN_RX  +
+ +

Definition at line 149 of file fpc_com_chain.h.

+ +
+
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__chain_8h.js b/hcp/doxygen/html/fpc__com__chain_8h.js new file mode 100644 index 0000000..a70f492 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h.js @@ -0,0 +1,11 @@ +var fpc__com__chain_8h = +[ + [ "fpc_com_chain_private", "structfpc__com__chain__private.html", "structfpc__com__chain__private" ], + [ "fpc_com_chain", "structfpc__com__chain.html", "structfpc__com__chain" ], + [ "fpc_com_chain_private_t", "fpc__com__chain_8h.html#a0983b70df0d560f35537acc24ecc0d0d", null ], + [ "fpc_com_chain_t", "fpc__com__chain_8h.html#a1530dd4e8729e5f546a96abc5ac0a6de", null ], + [ "fpc_com_chain_dir_t", "fpc__com__chain_8h.html#aed3b93f1297ab69d5bd87603d4d00005", [ + [ "FPC_COM_CHAIN_TX", "fpc__com__chain_8h.html#aed3b93f1297ab69d5bd87603d4d00005afe8870bc644ab21ffad73d3045febd4d", null ], + [ "FPC_COM_CHAIN_RX", "fpc__com__chain_8h.html#aed3b93f1297ab69d5bd87603d4d00005aa50bc934637a1ceea907810ccdd36e1c", null ] + ] ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.map b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.map new file mode 100644 index 0000000..41888bd --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.md5 b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.md5 new file mode 100644 index 0000000..fb067aa --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.md5 @@ -0,0 +1 @@ +1da3230b9ede79419647e0f9db2fcf4a \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.svg b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.svg new file mode 100644 index 0000000..72cca7f --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__dep__incl.svg @@ -0,0 +1,101 @@ + + + + + + +inc/fpc_com_chain.h + + +Node1 + +inc/fpc_com_chain.h + + +Node2 + + +inc/fpc_com_link.h + + + + +Node1->Node2 + + + + +Node5 + + +inc/fpc_com_transport.h + + + + +Node1->Node5 + + + + +Node6 + + +inc/fpc_hcp.h + + + + +Node1->Node6 + + + + +Node3 + + +src/fpc_com_link.c + + + + +Node2->Node3 + + + + +Node4 + + +src/fpc_com_transport.c + + + + +Node2->Node4 + + + + +Node5->Node4 + + + + +Node7 + + +src/fpc_hcp.c + + + + +Node6->Node7 + + + + + diff --git a/hcp/doxygen/html/fpc__com__chain_8h__incl.map b/hcp/doxygen/html/fpc__com__chain_8h__incl.map new file mode 100644 index 0000000..65def15 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__incl.map @@ -0,0 +1,5 @@ + + + + + diff --git a/hcp/doxygen/html/fpc__com__chain_8h__incl.md5 b/hcp/doxygen/html/fpc__com__chain_8h__incl.md5 new file mode 100644 index 0000000..6475780 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__incl.md5 @@ -0,0 +1 @@ +f3463291a698aa7de197e31a9e7ef155 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__chain_8h__incl.svg b/hcp/doxygen/html/fpc__com__chain_8h__incl.svg new file mode 100644 index 0000000..77c3842 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h__incl.svg @@ -0,0 +1,92 @@ + + + + + + +inc/fpc_com_chain.h + + +Node1 + +inc/fpc_com_chain.h + + +Node2 + +stdint.h + + +Node1->Node2 + + + + +Node3 + + +fpc_com_result.h + + + + +Node1->Node3 + + + + +Node4 + + +fpc_hcp_common.h + + + + +Node1->Node4 + + + + +Node6 + + +fpc_com_packets.h + + + + +Node1->Node6 + + + + +Node3->Node2 + + + + +Node4->Node2 + + + + +Node5 + +stdbool.h + + +Node4->Node5 + + + + +Node6->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__chain_8h_source.html b/hcp/doxygen/html/fpc__com__chain_8h_source.html new file mode 100644 index 0000000..77f33e3 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__chain_8h_source.html @@ -0,0 +1,109 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_chain.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_chain.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_COM_CHAIN_H
23 #define FPC_COM_CHAIN_H
24 
25 #include <stdint.h>
26 
27 #include "fpc_com_result.h"
28 #include "fpc_hcp_common.h"
29 #include "fpc_com_packets.h"
30 
34 typedef struct fpc_com_chain_private fpc_com_chain_private_t;
36 struct fpc_com_chain_private {
38  fpc_hcp_packet_t *hcp_packet;
40  uint16_t hcp_seq_len;
42  uint16_t hcp_seq_nr;
43 };
44 
48 typedef struct fpc_com_chain fpc_com_chain_t;
50 struct fpc_com_chain {
52  bool initialized;
53 
59  void *(*argument_allocator)(fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size,
60  bool *free_data, void *context);
62  void (*argument_free)(fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, void *context);
66  uint32_t (*crc_calc)(uint32_t start, const void *data, uint32_t size);
67 
73  fpc_com_result_t (*app_tx)(fpc_com_chain_t *chain);
75  fpc_com_result_t (*app_rx)(fpc_com_chain_t *chain);
77  uint16_t (*app_overhead_get)(uint16_t *offset);
79  uint16_t app_packet_size[2];
81  uint16_t app_mtu_size[2];
83  uint8_t *app_mtu_buffer[2];
91  fpc_com_result_t (*tsp_tx)(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain);
93  fpc_com_result_t (*tsp_rx)(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain);
95  uint16_t (*tsp_overhead_get)(uint16_t *offset);
103  uint16_t (*link_overhead_get)(uint16_t *offset);
105  fpc_com_channel_t channel;
113  fpc_com_result_t (*phy_tx)(uint16_t size, const uint8_t *buffer, uint32_t timeout,
114  void *session);
116  fpc_com_result_t (*phy_rx)(uint16_t size, uint8_t *buffer, uint32_t timeout,
117  void *session);
119  uint16_t phy_mtu_size[2];
121  uint8_t *phy_mtu_buffer[2];
123  uint32_t phy_timeout_tx;
125  uint32_t phy_timeout_rx;
129  fpc_com_chain_private_t private_vars;
130 
137  void *session;
143  void *context;
144 };
145 
149 typedef enum {
150  FPC_COM_CHAIN_TX = 0,
151  FPC_COM_CHAIN_RX = 1,
152 } fpc_com_chain_dir_t;
153 
154 #endif /* FPC_COM_CHAIN_H */
fpc_hcp_cmd_t
uint16_t fpc_hcp_cmd_t
Definition: fpc_hcp_common.h:92
+
fpc_com_chain_private::hcp_seq_len
uint16_t hcp_seq_len
Definition: fpc_com_chain.h:40
+
fpc_com_chain
Definition: fpc_com_chain.h:50
+
fpc_com_result.h
Communication result type definitions.
+
FPC_COM_CHAIN_TX
Definition: fpc_com_chain.h:150
+
fpc_hcp_packet
Application Command Packet.
Definition: fpc_hcp_common.h:210
+
fpc_com_chain::phy_timeout_tx
uint32_t phy_timeout_tx
Definition: fpc_com_chain.h:123
+
fpc_com_chain_dir_t
fpc_com_chain_dir_t
Communication chain direction type.
Definition: fpc_com_chain.h:149
+
fpc_com_chain::session
void * session
User session pointer. User private stuff, to be able to pass necessary info from the layer that calls...
Definition: fpc_com_chain.h:137
+
fpc_com_packet_transport
Definition: fpc_com_packets.h:37
+
fpc_com_chain::context
void * context
User context pointer. User private stuff, to be able to pass nessecary context to argument_allocator ...
Definition: fpc_com_chain.h:143
+
fpc_com_chain::channel
fpc_com_channel_t channel
Definition: fpc_com_chain.h:105
+
fpc_hcp_arg_data
Command Argument.
Definition: fpc_hcp_common.h:196
+
fpc_com_chain::initialized
bool initialized
Definition: fpc_com_chain.h:52
+
fpc_com_chain::phy_timeout_rx
uint32_t phy_timeout_rx
Definition: fpc_com_chain.h:125
+
FPC_COM_CHAIN_RX
Definition: fpc_com_chain.h:151
+
fpc_hcp_arg_t
uint16_t fpc_hcp_arg_t
Definition: fpc_hcp_common.h:191
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_chain_private::hcp_packet
fpc_hcp_packet_t * hcp_packet
Definition: fpc_com_chain.h:38
+
fpc_com_chain::private_vars
fpc_com_chain_private_t private_vars
Definition: fpc_com_chain.h:129
+
fpc_com_channel_t
uint16_t fpc_com_channel_t
Definition: fpc_com_packets.h:58
+
fpc_com_chain_private
Definition: fpc_com_chain.h:36
+
fpc_hcp_common.h
Host Communication Protocol common type definitions.
+
fpc_com_packets.h
Communication packet type definitions.
+
fpc_com_chain_private::hcp_seq_nr
uint16_t hcp_seq_nr
Definition: fpc_com_chain.h:42
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c.html b/hcp/doxygen/html/fpc__com__link_8c.html new file mode 100644 index 0000000..a39bf0b --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c.html @@ -0,0 +1,235 @@ + + + + + + +Host Communication Protocol: src/fpc_com_link.c File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Functions
+
+
fpc_com_link.c File Reference
+
+
+ +

Communication link layer implementation. +More...

+
#include <string.h>
+#include <stdlib.h>
+#include "fpc_com_link.h"
+
+Include dependency graph for fpc_com_link.c:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Functions

fpc_com_result_t fpc_com_link_transmit (fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
 Sends a packet over the physical link in blocking mode. More...
 
fpc_com_result_t fpc_com_link_receive (fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
 Receives a packet from the physical link. More...
 
uint16_t fpc_com_link_get_overhead (uint16_t *offset)
 Returns the overhead of the layer. More...
 
+

Detailed Description

+

Communication link layer implementation.

+ +

Definition in file fpc_com_link.c.

+

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t fpc_com_link_get_overhead (uint16_t * offset)
+
+ +

Returns the overhead of the layer.

+
Parameters
+ + +
[out]offsetThe offset to the packet data.
+
+
+
Returns
Overhead size in bytes.
+ +

Definition at line 126 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, and fpc_com_packet_link::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_link_receive (fpc_com_packet_link_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receives a packet from the physical link.

+
Parameters
+ + + +
[in,out]packetPacket to populate.
[in]chainThe communication chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 73 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, fpc_com_chain::crc_calc, fpc_com_packet_link::data, FPC_COM_ACK, FPC_COM_CHAIN_RX, FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_IO_ERROR, FPC_COM_RESULT_OK, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::phy_rx, fpc_com_chain::phy_timeout_rx, fpc_com_chain::phy_timeout_tx, fpc_com_chain::phy_tx, fpc_com_chain::session, and fpc_com_packet_link::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_link_transmit (fpc_com_packet_link_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Sends a packet over the physical link in blocking mode.

+
Parameters
+ + + +
[in]packetPacket to transmit.
[in]chainThe communication chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 27 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, fpc_com_chain::crc_calc, fpc_com_packet_link::data, FPC_COM_ACK, FPC_COM_CHAIN_TX, fpc_com_link_get_overhead(), FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_IO_ERROR, FPC_COM_RESULT_OK, FPC_COM_RESULT_TIMEOUT, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_rx, fpc_com_chain::phy_timeout_rx, fpc_com_chain::phy_timeout_tx, fpc_com_chain::phy_tx, fpc_com_chain::session, and fpc_com_packet_link::size.

+ +

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+ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c.js b/hcp/doxygen/html/fpc__com__link_8c.js new file mode 100644 index 0000000..7a7d60f --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c.js @@ -0,0 +1,6 @@ +var fpc__com__link_8c = +[ + [ "fpc_com_link_get_overhead", "fpc__com__link_8c.html#a3e60e21a5ac4ad4881e4929de2f3c2f4", null ], + [ "fpc_com_link_receive", "fpc__com__link_8c.html#ae64b80cd91fbfe44abc06dc52eacf739", null ], + [ "fpc_com_link_transmit", "fpc__com__link_8c.html#a43a8a308255ea41e7b7cdefd63a90d14", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8c__incl.map b/hcp/doxygen/html/fpc__com__link_8c__incl.map new file mode 100644 index 0000000..f80ec9e --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c__incl.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c__incl.md5 b/hcp/doxygen/html/fpc__com__link_8c__incl.md5 new file mode 100644 index 0000000..372b027 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c__incl.md5 @@ -0,0 +1 @@ +5ae4569dea06540c6706ee9e9b27db36 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8c__incl.svg b/hcp/doxygen/html/fpc__com__link_8c__incl.svg new file mode 100644 index 0000000..26e6a9f --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c__incl.svg @@ -0,0 +1,153 @@ + + + + + + +src/fpc_com_link.c + + +Node1 + +src/fpc_com_link.c + + +Node2 + +string.h + + +Node1->Node2 + + + + +Node3 + +stdlib.h + + +Node1->Node3 + + + + +Node4 + + +fpc_com_link.h + + + + +Node1->Node4 + + + + +Node5 + +stdbool.h + + +Node4->Node5 + + + + +Node6 + +stdint.h + + +Node4->Node6 + + + + +Node7 + + +fpc_com_result.h + + + + +Node4->Node7 + + + + +Node8 + + +fpc_com_chain.h + + + + +Node4->Node8 + + + + +Node7->Node6 + + + + +Node8->Node6 + + + + +Node8->Node7 + + + + +Node9 + + +fpc_hcp_common.h + + + + +Node8->Node9 + + + + +Node10 + + +fpc_com_packets.h + + + + +Node8->Node10 + + + + +Node9->Node5 + + + + +Node9->Node6 + + + + +Node10->Node6 + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map new file mode 100644 index 0000000..621ae0a --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 new file mode 100644 index 0000000..7012d06 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 @@ -0,0 +1 @@ +1079db44f9fcfecbed78b0a2bbb98b54 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg new file mode 100644 index 0000000..1fce018 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg @@ -0,0 +1,31 @@ + + + + + + +fpc_com_link_transmit + + +Node1 + +fpc_com_link_transmit + + +Node2 + + +fpc_com_link_get_overhead + + + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8c_source.html b/hcp/doxygen/html/fpc__com__link_8c_source.html new file mode 100644 index 0000000..49f5ee4 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8c_source.html @@ -0,0 +1,111 @@ + + + + + + +Host Communication Protocol: src/fpc_com_link.c Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_link.c
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #include <string.h>
23 #include <stdlib.h>
24 
25 #include "fpc_com_link.h"
26 
27 fpc_com_result_t fpc_com_link_transmit(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
28 {
29  uint32_t ack;
30  uint16_t size;
31  fpc_com_result_t result;
32 
33  if (packet == NULL) {
34  result = FPC_COM_RESULT_INVALID_ARGUMENT;
35  goto exit;
36  }
37 
38  /* Calculate CRC for payload */
39  packet->crc = chain->crc_calc(0, packet->data, packet->size);
40 
41  /* Get total size to be transfered over PHY layer */
42  size = packet->size + fpc_com_link_get_overhead(NULL);
43 
44  *((fpc_com_channel_t *)chain->phy_mtu_buffer[FPC_COM_CHAIN_TX]) = packet->channel;
45  *((uint16_t *)(chain->phy_mtu_buffer[FPC_COM_CHAIN_TX] + sizeof(packet->channel)))
46  = packet->size;
47  /* Copy CRC to PHY mtu buffer */
48  memcpy(packet->data + packet->size, &packet->crc, sizeof(packet->crc));
49 
50  /* Send Packet */
51  result = chain->phy_tx(size, chain->phy_mtu_buffer[FPC_COM_CHAIN_TX], chain->phy_timeout_tx,
52  chain->session);
53  if (result != FPC_COM_RESULT_OK) {
54  goto exit;
55  }
56 
57  /* Receive ACK */
58  result = chain->phy_rx(sizeof(ack), (uint8_t *)&ack, chain->phy_timeout_rx, chain->session);
59  /* Handle no ack and timeout as IO error */
60  if (ack != FPC_COM_ACK || result == FPC_COM_RESULT_TIMEOUT) {
61  result = FPC_COM_RESULT_IO_ERROR;
62  goto exit;
63  }
64  /* Handle rest as normal error */
65  if (result != FPC_COM_RESULT_OK) {
66  goto exit;
67  }
68 
69 exit:
70  return result;
71 }
72 
73 fpc_com_result_t fpc_com_link_receive(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
74 {
75  bool status;
76  uint32_t ack = FPC_COM_ACK;
77  const uint8_t header_size = sizeof(packet->channel) + sizeof(packet->size);
78  fpc_com_result_t result;
79 
80  if (packet == NULL) {
81  result = FPC_COM_RESULT_INVALID_ARGUMENT;
82  goto exit;
83  }
84 
85  /* Receive Header */
86  result = chain->phy_rx(header_size, chain->phy_mtu_buffer[FPC_COM_CHAIN_RX],
87  chain->phy_timeout_rx, chain->session);
88  if (result != FPC_COM_RESULT_OK) {
89  goto exit;
90  }
91 
92  packet->channel = *((fpc_com_channel_t *)chain->phy_mtu_buffer[FPC_COM_CHAIN_RX]);
93  packet->size = *((uint16_t *) (chain->phy_mtu_buffer[FPC_COM_CHAIN_RX]
94  + sizeof(fpc_com_channel_t)));
95  packet->data = chain->phy_mtu_buffer[FPC_COM_CHAIN_RX] + header_size;
96 
97  /* Check if packet size is valid */
98  if (chain->phy_mtu_size[FPC_COM_CHAIN_RX]
99  < (header_size + packet->size + sizeof(packet->crc))) {
100  result = FPC_COM_RESULT_IO_ERROR;
101  goto exit;
102  }
103 
104  /* Receive Payload */
105  result = chain->phy_rx(packet->size + sizeof(packet->crc), packet->data,
106  chain->phy_timeout_rx, chain->session);
107  if (result != FPC_COM_RESULT_OK) {
108  goto exit;
109  }
110 
111  /* Check incoming packet CRC */
112  memcpy(&packet->crc, packet->data + packet->size, sizeof(packet->crc));
113  status = (packet->crc == chain->crc_calc(0, packet->data, packet->size));
114  if (!status) {
115  result = FPC_COM_RESULT_IO_ERROR;
116  goto exit;
117  }
118 
119  /* Send ACK */
120  result = chain->phy_tx(sizeof(ack), (uint8_t *)&ack, chain->phy_timeout_tx, chain->session);
121 
122 exit:
123  return result;
124 }
125 
126 uint16_t fpc_com_link_get_overhead(uint16_t *offset)
127 {
128  fpc_com_packet_link_t *packet;
129  static const uint16_t internal_offset = sizeof(packet->channel) + sizeof(packet->size);
130 
131  if (offset) {
132  *offset = internal_offset;
133  }
134  return internal_offset + sizeof(packet->crc);
135 }
fpc_com_link_transmit
fpc_com_result_t fpc_com_link_transmit(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Sends a packet over the physical link in blocking mode.
Definition: fpc_com_link.c:27
+
FPC_COM_RESULT_IO_ERROR
Definition: fpc_com_result.h:37
+
fpc_com_chain::phy_mtu_buffer
uint8_t * phy_mtu_buffer[2]
Definition: fpc_com_chain.h:121
+
fpc_com_chain::phy_mtu_size
uint16_t phy_mtu_size[2]
Definition: fpc_com_chain.h:119
+
fpc_com_chain
Definition: fpc_com_chain.h:50
+
FPC_COM_CHAIN_TX
Definition: fpc_com_chain.h:150
+
fpc_com_chain::phy_rx
fpc_com_result_t(* phy_rx)(uint16_t size, uint8_t *buffer, uint32_t timeout, void *session)
Definition: fpc_com_chain.h:116
+
fpc_com_chain::phy_timeout_tx
uint32_t phy_timeout_tx
Definition: fpc_com_chain.h:123
+
FPC_COM_RESULT_TIMEOUT
Definition: fpc_com_result.h:38
+
fpc_com_chain::session
void * session
User session pointer. User private stuff, to be able to pass necessary info from the layer that calls...
Definition: fpc_com_chain.h:137
+
fpc_com_packet_link::size
uint16_t size
Definition: fpc_com_packets.h:65
+
FPC_COM_RESULT_INVALID_ARGUMENT
Definition: fpc_com_result.h:35
+
fpc_com_packet_link::data
uint8_t * data
Definition: fpc_com_packets.h:67
+
fpc_com_chain::crc_calc
uint32_t(* crc_calc)(uint32_t start, const void *data, uint32_t size)
Definition: fpc_com_chain.h:66
+
FPC_COM_ACK
#define FPC_COM_ACK
Definition: fpc_com_packets.h:32
+
fpc_com_link_get_overhead
uint16_t fpc_com_link_get_overhead(uint16_t *offset)
Returns the overhead of the layer.
Definition: fpc_com_link.c:126
+
fpc_com_chain::phy_tx
fpc_com_result_t(* phy_tx)(uint16_t size, const uint8_t *buffer, uint32_t timeout, void *session)
Definition: fpc_com_chain.h:113
+
fpc_com_chain::phy_timeout_rx
uint32_t phy_timeout_rx
Definition: fpc_com_chain.h:125
+
FPC_COM_CHAIN_RX
Definition: fpc_com_chain.h:151
+
fpc_com_packet_link::channel
fpc_com_channel_t channel
Definition: fpc_com_packets.h:63
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_packet_link::crc
uint32_t crc
Definition: fpc_com_packets.h:69
+
fpc_com_channel_t
uint16_t fpc_com_channel_t
Definition: fpc_com_packets.h:58
+
fpc_com_link.h
Communication link interface.
+
fpc_com_link_receive
fpc_com_result_t fpc_com_link_receive(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Receives a packet from the physical link.
Definition: fpc_com_link.c:73
+
FPC_COM_RESULT_OK
Definition: fpc_com_result.h:33
+
fpc_com_packet_link
Definition: fpc_com_packets.h:61
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h.html b/hcp/doxygen/html/fpc__com__link_8h.html new file mode 100644 index 0000000..5340057 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h.html @@ -0,0 +1,242 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_link.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Functions
+
+
fpc_com_link.h File Reference
+
+
+ +

Communication link interface. +More...

+
#include <stdbool.h>
+#include <stdint.h>
+#include "fpc_com_result.h"
+#include "fpc_com_chain.h"
+
+Include dependency graph for fpc_com_link.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
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+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Functions

fpc_com_result_t fpc_com_link_transmit (fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
 Sends a packet over the physical link in blocking mode. More...
 
fpc_com_result_t fpc_com_link_receive (fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
 Receives a packet from the physical link. More...
 
uint16_t fpc_com_link_get_overhead (uint16_t *offset)
 Returns the overhead of the layer. More...
 
+

Detailed Description

+

Communication link interface.

+ +

Definition in file fpc_com_link.h.

+

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t fpc_com_link_get_overhead (uint16_t * offset)
+
+ +

Returns the overhead of the layer.

+
Parameters
+ + +
[out]offsetThe offset to the packet data.
+
+
+
Returns
Overhead size in bytes.
+ +

Definition at line 126 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, and fpc_com_packet_link::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_link_receive (fpc_com_packet_link_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receives a packet from the physical link.

+
Parameters
+ + + +
[in,out]packetPacket to populate.
[in]chainThe communication chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 73 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, fpc_com_chain::crc_calc, fpc_com_packet_link::data, FPC_COM_ACK, FPC_COM_CHAIN_RX, FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_IO_ERROR, FPC_COM_RESULT_OK, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::phy_rx, fpc_com_chain::phy_timeout_rx, fpc_com_chain::phy_timeout_tx, fpc_com_chain::phy_tx, fpc_com_chain::session, and fpc_com_packet_link::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_link_transmit (fpc_com_packet_link_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Sends a packet over the physical link in blocking mode.

+
Parameters
+ + + +
[in]packetPacket to transmit.
[in]chainThe communication chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 27 of file fpc_com_link.c.

+ +

References fpc_com_packet_link::channel, fpc_com_packet_link::crc, fpc_com_chain::crc_calc, fpc_com_packet_link::data, FPC_COM_ACK, FPC_COM_CHAIN_TX, fpc_com_link_get_overhead(), FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_IO_ERROR, FPC_COM_RESULT_OK, FPC_COM_RESULT_TIMEOUT, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_rx, fpc_com_chain::phy_timeout_rx, fpc_com_chain::phy_timeout_tx, fpc_com_chain::phy_tx, fpc_com_chain::session, and fpc_com_packet_link::size.

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+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h.js b/hcp/doxygen/html/fpc__com__link_8h.js new file mode 100644 index 0000000..31e19e9 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h.js @@ -0,0 +1,6 @@ +var fpc__com__link_8h = +[ + [ "fpc_com_link_get_overhead", "fpc__com__link_8h.html#a3e60e21a5ac4ad4881e4929de2f3c2f4", null ], + [ "fpc_com_link_receive", "fpc__com__link_8h.html#ae64b80cd91fbfe44abc06dc52eacf739", null ], + [ "fpc_com_link_transmit", "fpc__com__link_8h.html#a43a8a308255ea41e7b7cdefd63a90d14", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8h__dep__incl.map b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.map new file mode 100644 index 0000000..e1b2862 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.map @@ -0,0 +1,4 @@ + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h__dep__incl.md5 b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.md5 new file mode 100644 index 0000000..dd31e89 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.md5 @@ -0,0 +1 @@ +25bb356645f94e2250849d59b6042d5f \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8h__dep__incl.svg b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.svg new file mode 100644 index 0000000..befe4d2 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__dep__incl.svg @@ -0,0 +1,44 @@ + + + + + + +inc/fpc_com_link.h + + +Node1 + +inc/fpc_com_link.h + + +Node2 + + +src/fpc_com_link.c + + + + +Node1->Node2 + + + + +Node3 + + +src/fpc_com_transport.c + + + + +Node1->Node3 + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h__incl.map b/hcp/doxygen/html/fpc__com__link_8h__incl.map new file mode 100644 index 0000000..905eabf --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__incl.map @@ -0,0 +1,6 @@ + + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h__incl.md5 b/hcp/doxygen/html/fpc__com__link_8h__incl.md5 new file mode 100644 index 0000000..fcda822 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__incl.md5 @@ -0,0 +1 @@ +2693b0444fc65501786e794e5550d85c \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8h__incl.svg b/hcp/doxygen/html/fpc__com__link_8h__incl.svg new file mode 100644 index 0000000..a6f11c1 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h__incl.svg @@ -0,0 +1,120 @@ + + + + + + +inc/fpc_com_link.h + + +Node1 + +inc/fpc_com_link.h + + +Node2 + +stdbool.h + + +Node1->Node2 + + + + +Node3 + +stdint.h + + +Node1->Node3 + + + + +Node4 + + +fpc_com_result.h + + + + +Node1->Node4 + + + + +Node5 + + +fpc_com_chain.h + + + + +Node1->Node5 + + + + +Node4->Node3 + + + + +Node5->Node3 + + + + +Node5->Node4 + + + + +Node6 + + +fpc_hcp_common.h + + + + +Node5->Node6 + + + + +Node7 + + +fpc_com_packets.h + + + + +Node5->Node7 + + + + +Node6->Node2 + + + + +Node6->Node3 + + + + +Node7->Node3 + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map new file mode 100644 index 0000000..621ae0a --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 new file mode 100644 index 0000000..7012d06 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.md5 @@ -0,0 +1 @@ +1079db44f9fcfecbed78b0a2bbb98b54 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg new file mode 100644 index 0000000..1fce018 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h_a43a8a308255ea41e7b7cdefd63a90d14_cgraph.svg @@ -0,0 +1,31 @@ + + + + + + +fpc_com_link_transmit + + +Node1 + +fpc_com_link_transmit + + +Node2 + + +fpc_com_link_get_overhead + + + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__link_8h_source.html b/hcp/doxygen/html/fpc__com__link_8h_source.html new file mode 100644 index 0000000..72874d3 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__link_8h_source.html @@ -0,0 +1,92 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_link.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_link.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_COM_LINK_H
23 #define FPC_COM_LINK_H
24 
25 #include <stdbool.h>
26 #include <stdint.h>
27 
28 #include "fpc_com_result.h"
29 #include "fpc_com_chain.h"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif /* __cplusplus */
34 
42 fpc_com_result_t fpc_com_link_transmit(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain);
43 
51 fpc_com_result_t fpc_com_link_receive(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain);
52 
59 uint16_t fpc_com_link_get_overhead(uint16_t *offset);
60 
61 #ifdef __cplusplus
62 }
63 #endif /* __cplusplus */
64 
65 #endif /* FPC_COM_LINK_H */
fpc_com_chain
Definition: fpc_com_chain.h:50
+
fpc_com_result.h
Communication result type definitions.
+
fpc_com_link_receive
fpc_com_result_t fpc_com_link_receive(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Receives a packet from the physical link.
Definition: fpc_com_link.c:73
+
fpc_com_link_transmit
fpc_com_result_t fpc_com_link_transmit(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Sends a packet over the physical link in blocking mode.
Definition: fpc_com_link.c:27
+
fpc_com_chain.h
Communication chain type definitions.
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_link_get_overhead
uint16_t fpc_com_link_get_overhead(uint16_t *offset)
Returns the overhead of the layer.
Definition: fpc_com_link.c:126
+
fpc_com_packet_link
Definition: fpc_com_packets.h:61
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h.html b/hcp/doxygen/html/fpc__com__packets_8h.html new file mode 100644 index 0000000..cf73c5d --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h.html @@ -0,0 +1,231 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_packets.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Structures | +Macros | +Typedefs | +Enumerations
+
+
fpc_com_packets.h File Reference
+
+
+ +

Communication packet type definitions. +More...

+
#include <stdint.h>
+
+Include dependency graph for fpc_com_packets.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + +

+Data Structures

struct  fpc_com_packet_transport
 
struct  fpc_com_packet_link
 
+ + + +

+Macros

#define FPC_COM_ACK   0x7f01ff7f
 
+ + + + + + + +

+Typedefs

typedef struct fpc_com_packet_transport fpc_com_packet_tsp_t
 
typedef uint16_t fpc_com_channel_t
 
typedef struct fpc_com_packet_link fpc_com_packet_link_t
 
+ + + +

+Enumerations

enum  fpc_com_channel {
+  FPC_COM_CHANNEL_NONE = 0x00, +
+  FPC_COM_CHANNEL_CLEAR = 0x01, +
+  FPC_COM_CHANNEL_TLS = 0x02, +
+  FPC_COM_CHANNEL_END = 0xFF +
+ }
 
+

Detailed Description

+

Communication packet type definitions.

+ +

Definition in file fpc_com_packets.h.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define FPC_COM_ACK   0x7f01ff7f
+
+

Communication acknowledge definition

+ +

Definition at line 32 of file fpc_com_packets.h.

+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef uint16_t fpc_com_channel_t
+
+

Communication channel type

+ +

Definition at line 58 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
typedef struct fpc_com_packet_link fpc_com_packet_link_t
+
+

Link layer packet

+ +
+
+ +
+
+ + + + +
typedef struct fpc_com_packet_transport fpc_com_packet_tsp_t
+
+

Transport layer packet.

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum fpc_com_channel
+
+

Transport packet channels.

+ + + + + +
Enumerator
FPC_COM_CHANNEL_NONE  +
FPC_COM_CHANNEL_CLEAR  +
FPC_COM_CHANNEL_TLS  +
FPC_COM_CHANNEL_END  +
+ +

Definition at line 51 of file fpc_com_packets.h.

+ +
+
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h.js b/hcp/doxygen/html/fpc__com__packets_8h.js new file mode 100644 index 0000000..719f942 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h.js @@ -0,0 +1,15 @@ +var fpc__com__packets_8h = +[ + [ "fpc_com_packet_transport", "structfpc__com__packet__transport.html", "structfpc__com__packet__transport" ], + [ "fpc_com_packet_link", "structfpc__com__packet__link.html", "structfpc__com__packet__link" ], + [ "FPC_COM_ACK", "fpc__com__packets_8h.html#a4f4c239eb61e8e793498793c1be608f7", null ], + [ "fpc_com_channel_t", "fpc__com__packets_8h.html#a243c6cf0a9ab056a1fce6430bb88c2d8", null ], + [ "fpc_com_packet_link_t", "fpc__com__packets_8h.html#af6fc3a46c87f1ad2a452eb822f2a0942", null ], + [ "fpc_com_packet_tsp_t", "fpc__com__packets_8h.html#a056a2f08f90fe7e467988b2ddbc41f3c", null ], + [ "fpc_com_channel", "fpc__com__packets_8h.html#ad77ec293a161472c5ca6283ae1c944c8", [ + [ "FPC_COM_CHANNEL_NONE", "fpc__com__packets_8h.html#ad77ec293a161472c5ca6283ae1c944c8a82d8a35822a610caddc5c841e3a74a2a", null ], + [ "FPC_COM_CHANNEL_CLEAR", "fpc__com__packets_8h.html#ad77ec293a161472c5ca6283ae1c944c8aff1cc469181cd2df91ed52a2092748ed", null ], + [ "FPC_COM_CHANNEL_TLS", "fpc__com__packets_8h.html#ad77ec293a161472c5ca6283ae1c944c8ae9bbbecb694256ca41a9b57f101fb973", null ], + [ "FPC_COM_CHANNEL_END", "fpc__com__packets_8h.html#ad77ec293a161472c5ca6283ae1c944c8af73ea123cd946a1ef0109660569cd856", null ] + ] ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.map b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.map new file mode 100644 index 0000000..590a765 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.md5 b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.md5 new file mode 100644 index 0000000..88f83de --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.md5 @@ -0,0 +1 @@ +061c95db64158805437ca80c13b84b7d \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.svg b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.svg new file mode 100644 index 0000000..45b3697 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__dep__incl.svg @@ -0,0 +1,114 @@ + + + + + + +inc/fpc_com_packets.h + + +Node1 + +inc/fpc_com_packets.h + + +Node2 + + +inc/fpc_com_chain.h + + + + +Node1->Node2 + + + + +Node3 + + +inc/fpc_com_link.h + + + + +Node2->Node3 + + + + +Node6 + + +inc/fpc_com_transport.h + + + + +Node2->Node6 + + + + +Node7 + + +inc/fpc_hcp.h + + + + +Node2->Node7 + + + + +Node4 + + +src/fpc_com_link.c + + + + +Node3->Node4 + + + + +Node5 + + +src/fpc_com_transport.c + + + + +Node3->Node5 + + + + +Node6->Node5 + + + + +Node8 + + +src/fpc_hcp.c + + + + +Node7->Node8 + + + + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h__incl.map b/hcp/doxygen/html/fpc__com__packets_8h__incl.map new file mode 100644 index 0000000..2b9729a --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h__incl.md5 b/hcp/doxygen/html/fpc__com__packets_8h__incl.md5 new file mode 100644 index 0000000..8993b28 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__incl.md5 @@ -0,0 +1 @@ +f1d62a394723cf9f4c0d14de4aab5e68 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__packets_8h__incl.svg b/hcp/doxygen/html/fpc__com__packets_8h__incl.svg new file mode 100644 index 0000000..c7079f1 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h__incl.svg @@ -0,0 +1,28 @@ + + + + + + +inc/fpc_com_packets.h + + +Node1 + +inc/fpc_com_packets.h + + +Node2 + +stdint.h + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__packets_8h_source.html b/hcp/doxygen/html/fpc__com__packets_8h_source.html new file mode 100644 index 0000000..a9b983c --- /dev/null +++ b/hcp/doxygen/html/fpc__com__packets_8h_source.html @@ -0,0 +1,102 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_packets.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_packets.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_COM_PACKETS_H
23 #define FPC_COM_PACKETS_H
24 
25 #include <stdint.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif /* __cplusplus */
30 
32 #define FPC_COM_ACK 0x7f01ff7f
33 
37 typedef struct fpc_com_packet_transport {
39  uint16_t size;
41  uint16_t seq_len;
43  uint16_t seq_nr;
45  uint8_t *data;
46 } fpc_com_packet_tsp_t;
47 
51 enum fpc_com_channel {
52  FPC_COM_CHANNEL_NONE = 0x00,
53  FPC_COM_CHANNEL_CLEAR = 0x01,
54  FPC_COM_CHANNEL_TLS = 0x02,
55  FPC_COM_CHANNEL_END = 0xFF,
56 };
58 typedef uint16_t fpc_com_channel_t;
59 
61 typedef struct fpc_com_packet_link {
63  fpc_com_channel_t channel;
65  uint16_t size;
67  uint8_t *data;
69  uint32_t crc;
70 } fpc_com_packet_link_t;
71 
72 #ifdef __cplusplus
73 }
74 #endif /* __cplusplus */
75 
76 #endif /* FPC_COM_PACKETS_H */
FPC_COM_CHANNEL_CLEAR
Definition: fpc_com_packets.h:53
+
fpc_com_packet_link_t
struct fpc_com_packet_link fpc_com_packet_link_t
+
fpc_com_channel
fpc_com_channel
Definition: fpc_com_packets.h:51
+
fpc_com_packet_transport::data
uint8_t * data
Definition: fpc_com_packets.h:45
+
FPC_COM_CHANNEL_NONE
Definition: fpc_com_packets.h:52
+
fpc_com_packet_link::size
uint16_t size
Definition: fpc_com_packets.h:65
+
fpc_com_packet_transport
Definition: fpc_com_packets.h:37
+
FPC_COM_CHANNEL_TLS
Definition: fpc_com_packets.h:54
+
fpc_com_packet_link::data
uint8_t * data
Definition: fpc_com_packets.h:67
+
fpc_com_packet_tsp_t
struct fpc_com_packet_transport fpc_com_packet_tsp_t
+
FPC_COM_CHANNEL_END
Definition: fpc_com_packets.h:55
+
fpc_com_packet_link::channel
fpc_com_channel_t channel
Definition: fpc_com_packets.h:63
+
fpc_com_packet_transport::seq_len
uint16_t seq_len
Definition: fpc_com_packets.h:41
+
fpc_com_packet_link::crc
uint32_t crc
Definition: fpc_com_packets.h:69
+
fpc_com_channel_t
uint16_t fpc_com_channel_t
Definition: fpc_com_packets.h:58
+
fpc_com_packet_transport::seq_nr
uint16_t seq_nr
Definition: fpc_com_packets.h:43
+
fpc_com_packet_transport::size
uint16_t size
Definition: fpc_com_packets.h:39
+
fpc_com_packet_link
Definition: fpc_com_packets.h:61
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__result_8h.html b/hcp/doxygen/html/fpc__com__result_8h.html new file mode 100644 index 0000000..ba641c1 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h.html @@ -0,0 +1,179 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_result.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Typedefs | +Enumerations
+
+
fpc_com_result.h File Reference
+
+
+ +

Communication result type definitions. +More...

+
#include <stdint.h>
+
+Include dependency graph for fpc_com_result.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + +

+Typedefs

typedef uint8_t fpc_com_result_t
 
+ + + +

+Enumerations

enum  fpc_com_result {
+  FPC_COM_RESULT_OK, +
+  FPC_COM_RESULT_NO_MEMORY, +
+  FPC_COM_RESULT_INVALID_ARGUMENT, +
+  FPC_COM_RESULT_NOT_IMPLEMENTED, +
+  FPC_COM_RESULT_IO_ERROR, +
+  FPC_COM_RESULT_TIMEOUT +
+ }
 
+

Detailed Description

+

Communication result type definitions.

+ +

Definition in file fpc_com_result.h.

+

Typedef Documentation

+ +
+
+ + + + +
typedef uint8_t fpc_com_result_t
+
+

Communication result type

+ +

Definition at line 41 of file fpc_com_result.h.

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum fpc_com_result
+
+

Communication result codes

+ + + + + + + +
Enumerator
FPC_COM_RESULT_OK  +
FPC_COM_RESULT_NO_MEMORY  +
FPC_COM_RESULT_INVALID_ARGUMENT  +
FPC_COM_RESULT_NOT_IMPLEMENTED  +
FPC_COM_RESULT_IO_ERROR  +
FPC_COM_RESULT_TIMEOUT  +
+ +

Definition at line 32 of file fpc_com_result.h.

+ +
+
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__result_8h.js b/hcp/doxygen/html/fpc__com__result_8h.js new file mode 100644 index 0000000..b1add6d --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h.js @@ -0,0 +1,12 @@ +var fpc__com__result_8h = +[ + [ "fpc_com_result_t", "fpc__com__result_8h.html#a49b1f9a24f677d396227ea645494070a", null ], + [ "fpc_com_result", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897a", [ + [ "FPC_COM_RESULT_OK", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aaa4090b7c45045bce15b6b8d9cd7ef914", null ], + [ "FPC_COM_RESULT_NO_MEMORY", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aa5c99bdb5025135bc89f86391ed9cf039", null ], + [ "FPC_COM_RESULT_INVALID_ARGUMENT", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aa2e96fad27e661c9eb3bce808d0d7e92e", null ], + [ "FPC_COM_RESULT_NOT_IMPLEMENTED", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aa01c8c09db85b54df5cb355631c36fe4e", null ], + [ "FPC_COM_RESULT_IO_ERROR", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aa9018f4fe6916e76acf8f1a8391d9b80f", null ], + [ "FPC_COM_RESULT_TIMEOUT", "fpc__com__result_8h.html#a5435902ad319b641b2758a2f8f48897aa37ce8bdd82e871575b23e9f1d6f06dbf", null ] + ] ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__result_8h__dep__incl.map b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.map new file mode 100644 index 0000000..ec44453 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.map @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/hcp/doxygen/html/fpc__com__result_8h__dep__incl.md5 b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.md5 new file mode 100644 index 0000000..b12a1a6 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.md5 @@ -0,0 +1 @@ +8c259507ddbf28df71e644395974c58b \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__result_8h__dep__incl.svg b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.svg new file mode 100644 index 0000000..26f1de6 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__dep__incl.svg @@ -0,0 +1,119 @@ + + + + + + +inc/fpc_com_result.h + + +Node1 + +inc/fpc_com_result.h + + +Node2 + + +inc/fpc_com_chain.h + + + + +Node1->Node2 + + + + +Node3 + + +inc/fpc_com_link.h + + + + +Node1->Node3 + + + + +Node2->Node3 + + + + +Node6 + + +inc/fpc_com_transport.h + + + + +Node2->Node6 + + + + +Node7 + + +inc/fpc_hcp.h + + + + +Node2->Node7 + + + + +Node4 + + +src/fpc_com_link.c + + + + +Node3->Node4 + + + + +Node5 + + +src/fpc_com_transport.c + + + + +Node3->Node5 + + + + +Node6->Node5 + + + + +Node8 + + +src/fpc_hcp.c + + + + +Node7->Node8 + + + + + diff --git a/hcp/doxygen/html/fpc__com__result_8h__incl.map b/hcp/doxygen/html/fpc__com__result_8h__incl.map new file mode 100644 index 0000000..6fcc9b3 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__incl.map @@ -0,0 +1,2 @@ + + diff --git a/hcp/doxygen/html/fpc__com__result_8h__incl.md5 b/hcp/doxygen/html/fpc__com__result_8h__incl.md5 new file mode 100644 index 0000000..0f2eca8 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__incl.md5 @@ -0,0 +1 @@ +59ffa2fa2be94ddda3a06d18caab6576 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__result_8h__incl.svg b/hcp/doxygen/html/fpc__com__result_8h__incl.svg new file mode 100644 index 0000000..d206e53 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h__incl.svg @@ -0,0 +1,28 @@ + + + + + + +inc/fpc_com_result.h + + +Node1 + +inc/fpc_com_result.h + + +Node2 + +stdint.h + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__result_8h_source.html b/hcp/doxygen/html/fpc__com__result_8h_source.html new file mode 100644 index 0000000..2aeb43c --- /dev/null +++ b/hcp/doxygen/html/fpc__com__result_8h_source.html @@ -0,0 +1,92 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_result.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_result.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_COM_RESULT_H
23 #define FPC_COM_RESULT_H
24 
25 #include <stdint.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif /* __cplusplus */
30 
32 enum fpc_com_result {
33  FPC_COM_RESULT_OK,
34  FPC_COM_RESULT_NO_MEMORY,
35  FPC_COM_RESULT_INVALID_ARGUMENT,
36  FPC_COM_RESULT_NOT_IMPLEMENTED,
37  FPC_COM_RESULT_IO_ERROR,
38  FPC_COM_RESULT_TIMEOUT,
39 };
41 typedef uint8_t fpc_com_result_t;
42 
43 #ifdef __cplusplus
44 }
45 #endif /* __cplusplus */
46 
47 #endif /* FPC_COM_RESULT_H */
FPC_COM_RESULT_IO_ERROR
Definition: fpc_com_result.h:37
+
FPC_COM_RESULT_NOT_IMPLEMENTED
Definition: fpc_com_result.h:36
+
FPC_COM_RESULT_TIMEOUT
Definition: fpc_com_result.h:38
+
FPC_COM_RESULT_INVALID_ARGUMENT
Definition: fpc_com_result.h:35
+
fpc_com_result
fpc_com_result
Definition: fpc_com_result.h:32
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
FPC_COM_RESULT_NO_MEMORY
Definition: fpc_com_result.h:34
+
FPC_COM_RESULT_OK
Definition: fpc_com_result.h:33
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c.html b/hcp/doxygen/html/fpc__com__transport_8c.html new file mode 100644 index 0000000..6ab9ec5 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c.html @@ -0,0 +1,244 @@ + + + + + + +Host Communication Protocol: src/fpc_com_transport.c File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Functions
+
+
fpc_com_transport.c File Reference
+
+
+ +

Communication transport layer implementation. +More...

+
#include <stdlib.h>
+#include <string.h>
+#include "fpc_com_link.h"
+#include "fpc_com_transport.h"
+
+Include dependency graph for fpc_com_transport.c:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Functions

fpc_com_result_t fpc_com_transport_transmit (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 Transmit a transport layer packet. More...
 
fpc_com_result_t fpc_com_transport_receive (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 Receive a transport layer packet. More...
 
uint16_t fpc_com_transport_get_overhead (uint16_t *offset)
 Returns the overhead of the layer. More...
 
+

Detailed Description

+

Communication transport layer implementation.

+ +

Definition in file fpc_com_transport.c.

+

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t fpc_com_transport_get_overhead (uint16_t * offset)
+
+ +

Returns the overhead of the layer.

+
Parameters
+ + +
[out]offsetThe offset to the packet data.
+
+
+
Returns
Overhead size in bytes.
+ +

Definition at line 88 of file fpc_com_transport.c.

+ +

References fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, and fpc_com_packet_transport::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_transport_receive (fpc_com_packet_tsp_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receive a transport layer packet.

+
Parameters
+ + + +
[in,out]packetThe packet to populate.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 60 of file fpc_com_transport.c.

+ +

References fpc_com_packet_transport::data, fpc_com_packet_link::data, fpc_com_link_receive(), FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_OK, fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, and fpc_com_packet_transport::size.

+ +

+Here is the call graph for this function:
+
+
+
+
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_transport_transmit (fpc_com_packet_tsp_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Transmit a transport layer packet.

+
Parameters
+ + + +
[in]packetThe packet to transmit.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 28 of file fpc_com_transport.c.

+ +

References fpc_com_packet_link::channel, fpc_com_chain::channel, fpc_com_packet_link::data, FPC_COM_CHAIN_TX, fpc_com_link_transmit(), FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, fpc_com_packet_transport::size, fpc_com_packet_link::size, and fpc_com_chain::tsp_overhead_get.

+ +

+Here is the call graph for this function:
+
+
+
+
+

+ +
+
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c.js b/hcp/doxygen/html/fpc__com__transport_8c.js new file mode 100644 index 0000000..ad4d579 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c.js @@ -0,0 +1,6 @@ +var fpc__com__transport_8c = +[ + [ "fpc_com_transport_get_overhead", "fpc__com__transport_8c.html#ab5c3ffee064012e456917a1b37d30938", null ], + [ "fpc_com_transport_receive", "fpc__com__transport_8c.html#acc641d17a6f587ceb132b5500390f99a", null ], + [ "fpc_com_transport_transmit", "fpc__com__transport_8c.html#af7766ded38ea5a21005d9c99dbd24a72", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8c__incl.map b/hcp/doxygen/html/fpc__com__transport_8c__incl.map new file mode 100644 index 0000000..76e9460 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c__incl.map @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c__incl.md5 b/hcp/doxygen/html/fpc__com__transport_8c__incl.md5 new file mode 100644 index 0000000..fa4345d --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c__incl.md5 @@ -0,0 +1 @@ +e2ee468a645c6759453b89bbbb374223 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8c__incl.svg b/hcp/doxygen/html/fpc__com__transport_8c__incl.svg new file mode 100644 index 0000000..b5bad52 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c__incl.svg @@ -0,0 +1,176 @@ + + + + + + +src/fpc_com_transport.c + + +Node1 + +src/fpc_com_transport.c + + +Node2 + +stdlib.h + + +Node1->Node2 + + + + +Node3 + +string.h + + +Node1->Node3 + + + + +Node4 + + +fpc_com_link.h + + + + +Node1->Node4 + + + + +Node11 + + +fpc_com_transport.h + + + + +Node1->Node11 + + + + +Node5 + +stdbool.h + + +Node4->Node5 + + + + +Node6 + +stdint.h + + +Node4->Node6 + + + + +Node7 + + +fpc_com_result.h + + + + +Node4->Node7 + + + + +Node8 + + +fpc_com_chain.h + + + + +Node4->Node8 + + + + +Node7->Node6 + + + + +Node8->Node6 + + + + +Node8->Node7 + + + + +Node9 + + +fpc_hcp_common.h + + + + +Node8->Node9 + + + + +Node10 + + +fpc_com_packets.h + + + + +Node8->Node10 + + + + +Node9->Node5 + + + + +Node9->Node6 + + + + +Node10->Node6 + + + + +Node11->Node6 + + + + +Node11->Node8 + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.map b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.map new file mode 100644 index 0000000..7ab2bf1 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 new file mode 100644 index 0000000..ad3feb8 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 @@ -0,0 +1 @@ +fc06ca2920b5dc571e73125ea600e963 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.svg b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.svg new file mode 100644 index 0000000..ffb034f --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_acc641d17a6f587ceb132b5500390f99a_cgraph.svg @@ -0,0 +1,31 @@ + + + + + + +fpc_com_transport_receive + + +Node1 + +fpc_com_transport_receive + + +Node2 + + +fpc_com_link_receive + + + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map new file mode 100644 index 0000000..e09af63 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 new file mode 100644 index 0000000..22f7f28 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 @@ -0,0 +1 @@ +20f39a00e89e8d273c4640a927738f62 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg new file mode 100644 index 0000000..4580bd6 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg @@ -0,0 +1,44 @@ + + + + + + +fpc_com_transport_transmit + + +Node1 + +fpc_com_transport_transmit + + +Node2 + + +fpc_com_link_transmit + + + + +Node1->Node2 + + + + +Node3 + + +fpc_com_link_get_overhead + + + + +Node2->Node3 + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8c_source.html b/hcp/doxygen/html/fpc__com__transport_8c_source.html new file mode 100644 index 0000000..fb9e30d --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8c_source.html @@ -0,0 +1,109 @@ + + + + + + +Host Communication Protocol: src/fpc_com_transport.c Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_transport.c
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #include <stdlib.h>
23 #include <string.h>
24 
25 #include "fpc_com_link.h"
26 #include "fpc_com_transport.h"
27 
28 fpc_com_result_t fpc_com_transport_transmit(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
29 {
30  fpc_com_packet_link_t link_packet = { 0 };
31  fpc_com_result_t result;
32  uint16_t link_offset;
33  uint16_t offset;
34 
35  if (packet == NULL|| chain == NULL) {
36  result = FPC_COM_RESULT_INVALID_ARGUMENT;
37  goto exit;
38  }
39 
40  /* Construct header */
41  chain->link_overhead_get(&link_offset);
42  link_packet.data = chain->phy_mtu_buffer[FPC_COM_CHAIN_TX] + link_offset;
43 
44  *((uint16_t *)(link_packet.data)) = packet->size;
45  offset = sizeof(packet->size);
46  *((uint16_t *)(link_packet.data + offset)) = packet->seq_nr;
47  offset += sizeof(packet->seq_nr);
48  *((uint16_t *)(link_packet.data + offset)) = packet->seq_len;
49 
50  link_packet.channel = chain->channel;
51  link_packet.size = packet->size + chain->tsp_overhead_get(NULL);
52 
53  /* Send packet */
54  result = fpc_com_link_transmit(&link_packet, chain);
55 
56 exit:
57  return result;
58 }
59 
60 fpc_com_result_t fpc_com_transport_receive(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
61 {
62  fpc_com_packet_link_t link_packet = { 0 };
63  fpc_com_result_t result;
64  uint16_t offset;
65 
66  if (packet == NULL|| chain == NULL) {
67  result = FPC_COM_RESULT_INVALID_ARGUMENT;
68  goto exit;
69  }
70 
71  result = fpc_com_link_receive(&link_packet, chain);
72  if (result != FPC_COM_RESULT_OK) {
73  goto exit;
74  }
75 
76  packet->size = *((uint16_t *)link_packet.data);
77  offset = sizeof(packet->size);
78  packet->seq_nr = *((uint16_t *)(link_packet.data + offset));
79  offset += sizeof(packet->seq_nr);
80  packet->seq_len = *((uint16_t *)(link_packet.data + offset));
81  offset += sizeof(packet->seq_len);
82  packet->data = link_packet.data + offset;
83 
84 exit:
85  return result;
86 }
87 
88 uint16_t fpc_com_transport_get_overhead(uint16_t *offset)
89 {
90  fpc_com_packet_tsp_t *packet;
91  static const uint16_t internal_offset = sizeof(packet->size) + sizeof(packet->seq_len)
92  + sizeof(packet->seq_nr);
93 
94  if (offset) {
95  *offset = internal_offset;
96  }
97 
98  return internal_offset;
99 }
fpc_com_transport_transmit
fpc_com_result_t fpc_com_transport_transmit(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
Transmit a transport layer packet.
Definition: fpc_com_transport.c:28
+
fpc_com_chain::tsp_overhead_get
uint16_t(* tsp_overhead_get)(uint16_t *offset)
Definition: fpc_com_chain.h:95
+
fpc_com_chain::phy_mtu_buffer
uint8_t * phy_mtu_buffer[2]
Definition: fpc_com_chain.h:121
+
fpc_com_chain
Definition: fpc_com_chain.h:50
+
FPC_COM_CHAIN_TX
Definition: fpc_com_chain.h:150
+
fpc_com_packet_transport::data
uint8_t * data
Definition: fpc_com_packets.h:45
+
fpc_com_packet_link::size
uint16_t size
Definition: fpc_com_packets.h:65
+
fpc_com_packet_transport
Definition: fpc_com_packets.h:37
+
fpc_com_link_receive
fpc_com_result_t fpc_com_link_receive(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Receives a packet from the physical link.
Definition: fpc_com_link.c:73
+
FPC_COM_RESULT_INVALID_ARGUMENT
Definition: fpc_com_result.h:35
+
fpc_com_chain::channel
fpc_com_channel_t channel
Definition: fpc_com_chain.h:105
+
fpc_com_link_transmit
fpc_com_result_t fpc_com_link_transmit(fpc_com_packet_link_t *packet, fpc_com_chain_t *chain)
Sends a packet over the physical link in blocking mode.
Definition: fpc_com_link.c:27
+
fpc_com_transport_receive
fpc_com_result_t fpc_com_transport_receive(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
Receive a transport layer packet.
Definition: fpc_com_transport.c:60
+
fpc_com_packet_link::data
uint8_t * data
Definition: fpc_com_packets.h:67
+
fpc_com_packet_link::channel
fpc_com_channel_t channel
Definition: fpc_com_packets.h:63
+
fpc_com_packet_transport::seq_len
uint16_t seq_len
Definition: fpc_com_packets.h:41
+
fpc_com_chain::link_overhead_get
uint16_t(* link_overhead_get)(uint16_t *offset)
Definition: fpc_com_chain.h:103
+
fpc_com_transport.h
Communication transport interface.
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_link.h
Communication link interface.
+
fpc_com_packet_transport::seq_nr
uint16_t seq_nr
Definition: fpc_com_packets.h:43
+
fpc_com_packet_transport::size
uint16_t size
Definition: fpc_com_packets.h:39
+
FPC_COM_RESULT_OK
Definition: fpc_com_result.h:33
+
fpc_com_transport_get_overhead
uint16_t fpc_com_transport_get_overhead(uint16_t *offset)
Returns the overhead of the layer.
Definition: fpc_com_transport.c:88
+
fpc_com_packet_link
Definition: fpc_com_packets.h:61
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h.html b/hcp/doxygen/html/fpc__com__transport_8h.html new file mode 100644 index 0000000..caf8e31 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h.html @@ -0,0 +1,248 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_transport.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Functions
+
+
fpc_com_transport.h File Reference
+
+
+ +

Communication transport interface. +More...

+
#include <stdint.h>
+#include "fpc_com_chain.h"
+
+Include dependency graph for fpc_com_transport.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + + + + + + +

+Functions

fpc_com_result_t fpc_com_transport_transmit (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 Transmit a transport layer packet. More...
 
fpc_com_result_t fpc_com_transport_receive (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 Receive a transport layer packet. More...
 
uint16_t fpc_com_transport_get_overhead (uint16_t *offset)
 Returns the overhead of the layer. More...
 
+

Detailed Description

+

Communication transport interface.

+ +

Definition in file fpc_com_transport.h.

+

Function Documentation

+ +
+
+ + + + + + + + +
uint16_t fpc_com_transport_get_overhead (uint16_t * offset)
+
+ +

Returns the overhead of the layer.

+
Parameters
+ + +
[out]offsetThe offset to the packet data.
+
+
+
Returns
Overhead size in bytes.
+ +

Definition at line 88 of file fpc_com_transport.c.

+ +

References fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, and fpc_com_packet_transport::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_transport_receive (fpc_com_packet_tsp_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receive a transport layer packet.

+
Parameters
+ + + +
[in,out]packetThe packet to populate.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 60 of file fpc_com_transport.c.

+ +

References fpc_com_packet_transport::data, fpc_com_packet_link::data, fpc_com_link_receive(), FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_OK, fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, and fpc_com_packet_transport::size.

+ +

+Here is the call graph for this function:
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+

+ +
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+ +
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+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_com_transport_transmit (fpc_com_packet_tsp_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Transmit a transport layer packet.

+
Parameters
+ + + +
[in]packetThe packet to transmit.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 28 of file fpc_com_transport.c.

+ +

References fpc_com_packet_link::channel, fpc_com_chain::channel, fpc_com_packet_link::data, FPC_COM_CHAIN_TX, fpc_com_link_transmit(), FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_packet_transport::seq_len, fpc_com_packet_transport::seq_nr, fpc_com_packet_transport::size, fpc_com_packet_link::size, and fpc_com_chain::tsp_overhead_get.

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+Here is the call graph for this function:
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+

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+ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h.js b/hcp/doxygen/html/fpc__com__transport_8h.js new file mode 100644 index 0000000..0c4c394 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h.js @@ -0,0 +1,6 @@ +var fpc__com__transport_8h = +[ + [ "fpc_com_transport_get_overhead", "fpc__com__transport_8h.html#ab5c3ffee064012e456917a1b37d30938", null ], + [ "fpc_com_transport_receive", "fpc__com__transport_8h.html#acc641d17a6f587ceb132b5500390f99a", null ], + [ "fpc_com_transport_transmit", "fpc__com__transport_8h.html#af7766ded38ea5a21005d9c99dbd24a72", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8h__dep__incl.map b/hcp/doxygen/html/fpc__com__transport_8h__dep__incl.map new file mode 100644 index 0000000..6d8a497 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h__dep__incl.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h__dep__incl.md5 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a/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.map b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.map new file mode 100644 index 0000000..7ab2bf1 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 new file mode 100644 index 0000000..ad3feb8 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.md5 @@ -0,0 +1 @@ +fc06ca2920b5dc571e73125ea600e963 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.svg b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.svg new file mode 100644 index 0000000..ffb034f --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_acc641d17a6f587ceb132b5500390f99a_cgraph.svg @@ -0,0 +1,31 @@ + + + + + + +fpc_com_transport_receive + + +Node1 + +fpc_com_transport_receive + + +Node2 + + +fpc_com_link_receive + + + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map new file mode 100644 index 0000000..e09af63 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.map @@ -0,0 +1,4 @@ + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 new file mode 100644 index 0000000..22f7f28 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.md5 @@ -0,0 +1 @@ +20f39a00e89e8d273c4640a927738f62 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg new file mode 100644 index 0000000..4580bd6 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_af7766ded38ea5a21005d9c99dbd24a72_cgraph.svg @@ -0,0 +1,44 @@ + + + + + + +fpc_com_transport_transmit + + +Node1 + +fpc_com_transport_transmit + + +Node2 + + +fpc_com_link_transmit + + + + +Node1->Node2 + + + + +Node3 + + +fpc_com_link_get_overhead + + + + +Node2->Node3 + + + + + diff --git a/hcp/doxygen/html/fpc__com__transport_8h_source.html b/hcp/doxygen/html/fpc__com__transport_8h_source.html new file mode 100644 index 0000000..1deb259 --- /dev/null +++ b/hcp/doxygen/html/fpc__com__transport_8h_source.html @@ -0,0 +1,91 @@ + + + + + + +Host Communication Protocol: inc/fpc_com_transport.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_com_transport.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_COM_TRANSPORT_H
23 #define FPC_COM_TRANSPORT_H
24 
25 #include <stdint.h>
26 
27 #include "fpc_com_chain.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif /* __cplusplus */
32 
40 fpc_com_result_t fpc_com_transport_transmit(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain);
41 
49 fpc_com_result_t fpc_com_transport_receive(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain);
50 
57 uint16_t fpc_com_transport_get_overhead(uint16_t *offset);
58 
59 #ifdef __cplusplus
60 }
61 #endif /* __cplusplus */
62 
63 #endif /* FPC_COM_TRANSPORT_H */
fpc_com_chain
Definition: fpc_com_chain.h:50
+
fpc_com_transport_transmit
fpc_com_result_t fpc_com_transport_transmit(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
Transmit a transport layer packet.
Definition: fpc_com_transport.c:28
+
fpc_com_transport_get_overhead
uint16_t fpc_com_transport_get_overhead(uint16_t *offset)
Returns the overhead of the layer.
Definition: fpc_com_transport.c:88
+
fpc_com_packet_transport
Definition: fpc_com_packets.h:37
+
fpc_com_chain.h
Communication chain type definitions.
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_transport_receive
fpc_com_result_t fpc_com_transport_receive(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
Receive a transport layer packet.
Definition: fpc_com_transport.c:60
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__hcp_8c.html b/hcp/doxygen/html/fpc__hcp_8c.html new file mode 100644 index 0000000..7bbe551 --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp_8c.html @@ -0,0 +1,721 @@ + + + + + + +Host Communication Protocol: src/fpc_hcp.c File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Functions
+
+
fpc_hcp.c File Reference
+
+
+ +

Host Communication Protocol implementation. +More...

+
#include <stdlib.h>
+#include <string.h>
+#include "fpc_hcp.h"
+
+Include dependency graph for fpc_hcp.c:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + + + + + + + + + + + + + +

+Macros

HCP Packet Member Sizes

Macros for packet member sizes.

+
#define PACKET_ID_SIZE   sizeof(((fpc_hcp_packet_t*)0)->id)
 
#define PACKET_NUM_ARGS_SIZE   sizeof(((fpc_hcp_packet_t*)0)->num_args)
 
#define PACKET_HEADER_SIZE   (PACKET_ID_SIZE + PACKET_NUM_ARGS_SIZE)
 
HCP Argument Member Sizes

Macros for argument member sizes.

+
#define ARGUMENT_ARG_SIZE   sizeof(((fpc_hcp_arg_data_t*)0)->arg)
 
#define ARGUMENT_SIZE_SIZE   sizeof(((fpc_hcp_arg_data_t*)0)->size)
 
#define ARGUMENT_HEADER_SIZE   (ARGUMENT_ARG_SIZE + ARGUMENT_SIZE_SIZE)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

static fpc_com_result_t recieve_chunks (fpc_com_chain_t *chain)
 Handle receive chunks. More...
 
static fpc_com_result_t transmit_chunks (fpc_com_chain_t *chain)
 Handle transmit chunks. More...
 
uint16_t fpc_hcp_get_size (fpc_hcp_packet_t *packet, uint16_t *num_args)
 Calculate serialized packet size. More...
 
fpc_com_result_t fpc_hcp_transmit (fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
 Transmits an application packet through the supplied transmit chain. More...
 
fpc_com_result_t fpc_hcp_receive (fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
 Receives an application packet through the supplied transmit chain. More...
 
bool fpc_hcp_arg_add (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data, void *data)
 Add argument to packet. More...
 
bool fpc_hcp_arg_check (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
 Check if command contains selected argument key. More...
 
fpc_hcp_arg_data_t * fpc_hcp_arg_get (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
 Get Argument with specified key. More...
 
bool fpc_hcp_arg_copy_data (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size, uint8_t *data)
 Copy data from an argument with specified key. More...
 
void fpc_hcp_free (fpc_com_chain_t *chain, fpc_hcp_packet_t *packet)
 Frees the resources held by the packet i.e. the dynamic data held in the arguments. More...
 
+

Detailed Description

+

Host Communication Protocol implementation.

+ +

Definition in file fpc_hcp.c.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ARGUMENT_ARG_SIZE   sizeof(((fpc_hcp_arg_data_t*)0)->arg)
+
+ +

Definition at line 44 of file fpc_hcp.c.

+ +
+
+ +
+
+ + + + +
#define ARGUMENT_HEADER_SIZE   (ARGUMENT_ARG_SIZE + ARGUMENT_SIZE_SIZE)
+
+ +

Definition at line 46 of file fpc_hcp.c.

+ +
+
+ +
+
+ + + + +
#define ARGUMENT_SIZE_SIZE   sizeof(((fpc_hcp_arg_data_t*)0)->size)
+
+ +

Definition at line 45 of file fpc_hcp.c.

+ +
+
+ +
+
+ + + + +
#define PACKET_HEADER_SIZE   (PACKET_ID_SIZE + PACKET_NUM_ARGS_SIZE)
+
+ +

Definition at line 35 of file fpc_hcp.c.

+ +
+
+ +
+
+ + + + +
#define PACKET_ID_SIZE   sizeof(((fpc_hcp_packet_t*)0)->id)
+
+ +

Definition at line 33 of file fpc_hcp.c.

+ +
+
+ +
+
+ + + + +
#define PACKET_NUM_ARGS_SIZE   sizeof(((fpc_hcp_packet_t*)0)->num_args)
+
+ +

Definition at line 34 of file fpc_hcp.c.

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bool fpc_hcp_arg_add (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg,
uint16_t size,
bool free_data,
void * data 
)
+
+ +

Add argument to packet.

+
Note
This function does not allocate any memory, it will only set the argument variables.
+
Parameters
+ + + + + + +
[in]packetPacket to add to.
[in]argArgument id.
[in]sizeSize of argument data.
[in]free_dataSet to true if data should be owned by the argument, false if user still owns data.
[in]dataPointer to argument data.
+
+
+
Returns
true = success, false = failure.
+ +

Definition at line 145 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, fpc_hcp_packet::arguments, fpc_hcp_arg_data::data, fpc_hcp_arg_data::free_data, fpc_hcp_packet::num_args, and fpc_hcp_arg_data::size.

+ +
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+ +
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+ + + + + + + + + + + + + + + + + + +
bool fpc_hcp_arg_check (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg 
)
+
+ +

Check if command contains selected argument key.

+
Parameters
+ + + +
[in]packetThe packet to scan.
[in]argArgument to look for.
+
+
+
Returns
true if found, false if not found.
+ +

Definition at line 169 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_get().

+ +

+Here is the call graph for this function:
+
+
+
+
+

+ +
+
+ +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bool fpc_hcp_arg_copy_data (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg,
uint16_t data_size,
uint8_t * data 
)
+
+ +

Copy data from an argument with specified key.

+

Argument data will be copied to specified data buffer. Remaining bytes in data will be cleared if the argument data size is less than data size when the argument contains data.

+
Parameters
+ + + + + +
[in]packetThe packet to operate on.
[in]argThe arg to retrieve data from.
[in]data_sizeNumber of bytes to copy.
[in,out]dataPointer to data buffer.
+
+
+
Returns
True if argument found, false if not found.
+ +

Definition at line 183 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::data, fpc_hcp_arg_get(), and fpc_hcp_arg_data::size.

+ +

+Here is the call graph for this function:
+
+
+
+
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_hcp_arg_data_t* fpc_hcp_arg_get (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg 
)
+
+ +

Get Argument with specified key.

+
Parameters
+ + + +
[in]packetThe packet to operate on.
[in]argThe arg to retrieve.
+
+
+
Returns
Pointer to fpc_hcp_arg_data_t is successful, otherwise NULL.
+ +

Definition at line 173 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, fpc_hcp_packet::arguments, and fpc_hcp_packet::num_args.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void fpc_hcp_free (fpc_com_chain_t * chain,
fpc_hcp_packet_t * packet 
)
+
+ +

Frees the resources held by the packet i.e. the dynamic data held in the arguments.

+
Parameters
+ + + +
[in]chainPointer to the communication chain used to retrieve the packet.
[in]packetPointer to packet.
+
+
+ +

Definition at line 198 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, fpc_com_chain::argument_free, fpc_hcp_packet::arguments, CMD_NONE, fpc_com_chain::context, fpc_hcp_packet::id, and fpc_hcp_packet::num_args.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint16_t fpc_hcp_get_size (fpc_hcp_packet_t * packet,
uint16_t * num_args 
)
+
+ +

Calculate serialized packet size.

+
Parameters
+ + + +
[in]packetPacket to calculate.
[in,out]num_argsWill return number of arguments held by the command can be set to NULL.
+
+
+
Returns
Serialized size.
+ +

Definition at line 64 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, ARGUMENT_HEADER_SIZE, fpc_hcp_packet::arguments, fpc_hcp_packet::num_args, PACKET_HEADER_SIZE, and fpc_hcp_arg_data::size.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_hcp_receive (fpc_hcp_packet_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receives an application packet through the supplied transmit chain.

+
Parameters
+ + + +
[in,out]packetPointer to pre-allocated packet struct.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 117 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, FPC_COM_CHAIN_RX, FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain_private::hcp_packet, fpc_com_chain::initialized, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::private_vars, recieve_chunks(), and fpc_com_chain::tsp_overhead_get.

+ +

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+
+
+
+
+

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
fpc_com_result_t fpc_hcp_transmit (fpc_hcp_packet_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Transmits an application packet through the supplied transmit chain.

+
Parameters
+ + + +
[in]packetApplication packet to send.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 89 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, FPC_COM_CHAIN_TX, FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain_private::hcp_packet, fpc_com_chain::initialized, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::private_vars, transmit_chunks(), and fpc_com_chain::tsp_overhead_get.

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+
+
+

+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static fpc_com_result_t recieve_chunks (fpc_com_chain_t * chain)
+ 		+static
+
+ +

Handle receive chunks.

+
Parameters
+ + +
chainComminucation chain. return fpc_com_result_t
+
+
+ +

Definition at line 211 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, fpc_com_chain::app_overhead_get, fpc_com_chain::app_packet_size, fpc_com_chain::app_rx, fpc_hcp_arg_data::arg, fpc_com_chain::argument_allocator, ARGUMENT_ARG_SIZE, fpc_com_chain::argument_free, ARGUMENT_SIZE_SIZE, fpc_com_chain::context, fpc_hcp_arg_data::data, FPC_COM_CHAIN_RX, FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_NO_MEMORY, FPC_COM_RESULT_OK, fpc_hcp_arg_add(), fpc_hcp_arg_data::free_data, HCP_MIN, fpc_com_chain_private::hcp_packet, fpc_hcp_packet::id, PACKET_HEADER_SIZE, PACKET_ID_SIZE, PACKET_NUM_ARGS_SIZE, fpc_com_chain::private_vars, and fpc_hcp_arg_data::size.

+ +

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+ +
+
+ +
+
+ + + + + +
+ + + + + + + + +
static fpc_com_result_t transmit_chunks (fpc_com_chain_t * chain)
+ 		+static
+
+ +

Handle transmit chunks.

+
Parameters
+ + +
chainComminucation chain. return fpc_com_result_t
+
+
+ +

Definition at line 355 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, fpc_com_chain::app_overhead_get, fpc_com_chain::app_packet_size, fpc_com_chain::app_tx, fpc_hcp_arg_data::arg, ARGUMENT_ARG_SIZE, ARGUMENT_HEADER_SIZE, ARGUMENT_SIZE_SIZE, fpc_hcp_packet::arguments, fpc_hcp_arg_data::data, FPC_COM_CHAIN_TX, FPC_COM_RESULT_INVALID_ARGUMENT, FPC_COM_RESULT_OK, fpc_hcp_get_size(), HCP_MIN, fpc_com_chain_private::hcp_packet, fpc_com_chain_private::hcp_seq_len, fpc_com_chain_private::hcp_seq_nr, fpc_hcp_packet::id, PACKET_HEADER_SIZE, PACKET_ID_SIZE, PACKET_NUM_ARGS_SIZE, fpc_com_chain::phy_mtu_size, fpc_com_chain::private_vars, and fpc_hcp_arg_data::size.

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+ +
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+ + + + diff --git a/hcp/doxygen/html/fpc__hcp_8c.js b/hcp/doxygen/html/fpc__hcp_8c.js new file mode 100644 index 0000000..2b0ac49 --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp_8c.js @@ -0,0 +1,19 @@ +var fpc__hcp_8c = +[ + [ "ARGUMENT_ARG_SIZE", "fpc__hcp_8c.html#a119829b571e80de1f9f2b2841e32fa42", null ], + [ "ARGUMENT_HEADER_SIZE", "fpc__hcp_8c.html#a3496d79780b19b71442831ff927f540b", null ], + [ "ARGUMENT_SIZE_SIZE", "fpc__hcp_8c.html#aa5d90c20e4e2341e40b371741f9f12c9", null ], + [ "PACKET_HEADER_SIZE", "fpc__hcp_8c.html#a69bfb6e73bae0625ac56f441ccf542d1", null ], + [ "PACKET_ID_SIZE", "fpc__hcp_8c.html#a6eac0136b31c600d0077de19003a0fb2", null ], + [ "PACKET_NUM_ARGS_SIZE", "fpc__hcp_8c.html#aeff07e75eb0e6cc94982a68ddb4adbd4", null ], + [ "fpc_hcp_arg_add", "fpc__hcp_8c.html#a9b6886d13174fd6e88bd673ba09cca7d", null ], + [ "fpc_hcp_arg_check", "fpc__hcp_8c.html#ae1b7ce8b198acf7c8f6802300e2591ea", null ], + [ "fpc_hcp_arg_copy_data", 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/dev/null +++ b/hcp/doxygen/html/fpc__hcp_8c_ae1b7ce8b198acf7c8f6802300e2591ea_cgraph.svg @@ -0,0 +1,31 @@ + + + + + + +fpc_hcp_arg_check + + +Node1 + +fpc_hcp_arg_check + + +Node2 + + +fpc_hcp_arg_get + + + + +Node1->Node2 + + + + + diff --git a/hcp/doxygen/html/fpc__hcp_8c_source.html b/hcp/doxygen/html/fpc__hcp_8c_source.html new file mode 100644 index 0000000..2e48205 --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp_8c_source.html @@ -0,0 +1,140 @@ + + + + + + +Host Communication Protocol: src/fpc_hcp.c Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_hcp.c
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #include <stdlib.h>
23 #include <string.h>
24 
25 #include "fpc_hcp.h"
26 
33 #define PACKET_ID_SIZE sizeof(((fpc_hcp_packet_t*)0)->id)
34 #define PACKET_NUM_ARGS_SIZE sizeof(((fpc_hcp_packet_t*)0)->num_args)
35 #define PACKET_HEADER_SIZE (PACKET_ID_SIZE + PACKET_NUM_ARGS_SIZE)
36 
44 #define ARGUMENT_ARG_SIZE sizeof(((fpc_hcp_arg_data_t*)0)->arg)
45 #define ARGUMENT_SIZE_SIZE sizeof(((fpc_hcp_arg_data_t*)0)->size)
46 #define ARGUMENT_HEADER_SIZE (ARGUMENT_ARG_SIZE + ARGUMENT_SIZE_SIZE)
47 
55 static fpc_com_result_t recieve_chunks(fpc_com_chain_t *chain);
62 static fpc_com_result_t transmit_chunks(fpc_com_chain_t *chain);
63 
64 uint16_t fpc_hcp_get_size(fpc_hcp_packet_t *packet, uint16_t *num_args)
65 {
66  uint16_t size = 0;
67  uint16_t args = 0;
68 
69  if (packet == NULL) {
70  goto exit;
71  }
72  size = PACKET_HEADER_SIZE;
73 
74  for (uint8_t i = 0; i < packet->num_args; i++) {
75  if (packet->arguments[i].arg != ARG_NONE) {
76  size += ARGUMENT_HEADER_SIZE;
77  size += packet->arguments[i].size;
78  args++;
79  }
80  }
81  if (num_args) {
82  *num_args = args;
83  }
84 
85 exit:
86  return size;
87 }
88 
89 fpc_com_result_t fpc_hcp_transmit(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
90 {
91  fpc_com_result_t result;
92 
93  if (chain == NULL || packet == NULL || chain->initialized == false ||
94  chain->phy_mtu_buffer[FPC_COM_CHAIN_TX] == NULL) {
95  result = FPC_COM_RESULT_INVALID_ARGUMENT;
96  goto exit;
97  }
98  chain->private_vars.hcp_packet = packet;
99 
100  if (chain->app_mtu_size[FPC_COM_CHAIN_TX] == 0 ||
101  chain->app_mtu_buffer[FPC_COM_CHAIN_TX] == NULL) {
102  uint16_t tsp_offset;
103  uint16_t link_offset;
104  uint16_t overhead;
105 
106  overhead = chain->tsp_overhead_get(&tsp_offset) + chain->link_overhead_get(&link_offset);
107  chain->app_mtu_buffer[FPC_COM_CHAIN_TX] = chain->phy_mtu_buffer[FPC_COM_CHAIN_TX]
108  + tsp_offset + link_offset;
109  chain->app_mtu_size[FPC_COM_CHAIN_TX] = chain->phy_mtu_size[FPC_COM_CHAIN_TX] - overhead;
110  }
111  result = transmit_chunks(chain);
112 
113 exit:
114  return result;
115 }
116 
117 fpc_com_result_t fpc_hcp_receive(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
118 {
119  fpc_com_result_t result;
120 
121  if (chain == NULL || packet == NULL || chain->initialized == false ||
122  chain->phy_mtu_buffer[FPC_COM_CHAIN_RX] == NULL) {
123  result = FPC_COM_RESULT_INVALID_ARGUMENT;
124  goto exit;
125  }
126  chain->private_vars.hcp_packet = packet;
127 
128  if (chain->app_mtu_size[FPC_COM_CHAIN_RX] == 0 ||
129  chain->app_mtu_buffer[FPC_COM_CHAIN_RX] == NULL) {
130  uint16_t tsp_offset;
131  uint16_t link_offset;
132  uint16_t overhead;
133 
134  overhead = chain->tsp_overhead_get(&tsp_offset) + chain->link_overhead_get(&link_offset);
135  chain->app_mtu_buffer[FPC_COM_CHAIN_RX] = chain->phy_mtu_buffer[FPC_COM_CHAIN_RX]
136  + tsp_offset + link_offset;
137  chain->app_mtu_size[FPC_COM_CHAIN_RX] = chain->phy_mtu_size[FPC_COM_CHAIN_RX] - overhead;
138  }
139  result = recieve_chunks(chain);
140 
141 exit:
142  return result;
143 }
144 
145 bool fpc_hcp_arg_add(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data,
146  void *data)
147 {
148  bool result = false;
149 
150  if (packet == NULL || (size > 0 && data == NULL)) {
151  goto exit;
152  }
153 
154  for (uint8_t i = 0; i < packet->num_args; i++) {
155  if (packet->arguments[i].arg == ARG_NONE) {
156  packet->arguments[i].arg = arg;
157  packet->arguments[i].size = size;
158  packet->arguments[i].free_data = free_data;
159  packet->arguments[i].data = data;
160  result = true;
161  break;
162  }
163  }
164 
165 exit:
166  return result;
167 }
168 
169 bool fpc_hcp_arg_check(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg) {
170  return fpc_hcp_arg_get(packet, arg) != NULL;
171 }
172 
173 fpc_hcp_arg_data_t *fpc_hcp_arg_get(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
174 {
175  for (uint8_t i = 0; i < packet->num_args; i++) {
176  if (packet->arguments[i].arg == arg) {
177  return &(packet->arguments[i]);
178  }
179  }
180  return NULL;
181 }
182 
183 bool fpc_hcp_arg_copy_data(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size,
184  uint8_t *data)
185 {
186  fpc_hcp_arg_data_t *arg_data = fpc_hcp_arg_get(packet, arg);
187 
188  if (arg_data == NULL || data == NULL || data_size == 0 || arg_data->size == 0
189  || data_size > arg_data->size) {
190  return false;
191  }
192 
193  memcpy(data, arg_data->data, data_size);
194 
195  return true;
196 }
197 
198 void fpc_hcp_free(fpc_com_chain_t *chain, fpc_hcp_packet_t *packet)
199 {
200  if (chain && packet) {
201  for (uint8_t i = 0; i < packet->num_args; i++) {
202  if (packet->arguments[i].arg != ARG_NONE) {
203  chain->argument_free(packet->id, &packet->arguments[i], chain->context);
204  }
205  }
206  memset(packet->arguments, 0x0, sizeof(*packet->arguments) * packet->num_args);
207  packet->id = CMD_NONE;
208  }
209 }
210 
211 static fpc_com_result_t recieve_chunks(fpc_com_chain_t *chain)
212 {
213  uint8_t *data;
214  uint16_t rem_size;
215  uint16_t id_rem_size;
216  uint16_t size_rem_size;
217  uint16_t arg_rem_size = 0;
218  uint16_t arg_size;
219  uint8_t *arg_data = NULL;
220  uint16_t overhead;
221  uint16_t arg_nr = 0;
222  uint16_t num_args = 0;
223  fpc_com_result_t result;
224  bool first_packet = true;
225  fpc_hcp_arg_t arg;
226  uint16_t app_offset;
227 
228  /* Calculate application packet data MTU size */
229  overhead = chain->app_overhead_get(&app_offset);
230  if (overhead > chain->app_mtu_size[FPC_COM_CHAIN_RX]) {
231  result = FPC_COM_RESULT_INVALID_ARGUMENT;
232  goto exit;
233  }
234 
235  /* Retrieve application packets */
236  do {
237  /* Get packet from application layer */
238  result = chain->app_rx(chain);
239  if (result != FPC_COM_RESULT_OK) {
240  break;
241  }
242 
243  /* Get packet size */
244  rem_size = chain->app_packet_size[FPC_COM_CHAIN_RX];
245  data = chain->app_mtu_buffer[FPC_COM_CHAIN_RX] + app_offset;
246 
247  if (first_packet) {
248  /* ID */
249  chain->private_vars.hcp_packet->id = *((uint16_t *) data);
250  data += PACKET_ID_SIZE;
251 
252  /* Number of arguments */
253  num_args = *((uint16_t *) data);
254  data += PACKET_NUM_ARGS_SIZE;
255 
256  first_packet = false;
257  rem_size -= PACKET_HEADER_SIZE;
258  id_rem_size = ARGUMENT_ARG_SIZE;
259  size_rem_size = ARGUMENT_SIZE_SIZE;
260  }
261 
262  while (rem_size && (arg_nr < num_args)) {
263  uint16_t copy_size;
264 
265  if (rem_size && id_rem_size) {
266  /* Set copy size */
267  copy_size = HCP_MIN(id_rem_size, rem_size);
268 
269  /* Copy arg id */
270  memcpy(((uint8_t *) &arg) + (ARGUMENT_ARG_SIZE - id_rem_size), data, copy_size);
271  data += copy_size;
272 
273  /* Update parameters */
274  id_rem_size -= copy_size;
275  rem_size -= copy_size;
276  }
277 
278  if (rem_size && size_rem_size) {
279  bool status;
280 
281  /* Set copy size */
282  copy_size = HCP_MIN(size_rem_size, rem_size);
283 
284  /* Copy arg size */
285  memcpy(((uint8_t *) &arg_size) + (ARGUMENT_SIZE_SIZE - size_rem_size),
286  data, copy_size);
287  data += copy_size;
288 
289  /* Update parameters */
290  size_rem_size -= copy_size;
291  rem_size -= copy_size;
292 
293  if (size_rem_size == 0) {
294  bool free_data = true;
295 
296  if (arg_size) {
297  arg_data = chain->argument_allocator(chain->private_vars.hcp_packet->id,
298  arg, arg_size, &free_data, chain->context);
299  if (arg_data == NULL) {
300  result = FPC_COM_RESULT_NO_MEMORY;
301  break;
302  }
303  }
304 
305  status = fpc_hcp_arg_add(chain->private_vars.hcp_packet, arg, arg_size,
306  free_data, arg_data);
307  if (status == false) {
308  fpc_hcp_arg_data_t arg_struct = { 0 };
309 
310  arg_struct.arg = arg;
311  arg_struct.free_data = free_data;
312  arg_struct.size = arg_size;
313  arg_struct.data = arg_data;
314  chain->argument_free(chain->private_vars.hcp_packet->id, &arg_struct,
315  chain->context);
316 
317  if (arg_nr < num_args) {
318  result = FPC_COM_RESULT_INVALID_ARGUMENT;
319  break;
320  } else {
321  result = FPC_COM_RESULT_NO_MEMORY;
322  break;
323  }
324  }
325  arg_rem_size = arg_size;
326  }
327  }
328 
329  if (rem_size && arg_rem_size) {
330  /* Set copy size */
331  copy_size = HCP_MIN(arg_rem_size, rem_size);
332 
333  /* Copy argument data */
334  memcpy(arg_data + (arg_size - arg_rem_size), data, copy_size);
335  data += copy_size;
336 
337  /* Update parameters */
338  rem_size -= copy_size;
339  arg_rem_size -= copy_size;
340  }
341 
342  /* If data has been copied set new arg to true */
343  if (id_rem_size == 0 && size_rem_size == 0 && arg_rem_size == 0) {
344  id_rem_size = ARGUMENT_ARG_SIZE;
345  size_rem_size = ARGUMENT_SIZE_SIZE;
346  arg_nr++;
347  }
348  }
349  } while (result == FPC_COM_RESULT_OK && arg_nr < num_args);
350 
351 exit:
352  return result;
353 }
354 
355 static fpc_com_result_t transmit_chunks(fpc_com_chain_t *chain)
356 {
357  uint16_t serialized_size;
358  uint16_t packet_data_left;
359  uint16_t data_rem_size = 0;
360  uint16_t app_mtu;
361  uint16_t overhead;
362  fpc_com_result_t result;
363  uint16_t num_args = 0;
364  uint16_t arg_nr = 0;
365  uint16_t app_offset;
366  uint8_t *data;
367  fpc_hcp_arg_data_t *arg_data = NULL;
368 
369 
370  /* Calculate transport packet data MTU size */
371  overhead = chain->app_overhead_get(&app_offset);
372  if (overhead > chain->phy_mtu_size[FPC_COM_CHAIN_TX]) {
373  result = FPC_COM_RESULT_INVALID_ARGUMENT;
374  goto exit;
375  }
376  app_mtu = chain->app_mtu_size[FPC_COM_CHAIN_TX] - overhead;
377 
378  /* Get application packet total serialized size */
379  serialized_size = fpc_hcp_get_size(chain->private_vars.hcp_packet, &num_args);
380 
381  /* Set initial sequence length and size */
382  /* Calculate sequence length (number of application packages) */
383  chain->private_vars.hcp_seq_len = (serialized_size + app_mtu + 1) / app_mtu;
384  chain->private_vars.hcp_seq_nr = 1;
385 
386  /* Set first packet size */
387  chain->app_packet_size[FPC_COM_CHAIN_TX] = HCP_MIN(serialized_size, app_mtu);
388  packet_data_left = chain->app_packet_size[FPC_COM_CHAIN_TX];
389 
390  /* Point packet data to application buffer */
391  data = chain->app_mtu_buffer[FPC_COM_CHAIN_TX] + app_offset;
392 
393  /* Copy command ID to buffer */
394  *((fpc_hcp_cmd_t *) data) = chain->private_vars.hcp_packet->id;
395  data += PACKET_ID_SIZE;
396 
397  /* Copy number of arguments to buffer */
398  *((uint16_t *) data) = num_args;
399  data += PACKET_NUM_ARGS_SIZE;
400 
401  packet_data_left -= PACKET_HEADER_SIZE;
402 
403  do {
404  /* Copy arguments to data blob */
405  while (packet_data_left && arg_nr < num_args) {
406  /* Copy arg header to buffer */
407  if (!data_rem_size && packet_data_left >= ARGUMENT_HEADER_SIZE) {
408  /* Get current argument */
409  arg_data = &chain->private_vars.hcp_packet->arguments[arg_nr];
410 
411  /* Copy argument id */
412  memcpy(data, &arg_data->arg, ARGUMENT_ARG_SIZE);
413  data += ARGUMENT_ARG_SIZE;
414 
415  /* Copy argument size */
416  memcpy(data, &arg_data->size, ARGUMENT_SIZE_SIZE);
417  data += ARGUMENT_SIZE_SIZE;
418 
419  /* Update parameters */
420  packet_data_left -= ARGUMENT_HEADER_SIZE;
421  data_rem_size = arg_data->size;
422  } else if (!data_rem_size && packet_data_left < ARGUMENT_HEADER_SIZE) {
423  /*
424  * Special case to ensure that the argument header
425  * is not split over several packets as that will break the
426  * argument allocator.
427  */
428  chain->app_packet_size[FPC_COM_CHAIN_TX] -= packet_data_left;
429  break;
430  }
431 
432  /* Copy argument data to transport package data blob */
433  if (packet_data_left && data_rem_size) {
434  uint16_t copy_size;
435 
436  /* Set copy size */
437  copy_size = HCP_MIN(data_rem_size, packet_data_left);
438 
439  /* Copy argument data */
440  memcpy(data, arg_data->data + (arg_data->size - data_rem_size), copy_size);
441  data += copy_size;
442 
443  /* Update parameters */
444  data_rem_size -= copy_size;
445  packet_data_left -= copy_size;
446  }
447  if (!data_rem_size) {
448  arg_nr++;
449  }
450  }
451 
452  /* Transmit transport package */
453  result = chain->app_tx(chain);
454 
455  chain->private_vars.hcp_seq_nr++;
456 
457  /* Reduce data left counter */
458  serialized_size -= chain->app_packet_size[FPC_COM_CHAIN_TX];
459 
460  /* Set next packet size */
461  packet_data_left = HCP_MIN(serialized_size, app_mtu);
462  chain->app_packet_size[FPC_COM_CHAIN_TX] = packet_data_left;
463 
464  /* Set destination offset to zero for next packet */
465  data = chain->app_mtu_buffer[FPC_COM_CHAIN_TX] + app_offset;
466  } while (result == FPC_COM_RESULT_OK && serialized_size);
467 
468 exit:
469  return result;
470 }
fpc_hcp_packet::num_args
uint16_t num_args
Definition: fpc_hcp_common.h:214
+
fpc_hcp_cmd_t
uint16_t fpc_hcp_cmd_t
Definition: fpc_hcp_common.h:92
+
fpc_com_chain_private::hcp_seq_len
uint16_t hcp_seq_len
Definition: fpc_com_chain.h:40
+
fpc_com_chain::tsp_overhead_get
uint16_t(* tsp_overhead_get)(uint16_t *offset)
Definition: fpc_com_chain.h:95
+
fpc_com_chain::app_tx
fpc_com_result_t(* app_tx)(fpc_com_chain_t *chain)
Definition: fpc_com_chain.h:73
+
fpc_com_chain::phy_mtu_buffer
uint8_t * phy_mtu_buffer[2]
Definition: fpc_com_chain.h:121
+
recieve_chunks
static fpc_com_result_t recieve_chunks(fpc_com_chain_t *chain)
Handle receive chunks.
Definition: fpc_hcp.c:211
+
fpc_com_chain::app_overhead_get
uint16_t(* app_overhead_get)(uint16_t *offset)
Definition: fpc_com_chain.h:77
+
fpc_com_chain::phy_mtu_size
uint16_t phy_mtu_size[2]
Definition: fpc_com_chain.h:119
+
fpc_com_chain
Definition: fpc_com_chain.h:50
+
fpc_hcp_arg_data::size
uint16_t size
Definition: fpc_hcp_common.h:200
+
ARGUMENT_HEADER_SIZE
#define ARGUMENT_HEADER_SIZE
Definition: fpc_hcp.c:46
+
fpc_hcp_arg_check
bool fpc_hcp_arg_check(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
Check if command contains selected argument key.
Definition: fpc_hcp.c:169
+
CMD_NONE
Definition: fpc_hcp_common.h:43
+
fpc_hcp_arg_data::data
uint8_t * data
Definition: fpc_hcp_common.h:204
+
FPC_COM_CHAIN_TX
Definition: fpc_com_chain.h:150
+
fpc_hcp_arg_data::free_data
bool free_data
Definition: fpc_hcp_common.h:202
+
fpc_hcp_packet
Application Command Packet.
Definition: fpc_hcp_common.h:210
+
HCP_MIN
#define HCP_MIN(x, y)
Definition: fpc_hcp_common.h:33
+
fpc_com_chain::app_mtu_size
uint16_t app_mtu_size[2]
Definition: fpc_com_chain.h:81
+
fpc_hcp_arg_copy_data
bool fpc_hcp_arg_copy_data(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size, uint8_t *data)
Copy data from an argument with specified key.
Definition: fpc_hcp.c:183
+
fpc_hcp_packet::id
fpc_hcp_cmd_t id
Definition: fpc_hcp_common.h:212
+
fpc_com_chain::argument_allocator
void *(* argument_allocator)(fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size, bool *free_data, void *context)
Definition: fpc_com_chain.h:59
+
transmit_chunks
static fpc_com_result_t transmit_chunks(fpc_com_chain_t *chain)
Handle transmit chunks.
Definition: fpc_hcp.c:355
+
PACKET_HEADER_SIZE
#define PACKET_HEADER_SIZE
Definition: fpc_hcp.c:35
+
fpc_hcp_arg_get
fpc_hcp_arg_data_t * fpc_hcp_arg_get(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
Get Argument with specified key.
Definition: fpc_hcp.c:173
+
fpc_com_chain::context
void * context
User context pointer. User private stuff, to be able to pass nessecary context to argument_allocator ...
Definition: fpc_com_chain.h:143
+
FPC_COM_RESULT_INVALID_ARGUMENT
Definition: fpc_com_result.h:35
+
fpc_com_chain::argument_free
void(* argument_free)(fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, void *context)
Definition: fpc_com_chain.h:62
+
PACKET_NUM_ARGS_SIZE
#define PACKET_NUM_ARGS_SIZE
Definition: fpc_hcp.c:34
+
fpc_hcp_arg_data
Command Argument.
Definition: fpc_hcp_common.h:196
+
fpc_com_chain::initialized
bool initialized
Definition: fpc_com_chain.h:52
+
ARGUMENT_ARG_SIZE
#define ARGUMENT_ARG_SIZE
Definition: fpc_hcp.c:44
+
fpc_hcp_arg_add
bool fpc_hcp_arg_add(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data, void *data)
Add argument to packet.
Definition: fpc_hcp.c:145
+
fpc_hcp_transmit
fpc_com_result_t fpc_hcp_transmit(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
Transmits an application packet through the supplied transmit chain.
Definition: fpc_hcp.c:89
+
ARG_NONE
Definition: fpc_hcp_common.h:96
+
fpc_com_chain::app_packet_size
uint16_t app_packet_size[2]
Definition: fpc_com_chain.h:79
+
fpc_com_chain::app_mtu_buffer
uint8_t * app_mtu_buffer[2]
Definition: fpc_com_chain.h:83
+
FPC_COM_CHAIN_RX
Definition: fpc_com_chain.h:151
+
fpc_hcp_arg_t
uint16_t fpc_hcp_arg_t
Definition: fpc_hcp_common.h:191
+
fpc_com_chain::link_overhead_get
uint16_t(* link_overhead_get)(uint16_t *offset)
Definition: fpc_com_chain.h:103
+
PACKET_ID_SIZE
#define PACKET_ID_SIZE
Definition: fpc_hcp.c:33
+
fpc_hcp_packet::arguments
fpc_hcp_arg_data_t * arguments
Definition: fpc_hcp_common.h:216
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_com_chain_private::hcp_packet
fpc_hcp_packet_t * hcp_packet
Definition: fpc_com_chain.h:38
+
fpc_com_chain::private_vars
fpc_com_chain_private_t private_vars
Definition: fpc_com_chain.h:129
+
fpc_hcp_get_size
uint16_t fpc_hcp_get_size(fpc_hcp_packet_t *packet, uint16_t *num_args)
Calculate serialized packet size.
Definition: fpc_hcp.c:64
+
FPC_COM_RESULT_NO_MEMORY
Definition: fpc_com_result.h:34
+
fpc_hcp_receive
fpc_com_result_t fpc_hcp_receive(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
Receives an application packet through the supplied transmit chain.
Definition: fpc_hcp.c:117
+
fpc_hcp_arg_data::arg
fpc_hcp_arg_t arg
Definition: fpc_hcp_common.h:198
+
fpc_hcp.h
Host Communication Protocol interface.
+
FPC_COM_RESULT_OK
Definition: fpc_com_result.h:33
+
ARGUMENT_SIZE_SIZE
#define ARGUMENT_SIZE_SIZE
Definition: fpc_hcp.c:45
+
fpc_hcp_free
void fpc_hcp_free(fpc_com_chain_t *chain, fpc_hcp_packet_t *packet)
Frees the resources held by the packet i.e. the dynamic data held in the arguments.
Definition: fpc_hcp.c:198
+
fpc_com_chain::app_rx
fpc_com_result_t(* app_rx)(fpc_com_chain_t *chain)
Definition: fpc_com_chain.h:75
+
fpc_com_chain_private::hcp_seq_nr
uint16_t hcp_seq_nr
Definition: fpc_com_chain.h:42
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__hcp_8h.html b/hcp/doxygen/html/fpc__hcp_8h.html new file mode 100644 index 0000000..8b503ba --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp_8h.html @@ -0,0 +1,528 @@ + + + + + + +Host Communication Protocol: inc/fpc_hcp.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
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+Functions
+
+
fpc_hcp.h File Reference
+
+
+ +

Host Communication Protocol interface. +More...

+
#include <stdbool.h>
+#include <stdint.h>
+#include "fpc_hcp_common.h"
+#include "fpc_com_chain.h"
+
+Include dependency graph for fpc_hcp.h:
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+This graph shows which files directly or indirectly include this file:
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Go to the source code of this file.

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+Functions

fpc_com_result_t fpc_hcp_transmit (fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
 Transmits an application packet through the supplied transmit chain. More...
 
fpc_com_result_t fpc_hcp_receive (fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
 Receives an application packet through the supplied transmit chain. More...
 
bool fpc_hcp_arg_add (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data, void *data)
 Add argument to packet. More...
 
bool fpc_hcp_arg_check (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
 Check if command contains selected argument key. More...
 
fpc_hcp_arg_data_t * fpc_hcp_arg_get (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
 Get Argument with specified key. More...
 
bool fpc_hcp_arg_copy_data (fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size, uint8_t *data)
 Copy data from an argument with specified key. More...
 
void fpc_hcp_free (fpc_com_chain_t *chain, fpc_hcp_packet_t *packet)
 Frees the resources held by the packet i.e. the dynamic data held in the arguments. More...
 
uint16_t fpc_hcp_get_size (fpc_hcp_packet_t *packet, uint16_t *num_args)
 Calculate serialized packet size. More...
 
+

Detailed Description

+

Host Communication Protocol interface.

+ +

Definition in file fpc_hcp.h.

+

Function Documentation

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bool fpc_hcp_arg_add (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg,
uint16_t size,
bool free_data,
void * data 
)
+
+ +

Add argument to packet.

+
Note
This function does not allocate any memory, it will only set the argument variables.
+
Parameters
+ + + + + + +
[in]packetPacket to add to.
[in]argArgument id.
[in]sizeSize of argument data.
[in]free_dataSet to true if data should be owned by the argument, false if user still owns data.
[in]dataPointer to argument data.
+
+
+
Returns
true = success, false = failure.
+ +

Definition at line 145 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, fpc_hcp_packet::arguments, fpc_hcp_arg_data::data, fpc_hcp_arg_data::free_data, fpc_hcp_packet::num_args, and fpc_hcp_arg_data::size.

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bool fpc_hcp_arg_check (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg 
)
+
+ +

Check if command contains selected argument key.

+
Parameters
+ + + +
[in]packetThe packet to scan.
[in]argArgument to look for.
+
+
+
Returns
true if found, false if not found.
+ +

Definition at line 169 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_get().

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bool fpc_hcp_arg_copy_data (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg,
uint16_t data_size,
uint8_t * data 
)
+
+ +

Copy data from an argument with specified key.

+

Argument data will be copied to specified data buffer. Remaining bytes in data will be cleared if the argument data size is less than data size when the argument contains data.

+
Parameters
+ + + + + +
[in]packetThe packet to operate on.
[in]argThe arg to retrieve data from.
[in]data_sizeNumber of bytes to copy.
[in,out]dataPointer to data buffer.
+
+
+
Returns
True if argument found, false if not found.
+ +

Definition at line 183 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::data, fpc_hcp_arg_get(), and fpc_hcp_arg_data::size.

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fpc_hcp_arg_data_t* fpc_hcp_arg_get (fpc_hcp_packet_t * packet,
fpc_hcp_arg_t arg 
)
+
+ +

Get Argument with specified key.

+
Parameters
+ + + +
[in]packetThe packet to operate on.
[in]argThe arg to retrieve.
+
+
+
Returns
Pointer to fpc_hcp_arg_data_t is successful, otherwise NULL.
+ +

Definition at line 173 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, fpc_hcp_packet::arguments, and fpc_hcp_packet::num_args.

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void fpc_hcp_free (fpc_com_chain_t * chain,
fpc_hcp_packet_t * packet 
)
+
+ +

Frees the resources held by the packet i.e. the dynamic data held in the arguments.

+
Parameters
+ + + +
[in]chainPointer to the communication chain used to retrieve the packet.
[in]packetPointer to packet.
+
+
+ +

Definition at line 198 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, fpc_com_chain::argument_free, fpc_hcp_packet::arguments, CMD_NONE, fpc_com_chain::context, fpc_hcp_packet::id, and fpc_hcp_packet::num_args.

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uint16_t fpc_hcp_get_size (fpc_hcp_packet_t * packet,
uint16_t * num_args 
)
+
+ +

Calculate serialized packet size.

+
Parameters
+ + + +
[in]packetPacket to calculate.
[in,out]num_argsWill return number of arguments held by the command can be set to NULL.
+
+
+
Returns
Serialized size.
+ +

Definition at line 64 of file fpc_hcp.c.

+ +

References fpc_hcp_arg_data::arg, ARG_NONE, ARGUMENT_HEADER_SIZE, fpc_hcp_packet::arguments, fpc_hcp_packet::num_args, PACKET_HEADER_SIZE, and fpc_hcp_arg_data::size.

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fpc_com_result_t fpc_hcp_receive (fpc_hcp_packet_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Receives an application packet through the supplied transmit chain.

+
Parameters
+ + + +
[in,out]packetPointer to pre-allocated packet struct.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 117 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, FPC_COM_CHAIN_RX, FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain_private::hcp_packet, fpc_com_chain::initialized, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::private_vars, recieve_chunks(), and fpc_com_chain::tsp_overhead_get.

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fpc_com_result_t fpc_hcp_transmit (fpc_hcp_packet_t * packet,
fpc_com_chain_t * chain 
)
+
+ +

Transmits an application packet through the supplied transmit chain.

+
Parameters
+ + + +
[in]packetApplication packet to send.
[in]chainThe chain to use.
+
+
+
Returns
fpc_com_result_t
+ +

Definition at line 89 of file fpc_hcp.c.

+ +

References fpc_com_chain::app_mtu_buffer, fpc_com_chain::app_mtu_size, FPC_COM_CHAIN_TX, FPC_COM_RESULT_INVALID_ARGUMENT, fpc_com_chain_private::hcp_packet, fpc_com_chain::initialized, fpc_com_chain::link_overhead_get, fpc_com_chain::phy_mtu_buffer, fpc_com_chain::phy_mtu_size, fpc_com_chain::private_vars, transmit_chunks(), and fpc_com_chain::tsp_overhead_get.

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b/hcp/doxygen/html/fpc__hcp_8h_source.html @@ -0,0 +1,99 @@ + + + + + + +Host Communication Protocol: inc/fpc_hcp.h Source File + + + + + + + + + + + +
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+
Host Communication Protocol +  2.0 +
+
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+ +
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+
fpc_hcp.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_HCP_H
23 #define FPC_HCP_H
24 
25 #include <stdbool.h>
26 #include <stdint.h>
27 
28 #include "fpc_hcp_common.h"
29 #include "fpc_com_chain.h"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif /* __cplusplus */
34 
42 fpc_com_result_t fpc_hcp_transmit(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain);
43 
51 fpc_com_result_t fpc_hcp_receive(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain);
52 
66 bool fpc_hcp_arg_add(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data,
67  void *data);
68 
76 bool fpc_hcp_arg_check(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg);
77 
85 fpc_hcp_arg_data_t *fpc_hcp_arg_get(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg);
86 
101 bool fpc_hcp_arg_copy_data(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size,
102  uint8_t *data);
103 
110 void fpc_hcp_free(fpc_com_chain_t *chain, fpc_hcp_packet_t *packet);
111 
119 uint16_t fpc_hcp_get_size(fpc_hcp_packet_t *packet, uint16_t *num_args);
120 
121 #ifdef __cplusplus
122 }
123 #endif /* __cplusplus */
124 
125 #endif /* FPC_HCP_H */
fpc_hcp_arg_check
bool fpc_hcp_arg_check(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
Check if command contains selected argument key.
Definition: fpc_hcp.c:169
+
fpc_com_chain
Definition: fpc_com_chain.h:50
+
fpc_hcp_packet
Application Command Packet.
Definition: fpc_hcp_common.h:210
+
fpc_hcp_arg_get
fpc_hcp_arg_data_t * fpc_hcp_arg_get(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg)
Get Argument with specified key.
Definition: fpc_hcp.c:173
+
fpc_com_chain.h
Communication chain type definitions.
+
fpc_hcp_arg_data
Command Argument.
Definition: fpc_hcp_common.h:196
+
fpc_hcp_arg_add
bool fpc_hcp_arg_add(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t size, bool free_data, void *data)
Add argument to packet.
Definition: fpc_hcp.c:145
+
fpc_hcp_receive
fpc_com_result_t fpc_hcp_receive(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
Receives an application packet through the supplied transmit chain.
Definition: fpc_hcp.c:117
+
fpc_hcp_arg_t
uint16_t fpc_hcp_arg_t
Definition: fpc_hcp_common.h:191
+
fpc_hcp_get_size
uint16_t fpc_hcp_get_size(fpc_hcp_packet_t *packet, uint16_t *num_args)
Calculate serialized packet size.
Definition: fpc_hcp.c:64
+
fpc_hcp_arg_copy_data
bool fpc_hcp_arg_copy_data(fpc_hcp_packet_t *packet, fpc_hcp_arg_t arg, uint16_t data_size, uint8_t *data)
Copy data from an argument with specified key.
Definition: fpc_hcp.c:183
+
fpc_hcp_transmit
fpc_com_result_t fpc_hcp_transmit(fpc_hcp_packet_t *packet, fpc_com_chain_t *chain)
Transmits an application packet through the supplied transmit chain.
Definition: fpc_hcp.c:89
+
fpc_com_result_t
uint8_t fpc_com_result_t
Definition: fpc_com_result.h:41
+
fpc_hcp_common.h
Host Communication Protocol common type definitions.
+
fpc_hcp_free
void fpc_hcp_free(fpc_com_chain_t *chain, fpc_hcp_packet_t *packet)
Frees the resources held by the packet i.e. the dynamic data held in the arguments.
Definition: fpc_hcp.c:198
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__hcp__common_8h.html b/hcp/doxygen/html/fpc__hcp__common_8h.html new file mode 100644 index 0000000..2d8c85e --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp__common_8h.html @@ -0,0 +1,691 @@ + + + + + + +Host Communication Protocol: inc/fpc_hcp_common.h File Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Structures | +Macros | +Typedefs | +Enumerations
+
+
fpc_hcp_common.h File Reference
+
+
+ +

Host Communication Protocol common type definitions. +More...

+
#include <stdint.h>
+#include <stdbool.h>
+
+Include dependency graph for fpc_hcp_common.h:
+
+
+
+
+
+This graph shows which files directly or indirectly include this file:
+
+
+
+
+
+

Go to the source code of this file.

+ + + + + + + + +

+Data Structures

struct  fpc_hcp_arg_data
 Command Argument. More...
 
struct  fpc_hcp_packet
 Application Command Packet. More...
 
+ + + + + + + +

+Macros

#define HCP_MIN(x, y)   (((x) < (y)) ? (x) : (y))
 
#define CMD_APP_BASE_VAL   0xE000
 
#define ARG_APP_BASE_VAL   0x7000
 
+ + + + + + + + + + + +

+Typedefs

typedef uint16_t fpc_hcp_cmd_t
 
typedef uint16_t fpc_hcp_arg_t
 
typedef struct fpc_hcp_arg_data fpc_hcp_arg_data_t
 Command Argument. More...
 
typedef struct fpc_hcp_packet fpc_hcp_packet_t
 Application Command Packet. More...
 
+ + + + + +

+Enumerations

enum  fpc_hcp_cmd {
+  CMD_NONE = 0x0000, +
+  CMD_CAPTURE = 0x0001, +
+  CMD_ENROLL = 0x0002, +
+  CMD_IDENTIFY = 0x0003, +
+  CMD_MATCH = 0x0004, +
+  CMD_IMAGE = 0x0005, +
+  CMD_TEMPLATE = 0x0006, +
+  CMD_WAIT = 0x0007, +
+  CMD_SETTINGS = 0x0008, +
+  CMD_NAVIGATE = 0x1001, +
+  CMD_SENSOR = 0x1002, +
+  CMD_DEADPIXELS = 0x1003, +
+  CMD_CONNECT = 0x2001, +
+  CMD_RECONNECT = 0x2002, +
+  CMD_RESET = 0x3002, +
+  CMD_CANCEL = 0x3003, +
+  CMD_INFO = 0x3004, +
+  CMD_STORAGE_TEMPLATE = 0x4002, +
+  CMD_STORAGE_CALIBRATION = 0x4003, +
+  CMD_STORAGE_LOG = 0x4004, +
+  CMD_STORAGE_SETTINGS = 0x4005, +
+  CMD_TEST = 0x5001, +
+  CMD_MCU = 0x5002, +
+  CMD_GPIO = 0x5003, +
+  CMD_COMMUNICATION = 0x6001, +
+  CMD_APP_BASE = CMD_APP_BASE_VAL, +
+  CMD_DIAG = 0xF003, +
+  CMD_FFFF = 0xFFFF +
+ }
 
enum  fpc_hcp_arg {
+  ARG_NONE = 0x0000, +
+  ARG_FINGER_DOWN = 0x0001, +
+  ARG_FINGER_UP = 0x0002, +
+  ARG_START = 0x0003, +
+  ARG_ADD = 0x0004, +
+  ARG_FINISH = 0x0005, +
+  ARG_ID = 0x0006, +
+  ARG_ALL = 0x0007, +
+  ARG_EXTRACT = 0x0008, +
+  ARG_MATCH_IMAGE = 0x0009, +
+  ARG_MATCH = 0x000A, +
+  ARG_ACQUIRE = 0x1001, +
+  ARG_RELEASE = 0x1002, +
+  ARG_SET = 0x1003, +
+  ARG_GET = 0x1004, +
+  ARG_UPLOAD = 0x1005, +
+  ARG_DOWNLOAD = 0x1006, +
+  ARG_CREATE = 0x1007, +
+  ARG_SAVE = 0x1008, +
+  ARG_DELETE = 0x1009, +
+  ARG_DATA = 0x100A, +
+  ARG_UPDATE = 0x100B, +
+  ARG_SEQ_NR = 0x100C, +
+  ARG_SEQ_LEN = 0x100D, +
+  ARG_RESULT = 0x2001, +
+  ARG_COUNT = 0x2002, +
+  ARG_SIZE = 0x2003, +
+  ARG_LEVEL = 0x2004, +
+  ARG_FORMAT = 0x2005, +
+  ARG_FLAG = 0x2006, +
+  ARG_PROPERTIES = 0x2007, +
+  ARG_SPEED = 0x2008, +
+  ARG_PROD_TEST = 0x2009, +
+  ARG_SENSOR_TYPE = 0x3001, +
+  ARG_WIDTH = 0x3002, +
+  ARG_HEIGHT = 0x3003, +
+  ARG_RESET = 0x3004, +
+  ARG_DPI = 0x3005, +
+  ARG_MAX_SPI_CLOCK = 0x3006, +
+  ARG_NUM_SUB_AREAS_WIDTH = 0x3007, +
+  ARG_NUM_SUB_AREAS_HEIGHT = 0x3008, +
+  ARG_IRQ_STATUS = 0x3009, +
+  ARG_RESET_HARD = 0x300A, +
+  ARG_IDLE = 0x4001, +
+  ARG_SLEEP = 0x4002, +
+  ARG_DEEP_SLEEP = 0x4003, +
+  ARG_POWER_MODE = 0x4004, +
+  ARG_BUSY_WAIT = 0x4005, +
+  ARG_TIMEOUT = 0x5001, +
+  ARG_DONE = 0x5002, +
+  ARG_BOOT = 0x6001, +
+  ARG_STATUS = 0x6002, +
+  ARG_VERSION = 0x6003, +
+  ARG_UNIQUE_ID = 0x6004, +
+  ARG_APP_BASE = ARG_APP_BASE_VAL, +
+  ARG_NONCE = 0x8001, +
+  ARG_MAC = 0x8002, +
+  ARG_RANDOM = 0x8003, +
+  ARG_CLAIM = 0x8004, +
+  ARG_PUBLIC_KEY = 0x8005, +
+  ARG_CIPHERTEXT = 0x8006, +
+  ARG_MTU = 0x9001, +
+  ARG_STACK = 0xE001, +
+  ARG_FILL = 0xE002, +
+  ARG_HEAP = 0xE003, +
+  ARG_MODE = 0xF001, +
+  ARG_DEBUG = 0xF002, +
+  ARG_FFFF = 0xFFFF +
+ }
 
+

Detailed Description

+

Host Communication Protocol common type definitions.

+ +

Definition in file fpc_hcp_common.h.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ARG_APP_BASE_VAL   0x7000
+
+

Program specific arguments base number

+ +

Definition at line 39 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
#define CMD_APP_BASE_VAL   0xE000
+
+

Program specific commands base number

+ +

Definition at line 36 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define HCP_MIN( x,
 y 
)   (((x) < (y)) ? (x) : (y))
+
+

Returns the smallest of two values.

+ +

Definition at line 33 of file fpc_hcp_common.h.

+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef struct fpc_hcp_arg_data fpc_hcp_arg_data_t
+
+ +

Command Argument.

+ +
+
+ +
+
+ + + + +
typedef uint16_t fpc_hcp_arg_t
+
+

HCP Argument type

+ +

Definition at line 191 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
typedef uint16_t fpc_hcp_cmd_t
+
+

HCP Command type

+ +

Definition at line 92 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
typedef struct fpc_hcp_packet fpc_hcp_packet_t
+
+ +

Application Command Packet.

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum fpc_hcp_arg
+
+

HCP Argument definitions

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
ARG_NONE  +
ARG_FINGER_DOWN  +
ARG_FINGER_UP  +
ARG_START  +
ARG_ADD  +
ARG_FINISH  +
ARG_ID  +
ARG_ALL  +
ARG_EXTRACT  +
ARG_MATCH_IMAGE  +
ARG_MATCH  +
ARG_ACQUIRE  +
ARG_RELEASE  +
ARG_SET  +
ARG_GET  +
ARG_UPLOAD  +
ARG_DOWNLOAD  +
ARG_CREATE  +
ARG_SAVE  +
ARG_DELETE  +
ARG_DATA  +
ARG_UPDATE  +
ARG_SEQ_NR  +
ARG_SEQ_LEN  +
ARG_RESULT  +
ARG_COUNT  +
ARG_SIZE  +
ARG_LEVEL  +
ARG_FORMAT  +
ARG_FLAG  +
ARG_PROPERTIES  +
ARG_SPEED  +
ARG_PROD_TEST  +
ARG_SENSOR_TYPE  +
ARG_WIDTH  +
ARG_HEIGHT  +
ARG_RESET  +
ARG_DPI  +
ARG_MAX_SPI_CLOCK  +
ARG_NUM_SUB_AREAS_WIDTH  +
ARG_NUM_SUB_AREAS_HEIGHT  +
ARG_IRQ_STATUS  +
ARG_RESET_HARD  +
ARG_IDLE  +
ARG_SLEEP  +
ARG_DEEP_SLEEP  +
ARG_POWER_MODE  +
ARG_BUSY_WAIT  +
ARG_TIMEOUT  +
ARG_DONE  +
ARG_BOOT  +
ARG_STATUS  +
ARG_VERSION  +
ARG_UNIQUE_ID  +
ARG_APP_BASE  +
ARG_NONCE  +
ARG_MAC  +
ARG_RANDOM  +
ARG_CLAIM  +
ARG_PUBLIC_KEY  +
ARG_CIPHERTEXT  +
ARG_MTU  +
ARG_STACK  +
ARG_FILL  +
ARG_HEAP  +
ARG_MODE  +
ARG_DEBUG  +
ARG_FFFF  +
+ +

Definition at line 95 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
enum fpc_hcp_cmd
+
+

HCP Command definitions

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
CMD_NONE  +
CMD_CAPTURE  +
CMD_ENROLL  +
CMD_IDENTIFY  +
CMD_MATCH  +
CMD_IMAGE  +
CMD_TEMPLATE  +
CMD_WAIT  +
CMD_SETTINGS  +
CMD_NAVIGATE  +
CMD_SENSOR  +
CMD_DEADPIXELS  +
CMD_CONNECT  +
CMD_RECONNECT  +
CMD_RESET  +
CMD_CANCEL  +
CMD_INFO  +
CMD_STORAGE_TEMPLATE  +
CMD_STORAGE_CALIBRATION  +
CMD_STORAGE_LOG  +
CMD_STORAGE_SETTINGS  +
CMD_TEST  +
CMD_MCU  +
CMD_GPIO  +
CMD_COMMUNICATION  +
CMD_APP_BASE  +
CMD_DIAG  +
CMD_FFFF  +
+ +

Definition at line 42 of file fpc_hcp_common.h.

+ +
+
+
+
+ + + + diff --git a/hcp/doxygen/html/fpc__hcp__common_8h.js b/hcp/doxygen/html/fpc__hcp__common_8h.js new file mode 100644 index 0000000..3fc7ecd --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp__common_8h.js @@ -0,0 +1,112 @@ +var fpc__hcp__common_8h = +[ + [ "fpc_hcp_arg_data", "structfpc__hcp__arg__data.html", "structfpc__hcp__arg__data" ], + [ "fpc_hcp_packet", "structfpc__hcp__packet.html", "structfpc__hcp__packet" ], + [ "ARG_APP_BASE_VAL", "fpc__hcp__common_8h.html#a09b96c2b90da3d5908a01e5fe67759a8", null ], + [ "CMD_APP_BASE_VAL", "fpc__hcp__common_8h.html#adfce1fcf9573fd4c0176d083e134826c", null ], + [ "HCP_MIN", "fpc__hcp__common_8h.html#a30795492e653a5a0de20222cf9ff927e", null ], + [ "fpc_hcp_arg_data_t", "fpc__hcp__common_8h.html#a4243dac41cd32d44aac72af8e1583b86", null ], + [ "fpc_hcp_arg_t", "fpc__hcp__common_8h.html#a7470deee2c0eae8f5ac7feb71649df0b", null ], + [ "fpc_hcp_cmd_t", "fpc__hcp__common_8h.html#ac3276a2f739c2a97e665a95212e75108", null ], + [ "fpc_hcp_packet_t", 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b/hcp/doxygen/html/fpc__hcp__common_8h__incl.md5 new file mode 100644 index 0000000..c01528b --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp__common_8h__incl.md5 @@ -0,0 +1 @@ +bd263c011edd4c4b84e46030d319bb62 \ No newline at end of file diff --git a/hcp/doxygen/html/fpc__hcp__common_8h__incl.svg b/hcp/doxygen/html/fpc__hcp__common_8h__incl.svg new file mode 100644 index 0000000..9cab59b --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp__common_8h__incl.svg @@ -0,0 +1,38 @@ + + + + + + +inc/fpc_hcp_common.h + + +Node1 + +inc/fpc_hcp_common.h + + +Node2 + +stdint.h + + +Node1->Node2 + + + + +Node3 + +stdbool.h + + +Node1->Node3 + + + + + diff --git a/hcp/doxygen/html/fpc__hcp__common_8h_source.html b/hcp/doxygen/html/fpc__hcp__common_8h_source.html new file mode 100644 index 0000000..ff6eb69 --- /dev/null +++ b/hcp/doxygen/html/fpc__hcp__common_8h_source.html @@ -0,0 +1,197 @@ + + + + + + +Host Communication Protocol: inc/fpc_hcp_common.h Source File + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+
fpc_hcp_common.h
+
+
+Go to the documentation of this file.
1 /*
2  * Copyright (c) 2020 Fingerprint Cards AB
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * https://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
22 #ifndef FPC_HCP_COMMON_H
23 #define FPC_HCP_COMMON_H
24 
25 #include <stdint.h>
26 #include <stdbool.h>
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif /* __cplusplus */
31 
33 #define HCP_MIN(x, y) (((x) < (y)) ? (x) : (y))
34 
36 #define CMD_APP_BASE_VAL 0xE000
37 
39 #define ARG_APP_BASE_VAL 0x7000
40 
42 enum fpc_hcp_cmd {
43  CMD_NONE = 0x0000,
44 
45  /* Biometry */
46  CMD_CAPTURE = 0x0001,
47  CMD_ENROLL = 0x0002,
48  CMD_IDENTIFY = 0x0003,
49  CMD_MATCH = 0x0004,
50  CMD_IMAGE = 0x0005,
51  CMD_TEMPLATE = 0x0006,
52  CMD_WAIT = 0x0007,
53  CMD_SETTINGS = 0x0008,
54 
55  /* Sensor */
56  CMD_NAVIGATE = 0x1001,
57  CMD_SENSOR = 0x1002,
58  CMD_DEADPIXELS = 0x1003,
59 
60  /* Security */
61  CMD_CONNECT = 0x2001,
62  CMD_RECONNECT = 0x2002,
63 
64  /* Firmware */
65  CMD_RESET = 0x3002,
66  CMD_CANCEL = 0x3003,
67  CMD_INFO = 0x3004,
68 
69  /* Storage */
70  CMD_STORAGE_TEMPLATE = 0x4002,
71  CMD_STORAGE_CALIBRATION = 0x4003,
72  CMD_STORAGE_LOG = 0x4004,
73  CMD_STORAGE_SETTINGS = 0x4005,
74 
75  /* Hardware */
76  CMD_TEST = 0x5001,
77  CMD_MCU = 0x5002,
78  CMD_GPIO = 0x5003,
79 
80  /* Communication */
81  CMD_COMMUNICATION = 0x6001,
82 
83  /* Application specific commands */
84  CMD_APP_BASE = CMD_APP_BASE_VAL,
85 
86  /* Debug */
87  CMD_DIAG = 0xF003,
88 
89  CMD_FFFF = 0xFFFF,
90 };
92 typedef uint16_t fpc_hcp_cmd_t;
93 
95 enum fpc_hcp_arg {
96  ARG_NONE = 0x0000,
97 
98  /* Biometry */
99  ARG_FINGER_DOWN = 0x0001,
100  ARG_FINGER_UP = 0x0002,
101  ARG_START = 0x0003,
102  ARG_ADD = 0x0004,
103  ARG_FINISH = 0x0005,
104  ARG_ID = 0x0006,
105  ARG_ALL = 0x0007,
106  ARG_EXTRACT = 0x0008,
107  ARG_MATCH_IMAGE = 0x0009,
108  ARG_MATCH = 0x000A,
109 
110  /* Data */
111  ARG_ACQUIRE = 0x1001,
112  ARG_RELEASE = 0x1002,
113  ARG_SET = 0x1003,
114  ARG_GET = 0x1004,
115  ARG_UPLOAD = 0x1005,
116  ARG_DOWNLOAD = 0x1006,
117  ARG_CREATE = 0x1007,
118  ARG_SAVE = 0x1008,
119  ARG_DELETE = 0x1009,
120  ARG_DATA = 0x100A,
121  ARG_UPDATE = 0x100B,
122  ARG_SEQ_NR = 0x100C,
123  ARG_SEQ_LEN = 0x100D,
124 
125  /* Results */
126  ARG_RESULT = 0x2001,
127  ARG_COUNT = 0x2002,
128  ARG_SIZE = 0x2003,
129  ARG_LEVEL = 0x2004,
130  ARG_FORMAT = 0x2005,
131  ARG_FLAG = 0x2006,
132  ARG_PROPERTIES = 0x2007,
133  ARG_SPEED = 0x2008,
134  ARG_PROD_TEST = 0x2009,
135 
136  /* Sensor */
137  ARG_SENSOR_TYPE = 0x3001,
138  ARG_WIDTH = 0x3002,
139  ARG_HEIGHT = 0x3003,
140  ARG_RESET = 0x3004,
141  ARG_DPI = 0x3005,
142  ARG_MAX_SPI_CLOCK = 0x3006,
143  ARG_NUM_SUB_AREAS_WIDTH = 0x3007,
144  ARG_NUM_SUB_AREAS_HEIGHT = 0x3008,
145  ARG_IRQ_STATUS = 0x3009,
146  ARG_RESET_HARD = 0x300A,
147 
148  /* MCU */
149  ARG_IDLE = 0x4001,
150  ARG_SLEEP = 0x4002,
151  ARG_DEEP_SLEEP = 0x4003,
152  ARG_POWER_MODE = 0x4004,
153  ARG_BUSY_WAIT = 0x4005,
154 
155  /* Misc */
156  ARG_TIMEOUT = 0x5001,
157  ARG_DONE = 0x5002,
158 
159  /* Info */
160  ARG_BOOT = 0x6001,
161  ARG_STATUS = 0x6002,
162  ARG_VERSION = 0x6003,
163  ARG_UNIQUE_ID = 0x6004,
164 
165  /* Application specific arguments */
166  ARG_APP_BASE = ARG_APP_BASE_VAL,
167 
168  /* VSM */
169  ARG_NONCE = 0x8001,
170  ARG_MAC = 0x8002,
171  ARG_RANDOM = 0x8003,
172  ARG_CLAIM = 0x8004,
173  ARG_PUBLIC_KEY = 0x8005,
174  ARG_CIPHERTEXT = 0x8006,
175 
176  /* Communication */
177  ARG_MTU = 0x9001,
178 
179  /* Debug */
180  ARG_STACK = 0xE001,
181  ARG_FILL = 0xE002,
182  ARG_HEAP = 0xE003,
183 
184  /* Log */
185  ARG_MODE = 0xF001,
186  ARG_DEBUG = 0xF002,
187 
188  ARG_FFFF = 0xFFFF,
189 };
191 typedef uint16_t fpc_hcp_arg_t;
192 
196 typedef struct fpc_hcp_arg_data {
198  fpc_hcp_arg_t arg;
200  uint16_t size;
202  bool free_data;
204  uint8_t *data;
205 } fpc_hcp_arg_data_t;
206 
210 typedef struct fpc_hcp_packet {
212  fpc_hcp_cmd_t id;
214  uint16_t num_args;
216  fpc_hcp_arg_data_t *arguments;
217 } fpc_hcp_packet_t;
218 
219 #ifdef __cplusplus
220 }
221 #endif /* __cplusplus */
222 
223 #endif /* FPC_HCP_COMMON_H */
ARG_SLEEP
Definition: fpc_hcp_common.h:150
+
ARG_RESET_HARD
Definition: fpc_hcp_common.h:146
+
fpc_hcp_packet::num_args
uint16_t num_args
Definition: fpc_hcp_common.h:214
+
ARG_UPLOAD
Definition: fpc_hcp_common.h:115
+
fpc_hcp_cmd_t
uint16_t fpc_hcp_cmd_t
Definition: fpc_hcp_common.h:92
+
ARG_NUM_SUB_AREAS_WIDTH
Definition: fpc_hcp_common.h:143
+
ARG_FINGER_DOWN
Definition: fpc_hcp_common.h:99
+
ARG_HEAP
Definition: fpc_hcp_common.h:182
+
fpc_hcp_arg
fpc_hcp_arg
Definition: fpc_hcp_common.h:95
+
ARG_MODE
Definition: fpc_hcp_common.h:185
+
CMD_STORAGE_SETTINGS
Definition: fpc_hcp_common.h:73
+
CMD_APP_BASE_VAL
#define CMD_APP_BASE_VAL
Definition: fpc_hcp_common.h:36
+
ARG_SENSOR_TYPE
Definition: fpc_hcp_common.h:137
+
ARG_MAX_SPI_CLOCK
Definition: fpc_hcp_common.h:142
+
ARG_CREATE
Definition: fpc_hcp_common.h:117
+
ARG_START
Definition: fpc_hcp_common.h:101
+
ARG_MTU
Definition: fpc_hcp_common.h:177
+
CMD_IMAGE
Definition: fpc_hcp_common.h:50
+
fpc_hcp_packet_t
struct fpc_hcp_packet fpc_hcp_packet_t
Application Command Packet.
+
fpc_hcp_arg_data::size
uint16_t size
Definition: fpc_hcp_common.h:200
+
ARG_STACK
Definition: fpc_hcp_common.h:180
+
ARG_SIZE
Definition: fpc_hcp_common.h:128
+
CMD_MCU
Definition: fpc_hcp_common.h:77
+
CMD_NONE
Definition: fpc_hcp_common.h:43
+
fpc_hcp_arg_data::data
uint8_t * data
Definition: fpc_hcp_common.h:204
+
ARG_SPEED
Definition: fpc_hcp_common.h:133
+
fpc_hcp_arg_data::free_data
bool free_data
Definition: fpc_hcp_common.h:202
+
fpc_hcp_packet
Application Command Packet.
Definition: fpc_hcp_common.h:210
+
CMD_CAPTURE
Definition: fpc_hcp_common.h:46
+
CMD_COMMUNICATION
Definition: fpc_hcp_common.h:81
+
fpc_hcp_packet::id
fpc_hcp_cmd_t id
Definition: fpc_hcp_common.h:212
+
CMD_GPIO
Definition: fpc_hcp_common.h:78
+
ARG_LEVEL
Definition: fpc_hcp_common.h:129
+
CMD_DEADPIXELS
Definition: fpc_hcp_common.h:58
+
CMD_TEMPLATE
Definition: fpc_hcp_common.h:51
+
ARG_DPI
Definition: fpc_hcp_common.h:141
+
CMD_WAIT
Definition: fpc_hcp_common.h:52
+
ARG_SEQ_LEN
Definition: fpc_hcp_common.h:123
+
CMD_DIAG
Definition: fpc_hcp_common.h:87
+
ARG_APP_BASE
Definition: fpc_hcp_common.h:166
+
ARG_BOOT
Definition: fpc_hcp_common.h:160
+
ARG_VERSION
Definition: fpc_hcp_common.h:162
+
ARG_GET
Definition: fpc_hcp_common.h:114
+
ARG_FINGER_UP
Definition: fpc_hcp_common.h:100
+
CMD_SENSOR
Definition: fpc_hcp_common.h:57
+
ARG_MATCH
Definition: fpc_hcp_common.h:108
+
ARG_PROD_TEST
Definition: fpc_hcp_common.h:134
+
ARG_FLAG
Definition: fpc_hcp_common.h:131
+
CMD_STORAGE_TEMPLATE
Definition: fpc_hcp_common.h:70
+
ARG_NUM_SUB_AREAS_HEIGHT
Definition: fpc_hcp_common.h:144
+
ARG_CLAIM
Definition: fpc_hcp_common.h:172
+
ARG_NONCE
Definition: fpc_hcp_common.h:169
+
ARG_RELEASE
Definition: fpc_hcp_common.h:112
+
ARG_ACQUIRE
Definition: fpc_hcp_common.h:111
+
CMD_APP_BASE
Definition: fpc_hcp_common.h:84
+
CMD_RESET
Definition: fpc_hcp_common.h:65
+
ARG_ID
Definition: fpc_hcp_common.h:104
+
ARG_COUNT
Definition: fpc_hcp_common.h:127
+
ARG_MATCH_IMAGE
Definition: fpc_hcp_common.h:107
+
CMD_TEST
Definition: fpc_hcp_common.h:76
+
ARG_PUBLIC_KEY
Definition: fpc_hcp_common.h:173
+
ARG_EXTRACT
Definition: fpc_hcp_common.h:106
+
ARG_ADD
Definition: fpc_hcp_common.h:102
+
fpc_hcp_arg_data
Command Argument.
Definition: fpc_hcp_common.h:196
+
CMD_NAVIGATE
Definition: fpc_hcp_common.h:56
+
ARG_STATUS
Definition: fpc_hcp_common.h:161
+
ARG_UNIQUE_ID
Definition: fpc_hcp_common.h:163
+
ARG_UPDATE
Definition: fpc_hcp_common.h:121
+
ARG_NONE
Definition: fpc_hcp_common.h:96
+
ARG_DELETE
Definition: fpc_hcp_common.h:119
+
ARG_ALL
Definition: fpc_hcp_common.h:105
+
ARG_DEBUG
Definition: fpc_hcp_common.h:186
+
ARG_PROPERTIES
Definition: fpc_hcp_common.h:132
+
ARG_RANDOM
Definition: fpc_hcp_common.h:171
+
ARG_IDLE
Definition: fpc_hcp_common.h:149
+
ARG_FORMAT
Definition: fpc_hcp_common.h:130
+
CMD_INFO
Definition: fpc_hcp_common.h:67
+
CMD_CANCEL
Definition: fpc_hcp_common.h:66
+
ARG_DEEP_SLEEP
Definition: fpc_hcp_common.h:151
+
fpc_hcp_arg_t
uint16_t fpc_hcp_arg_t
Definition: fpc_hcp_common.h:191
+
ARG_DONE
Definition: fpc_hcp_common.h:157
+
ARG_FFFF
Definition: fpc_hcp_common.h:188
+
ARG_MAC
Definition: fpc_hcp_common.h:170
+
ARG_BUSY_WAIT
Definition: fpc_hcp_common.h:153
+
fpc_hcp_packet::arguments
fpc_hcp_arg_data_t * arguments
Definition: fpc_hcp_common.h:216
+
ARG_SEQ_NR
Definition: fpc_hcp_common.h:122
+
CMD_CONNECT
Definition: fpc_hcp_common.h:61
+
ARG_DATA
Definition: fpc_hcp_common.h:120
+
CMD_STORAGE_LOG
Definition: fpc_hcp_common.h:72
+
fpc_hcp_cmd
fpc_hcp_cmd
Definition: fpc_hcp_common.h:42
+
ARG_APP_BASE_VAL
#define ARG_APP_BASE_VAL
Definition: fpc_hcp_common.h:39
+
CMD_SETTINGS
Definition: fpc_hcp_common.h:53
+
ARG_RESET
Definition: fpc_hcp_common.h:140
+
CMD_ENROLL
Definition: fpc_hcp_common.h:47
+
ARG_HEIGHT
Definition: fpc_hcp_common.h:139
+
CMD_MATCH
Definition: fpc_hcp_common.h:49
+
ARG_FINISH
Definition: fpc_hcp_common.h:103
+
CMD_FFFF
Definition: fpc_hcp_common.h:89
+
ARG_TIMEOUT
Definition: fpc_hcp_common.h:156
+
fpc_hcp_arg_data_t
struct fpc_hcp_arg_data fpc_hcp_arg_data_t
Command Argument.
+
ARG_RESULT
Definition: fpc_hcp_common.h:126
+
fpc_hcp_arg_data::arg
fpc_hcp_arg_t arg
Definition: fpc_hcp_common.h:198
+
ARG_SET
Definition: fpc_hcp_common.h:113
+
CMD_IDENTIFY
Definition: fpc_hcp_common.h:48
+
ARG_IRQ_STATUS
Definition: fpc_hcp_common.h:145
+
ARG_SAVE
Definition: fpc_hcp_common.h:118
+
ARG_CIPHERTEXT
Definition: fpc_hcp_common.h:174
+
CMD_RECONNECT
Definition: fpc_hcp_common.h:62
+
CMD_STORAGE_CALIBRATION
Definition: fpc_hcp_common.h:71
+
ARG_POWER_MODE
Definition: fpc_hcp_common.h:152
+
ARG_WIDTH
Definition: fpc_hcp_common.h:138
+
ARG_FILL
Definition: fpc_hcp_common.h:181
+
ARG_DOWNLOAD
Definition: fpc_hcp_common.h:116
+
+
+ + + + diff --git a/hcp/doxygen/html/functions.html b/hcp/doxygen/html/functions.html new file mode 100644 index 0000000..f092547 --- /dev/null +++ b/hcp/doxygen/html/functions.html @@ -0,0 +1,261 @@ + + + + + + +Host Communication Protocol: Data Fields + + + + + + + + + + + +
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Host Communication Protocol +  2.0 +
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Host Communication Protocol +  2.0 +
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Graph Legend
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This page explains how to interpret the graphs that are generated by doxygen.

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Consider the following example:

1 /*! Invisible class because of truncation */
2 class Invisible { };
3 
4 /*! Truncated class, inheritance relation is hidden */
5 class Truncated : public Invisible { };
6 
7 /* Class not documented with doxygen comments */
8 class Undocumented { };
9 
10 /*! Class that is inherited using public inheritance */
11 class PublicBase : public Truncated { };
12 
13 /*! A template class */
14 template<class T> class Templ { };
15 
16 /*! Class that is inherited using protected inheritance */
17 class ProtectedBase { };
18 
19 /*! Class that is inherited using private inheritance */
20 class PrivateBase { };
21 
22 /*! Class that is used by the Inherited class */
23 class Used { };
24 
25 /*! Super class that inherits a number of other classes */
26 class Inherited : public PublicBase,
27  protected ProtectedBase,
28  private PrivateBase,
29  public Undocumented,
30  public Templ<int>
31 {
32  private:
33  Used *m_usedClass;
34 };

This will result in the following graph:

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Go to the source code of this file.

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hcp.md
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+Go to the documentation of this file.
1 # Main {#mainpage}
2 
3 Welcome to the documentation for the Host Communication Protocol (HCP).
4 
5 The first part covers the physical method of sending messages and the second part covers the
6 specification of the different command flows.
7 
8 \section fes FPC embedded stack and HCP
9 - \subpage stack
10 - \subpage hcpf
11 
12 \section cfs Command flow specification
13 - \subpage bio
14  - \ref capture_b
15  - \ref extract_b
16  - \ref enroll_b
17  - \ref identify_b
18 - \subpage image
19 - \subpage template
20 - \subpage storage
21 - \subpage sensor
22 - \subpage device
+
+ + + + diff --git a/hcp/doxygen/html/hcpf.html b/hcp/doxygen/html/hcpf.html new file mode 100644 index 0000000..2c4bc96 --- /dev/null +++ b/hcp/doxygen/html/hcpf.html @@ -0,0 +1,103 @@ + + + + + + +Host Communication Protocol: HCP frame format + + + + + + + + + + + +
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Host Communication Protocol +  2.0 +
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+
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+
+ +
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+
+
+
HCP frame format
+
+
+

The Host Communication Protocol (HCP) describes a general way of sending commands and information between devices.

+
+hcp.svg +
+HCP frame format
+

+Command

+

The Commands define the general action that is going to be executed. However, each command can have several Arguments each with data attached.

+ + + + + +
CMD Num Args Payload
2 bytes 2 bytes xx bytes
+

All fields are using unsigned data types.

+

+Argument

+

The Argument is used as a complement to the command if it is needed and can contain arbitrary data.

+ + + + + +
ARG Size Data
2 bytes 2 bytes size bytes
+

All fields are using unsigned data types.

+
+
+ + + + diff --git a/hcp/doxygen/html/image.html b/hcp/doxygen/html/image.html new file mode 100644 index 0000000..faf8031 --- /dev/null +++ b/hcp/doxygen/html/image.html @@ -0,0 +1,87 @@ + + + + + + +Host Communication Protocol: Image handling + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + +
+
+ +
+
+
+ +
+
+
+
Image handling
+
+
+

+Create

+
+

+Upload

+
+

+Download

+
+
+
+ + + + diff --git a/hcp/doxygen/html/index.html b/hcp/doxygen/html/index.html new file mode 100644 index 0000000..bd8f33c --- /dev/null +++ b/hcp/doxygen/html/index.html @@ -0,0 +1,101 @@ + + + + + + +Host Communication Protocol: Main + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
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+ + + +
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+
+
Main
+
+
+

Welcome to the documentation for the Host Communication Protocol (HCP).

+

The first part covers the physical method of sending messages and the second part covers the specification of the different command flows.

+

+FPC embedded stack and HCP

+ +

+Command flow specification

+ +
+
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bw=this[0],bv=this.offsetParent(),bx=this.offset(),e=ad.test(bv[0].nodeName)?{top:0,left:0}:bv.offset();bx.top-=parseFloat(b.css(bw,"marginTop"))||0;bx.left-=parseFloat(b.css(bw,"marginLeft"))||0;e.top+=parseFloat(b.css(bv[0],"borderTopWidth"))||0;e.left+=parseFloat(b.css(bv[0],"borderLeftWidth"))||0;return{top:bx.top-e.top,left:bx.left-e.left}},offsetParent:function(){return this.map(function(){var e=this.offsetParent||av.body;while(e&&(!ad.test(e.nodeName)&&b.css(e,"position")==="static")){e=e.offsetParent}return e})}});b.each(["Left","Top"],function(bv,e){var bw="scroll"+e;b.fn[bw]=function(bz){var bx,by;if(bz===L){bx=this[0];if(!bx){return null}by=aK(bx);return by?("pageXOffset" in by)?by[bv?"pageYOffset":"pageXOffset"]:b.support.boxModel&&by.document.documentElement[bw]||by.document.body[bw]:bx[bw]}return this.each(function(){by=aK(this);if(by){by.scrollTo(!bv?bz:b(by).scrollLeft(),bv?bz:b(by).scrollTop())}else{this[bw]=bz}})}});function aK(e){return b.isWindow(e)?e:e.nodeType===9?e.defaultView||e.parentWindow:false}b.each(["Height","Width"],function(bv,e){var bw=e.toLowerCase();b.fn["inner"+e]=function(){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,"padding")):this[bw]():null};b.fn["outer"+e]=function(by){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,by?"margin":"border")):this[bw]():null};b.fn[bw]=function(bz){var bA=this[0];if(!bA){return bz==null?null:this}if(b.isFunction(bz)){return this.each(function(bE){var bD=b(this);bD[bw](bz.call(this,bE,bD[bw]()))})}if(b.isWindow(bA)){var bB=bA.document.documentElement["client"+e],bx=bA.document.body;return bA.document.compatMode==="CSS1Compat"&&bB||bx&&bx["client"+e]||bB}else{if(bA.nodeType===9){return Math.max(bA.documentElement["client"+e],bA.body["scroll"+e],bA.documentElement["scroll"+e],bA.body["offset"+e],bA.documentElement["offset"+e])}else{if(bz===L){var bC=b.css(bA,bw),by=parseFloat(bC);return b.isNumeric(by)?by:bC}else{return this.css(bw,typeof bz==="string"?bz:bz+"px")}}}}});bb.jQuery=bb.$=b;if(typeof define==="function"&&define.amd&&define.amd.jQuery){define("jquery",[],function(){return b})}})(window);/* + * jQuery UI 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI + */ +(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:"1.8.18",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e==="number"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css("position")))||(/absolute/).test(this.css("position"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,"position",1))&&(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,"overflow",1)+a.curCSS(this,"overflow-y",1)+a.curCSS(this,"overflow-x",1))}).eq(0)}return(/fixed/).test(this.css("position"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css("zIndex",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css("position");if(e==="absolute"||e==="relative"||e==="fixed"){g=parseInt(f.css("zIndex"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/* + * jQuery UI Widget 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Widget + */ +(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i==="string",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)==="_"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:"widget",widgetEventPrefix:"",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind("remove."+this.widgetName,function(){e.destroy()});this._create();this._trigger("create");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind("."+this.widgetName).removeData(this.widgetName);this.widget().unbind("."+this.widgetName).removeAttr("aria-disabled").removeClass(this.widgetBaseClass+"-disabled ui-state-disabled")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f==="string"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e==="disabled"){this.widget()[f?"addClass":"removeClass"](this.widgetBaseClass+"-disabled ui-state-disabled").attr("aria-disabled",f)}return this},enable:function(){return this._setOption("disabled",false)},disable:function(){return this._setOption("disabled",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/* + * jQuery UI Mouse 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var 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[legend]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

bool initialized
 
uint32_t(* crc_calc )(uint32_t start, const void *data, uint32_t size)
 
fpc_com_chain_private_t private_vars
 
void * session
 User session pointer. User private stuff, to be able to pass necessary info from the layer that calls hcp down to the user's TX and RX functions (phy_tx/rx), to enable multi threaded applications at the host side. More...
 
void * context
 User context pointer. User private stuff, to be able to pass nessecary context to argument_allocator and argument_free. More...
 
HCP Layer
void *(* argument_allocator )(fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size, bool *free_data, void *context)
 
void(* argument_free )(fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, void *context)
 
Application Layer
fpc_com_result_t(* app_tx )(fpc_com_chain_t *chain)
 
fpc_com_result_t(* app_rx )(fpc_com_chain_t *chain)
 
uint16_t(* app_overhead_get )(uint16_t *offset)
 
uint16_t app_packet_size [2]
 
uint16_t app_mtu_size [2]
 
uint8_t * app_mtu_buffer [2]
 
Transport Layer
fpc_com_result_t(* tsp_tx )(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 
fpc_com_result_t(* tsp_rx )(fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
 
uint16_t(* tsp_overhead_get )(uint16_t *offset)
 
Link Layer
uint16_t(* link_overhead_get )(uint16_t *offset)
 
fpc_com_channel_t channel
 
Physical Layer
fpc_com_result_t(* phy_tx )(uint16_t size, const uint8_t *buffer, uint32_t timeout, void *session)
 
fpc_com_result_t(* phy_rx )(uint16_t size, uint8_t *buffer, uint32_t timeout, void *session)
 
uint16_t phy_mtu_size [2]
 
uint8_t * phy_mtu_buffer [2]
 
uint32_t phy_timeout_tx
 
uint32_t phy_timeout_rx
 
+

Detailed Description

+

Communication chain struct

+ +

Definition at line 50 of file fpc_com_chain.h.

+

Field Documentation

+ +
+
+ + + + +
uint8_t* fpc_com_chain::app_mtu_buffer[2]
+
+

Application MTU buffers

+ +

Definition at line 83 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_chain::app_mtu_size[2]
+
+

Application MTU sizes

+ +

Definition at line 81 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t(* fpc_com_chain::app_overhead_get) (uint16_t *offset)
+
+

Application layer overhead get interface function

+ +

Definition at line 77 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_chain::app_packet_size[2]
+
+

Application packet sizes

+ +

Definition at line 79 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::app_rx) (fpc_com_chain_t *chain)
+
+

Application layer receive interface function

+ +

Definition at line 75 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::app_tx) (fpc_com_chain_t *chain)
+
+

Application layer transmit interface function

+ +

Definition at line 73 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
void*(* fpc_com_chain::argument_allocator) (fpc_hcp_cmd_t cmd, fpc_hcp_arg_t arg, uint16_t size, bool *free_data, void *context)
+
+

Argument allocator interface function

+ +

Definition at line 59 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
void(* fpc_com_chain::argument_free) (fpc_hcp_cmd_t cmd, fpc_hcp_arg_data_t *arg_data, void *context)
+
+

Argument free interface function

+ +

Definition at line 62 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_channel_t fpc_com_chain::channel
+
+

Communication channel

+ +

Definition at line 105 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
void* fpc_com_chain::context
+
+ +

User context pointer. User private stuff, to be able to pass nessecary context to argument_allocator and argument_free.

+ +

Definition at line 143 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint32_t(* fpc_com_chain::crc_calc) (uint32_t start, const void *data, uint32_t size)
+
+

CRC calculation interface function

+ +

Definition at line 66 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
bool fpc_com_chain::initialized
+
+

Initialization status

+ +

Definition at line 52 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t(* fpc_com_chain::link_overhead_get) (uint16_t *offset)
+
+

Link layer overhead get interface function

+ +

Definition at line 103 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint8_t* fpc_com_chain::phy_mtu_buffer[2]
+
+

Physical MTU buffers

+ +

Definition at line 121 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_chain::phy_mtu_size[2]
+
+

Physical MTU sizes

+ +

Definition at line 119 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::phy_rx) (uint16_t size, uint8_t *buffer, uint32_t timeout, void *session)
+
+

Physical layer receive interface function

+ +

Definition at line 116 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint32_t fpc_com_chain::phy_timeout_rx
+
+

Physical receive timeout

+ +

Definition at line 125 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint32_t fpc_com_chain::phy_timeout_tx
+
+

Physical transmit timeout

+ +

Definition at line 123 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::phy_tx) (uint16_t size, const uint8_t *buffer, uint32_t timeout, void *session)
+
+

Physical layer transmit interface function

+ +

Definition at line 113 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_chain_private_t fpc_com_chain::private_vars
+
+

Communication change private variables

+ +

Definition at line 129 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
void* fpc_com_chain::session
+
+ +

User session pointer. User private stuff, to be able to pass necessary info from the layer that calls hcp down to the user's TX and RX functions (phy_tx/rx), to enable multi threaded applications at the host side.

+ +

Definition at line 137 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t(* fpc_com_chain::tsp_overhead_get) (uint16_t *offset)
+
+

Transport layer overhead get interface function

+ +

Definition at line 95 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::tsp_rx) (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
+
+

Transport layer receive interface function

+ +

Definition at line 93 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
fpc_com_result_t(* fpc_com_chain::tsp_tx) (fpc_com_packet_tsp_t *packet, fpc_com_chain_t *chain)
+
+

Transport layer transmit interface function

+ +

Definition at line 91 of file fpc_com_chain.h.

+ +
+
+
The documentation for this struct was generated from the following file: + + + + + + diff --git a/hcp/doxygen/html/structfpc__com__chain.js b/hcp/doxygen/html/structfpc__com__chain.js new file mode 100644 index 0000000..0f4123f --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain.js @@ -0,0 +1,27 @@ +var structfpc__com__chain = +[ + [ "app_mtu_buffer", "structfpc__com__chain.html#a7e8d84ccc4f808b0b95a4968f8445793", null ], + [ "app_mtu_size", "structfpc__com__chain.html#aacb377d52218056953552b9528654e75", null ], + [ "app_overhead_get", "structfpc__com__chain.html#a0059f42e6687eb0f82e5ee1de6b7236b", null ], + [ "app_packet_size", "structfpc__com__chain.html#aa60e372908d633b665e2ee4e3f220eac", null ], + [ "app_rx", "structfpc__com__chain.html#adc6a3bbad06589291a9441417cbb48c5", null ], + [ "app_tx", "structfpc__com__chain.html#a3498d443baffb40cb1201380423a753d", null ], + [ "argument_allocator", "structfpc__com__chain.html#a6e99f2fce0216d384bfba272cfba56b9", null ], + [ "argument_free", "structfpc__com__chain.html#af2a276eb2ccc79b6165584d97e798874", null ], + [ "channel", "structfpc__com__chain.html#aa42c6bf7052b0047c8b91635a13674d8", null ], + [ "context", "structfpc__com__chain.html#a6b907ebf3aeb09944baae1fd72a7abf9", null ], + [ "crc_calc", "structfpc__com__chain.html#ac697aca7a789065170e24d18647df0e7", null ], + [ "initialized", "structfpc__com__chain.html#a4a5f51c68263c56df53e3026d0959c4c", null ], + [ "link_overhead_get", "structfpc__com__chain.html#a055b5749b6e11042f39604bc7c7a33fe", null ], + [ "phy_mtu_buffer", "structfpc__com__chain.html#a63a02907c00e5443c7c3d4c0bd158d36", null ], + [ "phy_mtu_size", "structfpc__com__chain.html#ad135c2c04d54045141c2c3ffff09636d", null ], + [ "phy_rx", "structfpc__com__chain.html#ae0e4aa33099bfc0c9910c7b6bb30f915", null ], + [ "phy_timeout_rx", "structfpc__com__chain.html#a2e3f88e744ac92baecf22b8be8b8bdb2", null ], + [ "phy_timeout_tx", "structfpc__com__chain.html#a12a7599fb0f8ca779f6f5ac1df47bed2", null ], + [ "phy_tx", "structfpc__com__chain.html#a67cdb9c412d3478b46f9091d094c4faf", null ], + [ "private_vars", "structfpc__com__chain.html#a30701342d30047f48d0ec4f3f47f6ca3", null ], + [ "session", "structfpc__com__chain.html#a92eac8623fea4a4134d073233d25a63f", null ], + [ "tsp_overhead_get", "structfpc__com__chain.html#a319d3aa6f72ba5b04f6ac73bd09e860e", null ], + [ "tsp_rx", "structfpc__com__chain.html#a72f15dbe8cd7750f8f33346783404fb9", null ], + [ "tsp_tx", "structfpc__com__chain.html#aa9ee59b2a8c25a2cec027c078bb5db57", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__com__chain__coll__graph.map b/hcp/doxygen/html/structfpc__com__chain__coll__graph.map new file mode 100644 index 0000000..ae3a4a5 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__coll__graph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/hcp/doxygen/html/structfpc__com__chain__coll__graph.md5 b/hcp/doxygen/html/structfpc__com__chain__coll__graph.md5 new file mode 100644 index 0000000..b582e7d --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__coll__graph.md5 @@ -0,0 +1 @@ +62b5c96dd34d9372a91cd51284c482c6 \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__com__chain__coll__graph.svg b/hcp/doxygen/html/structfpc__com__chain__coll__graph.svg new file mode 100644 index 0000000..151441b --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__coll__graph.svg @@ -0,0 +1,60 @@ + + + + + + +fpc_com_chain + + +Node1 + +fpc_com_chain + + +Node2 + + +fpc_com_chain_private + + + + +Node2->Node1 + + + private_vars + + +Node3 + + +fpc_hcp_packet + + + + +Node3->Node2 + + + hcp_packet + + +Node4 + + +fpc_hcp_arg_data + + + + +Node4->Node3 + + + arguments + + + diff --git a/hcp/doxygen/html/structfpc__com__chain__private.html b/hcp/doxygen/html/structfpc__com__chain__private.html new file mode 100644 index 0000000..6565d01 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__private.html @@ -0,0 +1,158 @@ + + + + + + +Host Communication Protocol: fpc_com_chain_private Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Fields
+
+
fpc_com_chain_private Struct Reference
+
+
+ +

#include <fpc_com_chain.h>

+
+Collaboration diagram for fpc_com_chain_private:
+
+
+
+
[legend]
+ + + + + + + + +

+Data Fields

fpc_hcp_packet_t * hcp_packet
 
uint16_t hcp_seq_len
 
uint16_t hcp_seq_nr
 
+

Detailed Description

+

Communication chain private struct

+ +

Definition at line 36 of file fpc_com_chain.h.

+

Field Documentation

+ +
+
+ + + + +
fpc_hcp_packet_t* fpc_com_chain_private::hcp_packet
+
+

HCP packet

+ +

Definition at line 38 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_chain_private::hcp_seq_len
+
+

HCP sequence length

+ +

Definition at line 40 of file fpc_com_chain.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_chain_private::hcp_seq_nr
+
+

HCP sequence number

+ +

Definition at line 42 of file fpc_com_chain.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/hcp/doxygen/html/structfpc__com__chain__private.js b/hcp/doxygen/html/structfpc__com__chain__private.js new file mode 100644 index 0000000..ffa1f0b --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__private.js @@ -0,0 +1,6 @@ +var structfpc__com__chain__private = +[ + [ "hcp_packet", "structfpc__com__chain__private.html#ab64b1b4bd3081ca3db41ffa0e81bc916", null ], + [ "hcp_seq_len", "structfpc__com__chain__private.html#af8ce1ceb9f2ce4cfca0c5db4112b66a0", null ], + [ "hcp_seq_nr", "structfpc__com__chain__private.html#ac3cc68074e460e7f02487f4fd3b0f72b", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.map b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.map new file mode 100644 index 0000000..fc2dc95 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.map @@ -0,0 +1,4 @@ + + + + diff --git a/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.md5 b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.md5 new file mode 100644 index 0000000..ee40ef7 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.md5 @@ -0,0 +1 @@ +7c008b78ccb55fb4de6e98769ef6f843 \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.svg b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.svg new file mode 100644 index 0000000..6d344fc --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__chain__private__coll__graph.svg @@ -0,0 +1,46 @@ + + + + + + +fpc_com_chain_private + + +Node1 + +fpc_com_chain_private + + +Node2 + + +fpc_hcp_packet + + + + +Node2->Node1 + + + hcp_packet + + +Node3 + + +fpc_hcp_arg_data + + + + +Node3->Node2 + + + arguments + + + diff --git a/hcp/doxygen/html/structfpc__com__packet__link.html b/hcp/doxygen/html/structfpc__com__packet__link.html new file mode 100644 index 0000000..e845432 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__packet__link.html @@ -0,0 +1,169 @@ + + + + + + +Host Communication Protocol: fpc_com_packet_link Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Fields
+
+
fpc_com_packet_link Struct Reference
+
+
+ +

#include <fpc_com_packets.h>

+ + + + + + + + + + +

+Data Fields

fpc_com_channel_t channel
 
uint16_t size
 
uint8_t * data
 
uint32_t crc
 
+

Detailed Description

+

Link layer packet

+ +

Definition at line 61 of file fpc_com_packets.h.

+

Field Documentation

+ +
+
+ + + + +
fpc_com_channel_t fpc_com_packet_link::channel
+
+

Communication channel

+ +

Definition at line 63 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint32_t fpc_com_packet_link::crc
+
+

CRC of data

+ +

Definition at line 69 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint8_t* fpc_com_packet_link::data
+
+

Packet data

+ +

Definition at line 67 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_packet_link::size
+
+

Size of packet

+ +

Definition at line 65 of file fpc_com_packets.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/hcp/doxygen/html/structfpc__com__packet__link.js b/hcp/doxygen/html/structfpc__com__packet__link.js new file mode 100644 index 0000000..7b35e09 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__packet__link.js @@ -0,0 +1,7 @@ +var structfpc__com__packet__link = +[ + [ "channel", "structfpc__com__packet__link.html#aa90708dd6d842b318723cb70d6939c2a", null ], + [ "crc", "structfpc__com__packet__link.html#a2b36a249ee8d192688f2a5f3cce8cde4", null ], + [ "data", "structfpc__com__packet__link.html#ac5412a399ecd825e331b560c1ec078fd", null ], + [ "size", "structfpc__com__packet__link.html#a7305e6e32039579c1258ccb42513049b", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__com__packet__transport.html b/hcp/doxygen/html/structfpc__com__packet__transport.html new file mode 100644 index 0000000..e30f80d --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__packet__transport.html @@ -0,0 +1,169 @@ + + + + + + +Host Communication Protocol: fpc_com_packet_transport Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Fields
+
+
fpc_com_packet_transport Struct Reference
+
+
+ +

#include <fpc_com_packets.h>

+ + + + + + + + + + +

+Data Fields

uint16_t size
 
uint16_t seq_len
 
uint16_t seq_nr
 
uint8_t * data
 
+

Detailed Description

+

Transport layer packet.

+ +

Definition at line 37 of file fpc_com_packets.h.

+

Field Documentation

+ +
+
+ + + + +
uint8_t* fpc_com_packet_transport::data
+
+

Packet data

+ +

Definition at line 45 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_packet_transport::seq_len
+
+

Sequence length

+ +

Definition at line 41 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_packet_transport::seq_nr
+
+

Sequence number

+ +

Definition at line 43 of file fpc_com_packets.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_com_packet_transport::size
+
+

Size of packet

+ +

Definition at line 39 of file fpc_com_packets.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/hcp/doxygen/html/structfpc__com__packet__transport.js b/hcp/doxygen/html/structfpc__com__packet__transport.js new file mode 100644 index 0000000..6fef708 --- /dev/null +++ b/hcp/doxygen/html/structfpc__com__packet__transport.js @@ -0,0 +1,7 @@ +var structfpc__com__packet__transport = +[ + [ "data", "structfpc__com__packet__transport.html#a701682a127995ad73fd3d945faa0e6d0", null ], + [ "seq_len", "structfpc__com__packet__transport.html#af72d4eb7fdaf84b87dd369b348eafc6d", null ], + [ "seq_nr", "structfpc__com__packet__transport.html#a41944ffde2478be8fca892e84bd633c0", null ], + [ "size", "structfpc__com__packet__transport.html#a9c0d37a137ba70a8d0ecd17802e3810a", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__hcp__arg__data.html b/hcp/doxygen/html/structfpc__hcp__arg__data.html new file mode 100644 index 0000000..b542592 --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__arg__data.html @@ -0,0 +1,172 @@ + + + + + + +Host Communication Protocol: fpc_hcp_arg_data Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Fields
+
+
fpc_hcp_arg_data Struct Reference
+
+
+ +

Command Argument. + More...

+ +

#include <fpc_hcp_common.h>

+ + + + + + + + + + +

+Data Fields

fpc_hcp_arg_t arg
 
uint16_t size
 
bool free_data
 
uint8_t * data
 
+

Detailed Description

+

Command Argument.

+ +

Definition at line 196 of file fpc_hcp_common.h.

+

Field Documentation

+ +
+
+ + + + +
fpc_hcp_arg_t fpc_hcp_arg_data::arg
+
+

Argument

+ +

Definition at line 198 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
uint8_t* fpc_hcp_arg_data::data
+
+

Pointer to data

+ +

Definition at line 204 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
bool fpc_hcp_arg_data::free_data
+
+

Free data inside HCP

+ +

Definition at line 202 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_hcp_arg_data::size
+
+

Size of data

+ +

Definition at line 200 of file fpc_hcp_common.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/hcp/doxygen/html/structfpc__hcp__arg__data.js b/hcp/doxygen/html/structfpc__hcp__arg__data.js new file mode 100644 index 0000000..bed4817 --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__arg__data.js @@ -0,0 +1,7 @@ +var structfpc__hcp__arg__data = +[ + [ "arg", "structfpc__hcp__arg__data.html#ad10d9a131410e8832ee545e38c2957f0", null ], + [ "data", "structfpc__hcp__arg__data.html#a96b9e7812ba72f1c27355f8896079c2e", null ], + [ "free_data", "structfpc__hcp__arg__data.html#a2b1579dabe9af25ac70ba5c9345bec6a", null ], + [ "size", "structfpc__hcp__arg__data.html#aaee76f9b7bf53b5b9095ae68a8dbe4ec", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__hcp__packet.html b/hcp/doxygen/html/structfpc__hcp__packet.html new file mode 100644 index 0000000..f6befcd --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__packet.html @@ -0,0 +1,161 @@ + + + + + + +Host Communication Protocol: fpc_hcp_packet Struct Reference + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + + +
+
+ +
+
+
+ +
+
+
+Data Fields
+
+
fpc_hcp_packet Struct Reference
+
+
+ +

Application Command Packet. + More...

+ +

#include <fpc_hcp_common.h>

+
+Collaboration diagram for fpc_hcp_packet:
+
+
+
+
[legend]
+ + + + + + + + +

+Data Fields

fpc_hcp_cmd_t id
 
uint16_t num_args
 
fpc_hcp_arg_data_t * arguments
 
+

Detailed Description

+

Application Command Packet.

+ +

Definition at line 210 of file fpc_hcp_common.h.

+

Field Documentation

+ +
+
+ + + + +
fpc_hcp_arg_data_t* fpc_hcp_packet::arguments
+
+

Pointer to argument data

+ +

Definition at line 216 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
fpc_hcp_cmd_t fpc_hcp_packet::id
+
+

Command ID

+ +

Definition at line 212 of file fpc_hcp_common.h.

+ +
+
+ +
+
+ + + + +
uint16_t fpc_hcp_packet::num_args
+
+

Number of arguments

+ +

Definition at line 214 of file fpc_hcp_common.h.

+ +
+
+
The documentation for this struct was generated from the following file: +
+
+ + + + diff --git a/hcp/doxygen/html/structfpc__hcp__packet.js b/hcp/doxygen/html/structfpc__hcp__packet.js new file mode 100644 index 0000000..2e725bc --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__packet.js @@ -0,0 +1,6 @@ +var structfpc__hcp__packet = +[ + [ "arguments", "structfpc__hcp__packet.html#a12c84e4603123d4a7b7968c1a408ac8a", null ], + [ "id", "structfpc__hcp__packet.html#a048db38d843571e797e3768b7e28691d", null ], + [ "num_args", "structfpc__hcp__packet.html#a43efbc11424d711b82fe5dde8d8da393", null ] +]; \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.map b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.map new file mode 100644 index 0000000..542b000 --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.map @@ -0,0 +1,3 @@ + + + diff --git a/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.md5 b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.md5 new file mode 100644 index 0000000..8db2ba9 --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.md5 @@ -0,0 +1 @@ +bb44f25e236a810c642564aa21997983 \ No newline at end of file diff --git a/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.svg b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.svg new file mode 100644 index 0000000..9a08ef3 --- /dev/null +++ b/hcp/doxygen/html/structfpc__hcp__packet__coll__graph.svg @@ -0,0 +1,32 @@ + + + + + + +fpc_hcp_packet + + +Node1 + +fpc_hcp_packet + + +Node2 + + +fpc_hcp_arg_data + + + + +Node2->Node1 + + + arguments + + + diff --git a/hcp/doxygen/html/sync_off.png b/hcp/doxygen/html/sync_off.png new file mode 100644 index 0000000..3b443fc Binary files /dev/null and b/hcp/doxygen/html/sync_off.png differ diff --git a/hcp/doxygen/html/sync_on.png b/hcp/doxygen/html/sync_on.png new file mode 100644 index 0000000..e08320f Binary files /dev/null and b/hcp/doxygen/html/sync_on.png differ diff --git a/hcp/doxygen/html/tab_a.png b/hcp/doxygen/html/tab_a.png new file mode 100644 index 0000000..3b725c4 Binary files /dev/null and b/hcp/doxygen/html/tab_a.png differ diff --git a/hcp/doxygen/html/tab_b.png b/hcp/doxygen/html/tab_b.png new file mode 100644 index 0000000..e2b4a86 Binary files /dev/null and b/hcp/doxygen/html/tab_b.png differ diff --git a/hcp/doxygen/html/tab_h.png b/hcp/doxygen/html/tab_h.png new file mode 100644 index 0000000..fd5cb70 Binary files /dev/null and b/hcp/doxygen/html/tab_h.png differ diff --git a/hcp/doxygen/html/tab_s.png b/hcp/doxygen/html/tab_s.png new file mode 100644 index 0000000..ab478c9 Binary files /dev/null and b/hcp/doxygen/html/tab_s.png differ diff --git a/hcp/doxygen/html/tabs.css b/hcp/doxygen/html/tabs.css new file mode 100644 index 0000000..9cf578f --- /dev/null +++ b/hcp/doxygen/html/tabs.css @@ -0,0 +1,60 @@ +.tabs, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 13px; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + line-height: 36px; + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/hcp/doxygen/html/template.html b/hcp/doxygen/html/template.html new file mode 100644 index 0000000..d1eb80e --- /dev/null +++ b/hcp/doxygen/html/template.html @@ -0,0 +1,87 @@ + + + + + + +Host Communication Protocol: Template handling + + + + + + + + + + + +
+
+ + + + + + +
+
Host Communication Protocol +  2.0 +
+
+
+ + + +
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+ +
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+ + + + diff --git a/hcp/hcp.doxyfile b/hcp/hcp.doxyfile new file mode 100644 index 0000000..8ba9142 --- /dev/null +++ b/hcp/hcp.doxyfile @@ -0,0 +1,2446 @@ +# Doxyfile 1.8.13 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all text +# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv +# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv +# for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "Host Communication Protocol" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = 2.0 + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify a logo or an icon that is included +# in the documentation. The maximum height of the logo should not exceed 55 +# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy +# the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. If +# left blank the current directory will be used. + +OUTPUT_DIRECTORY = doxygen + +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- +# directories (in 2 levels) under the output directory of each output format and +# will distribute the generated files over these directories. Enabling this +# option can be useful when feeding doxygen a huge amount of source files, where +# putting all generated files in the same directory would otherwise causes +# performance problems for the file system. +# The default value is: NO. + +CREATE_SUBDIRS = NO + +# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII +# characters to appear in the names of generated files. If set to NO, non-ASCII +# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode +# U+3044. +# The default value is: NO. + +ALLOW_UNICODE_NAMES = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, +# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), +# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, +# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, +# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, +# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, +# Ukrainian and Vietnamese. +# The default value is: English. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member +# descriptions after the members that are listed in the file and class +# documentation (similar to Javadoc). Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. +# The default value is: NO. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path +# before files name in the file list and in the header files. If set to NO the +# shortest path that makes the file name unique will be used +# The default value is: YES. + +FULL_PATH_NAMES = YES + +# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. +# Stripping is only done if one of the specified strings matches the left-hand +# part of the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the path to +# strip. +# +# Note that you can specify absolute paths here, but also relative paths, which +# will be relative from the directory where doxygen is started. +# This tag requires that the tag FULL_PATH_NAMES is set to YES. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the +# path mentioned in the documentation of a class, which tells the reader which +# header file to include in order to use a class. If left blank only the name of +# the header file containing the class definition is used. Otherwise one should +# specify the list of include paths that are normally passed to the compiler +# using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but +# less readable) file names. This can be useful is your file systems doesn't +# support long names like on DOS, Mac, or CD-ROM. +# The default value is: NO. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the +# first line (until the first dot) of a Javadoc-style comment as the brief +# description. If set to NO, the Javadoc-style will behave just like regular Qt- +# style comments (thus requiring an explicit @brief command for a brief +# description.) +# The default value is: NO. + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first +# line (until the first dot) of a Qt-style comment as the brief description. If +# set to NO, the Qt-style will behave just like regular Qt-style comments (thus +# requiring an explicit \brief command for a brief description.) +# The default value is: NO. + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a +# multi-line C++ special comment block (i.e. a block of //! or /// comments) as +# a brief description. This used to be the default behavior. The new default is +# to treat a multi-line C++ comment block as a detailed description. Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new +# page for each member. If set to NO, the documentation of a member will be part +# of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen +# uses this value to replace tabs by spaces in code fragments. +# Minimum value: 1, maximum value: 16, default value: 4. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that act as commands in +# the documentation. An alias has the form: +# name=value +# For example adding +# "sideeffect=@par Side Effects:\n" +# will allow you to put the command \sideeffect (or @sideeffect) in the +# documentation, which will result in a user-defined paragraph with heading +# "Side Effects:". You can put \n's in the value part of an alias to insert +# newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding "class=itcl::class" +# will allow you to use the command class in the itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for VHDL. +# The default value is: NO. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, and +# language is one of the parsers supported by doxygen: IDL, Java, Javascript, +# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran: +# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran: +# Fortran. In the later case the parser tries to guess whether the code is fixed +# or free formatted code, this is the default for Fortran type files), VHDL. For +# instance to make doxygen treat .inc files as Fortran files (default is PHP), +# and .f files as C (default is Fortran), use: inc=Fortran f=C. +# +# Note: For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = YES + +# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up +# to that level are automatically included in the table of contents, even if +# they do not have an id attribute. +# Note: This feature currently applies only to Markdown headings. +# Minimum value: 0, maximum value: 99, default value: 0. +# This tag requires that the tag MARKDOWN_SUPPORT is set to YES. + +TOC_INCLUDE_HEADINGS = 0 + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. +# The default value is: YES. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should set this +# tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); +# versus func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES will make +# doxygen to replace the get and set methods by a property in the documentation. +# This will only work if the methods are indeed getting or setting a simple +# type. If this is not the case, or you want to show the methods anyway, you +# should set this option to NO. +# The default value is: YES. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. +# The default value is: NO. + +DISTRIBUTE_GROUP_DOC = YES + +# If one adds a struct or class to a group and this option is enabled, then also +# any nested class or struct is added to the same group. By default this option +# is disabled and one has to add nested compounds explicitly via \ingroup. +# The default value is: NO. + +GROUP_NESTED_COMPOUNDS = NO + +# Set the SUBGROUPING tag to YES to allow class member groups of the same type +# (for instance a group of public functions) to be put as a subgroup of that +# type (e.g. under the Public Functions section). Set it to NO to prevent +# subgrouping. Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = YES + +# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO, +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. If set to YES, local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO, only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = YES + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = doxygen\doxygen_error.log + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = inc \ + src \ + hcp.md \ + doc/md + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, +# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf. + +FILE_PATTERNS = *.c \ + *.h \ + *.md + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = inc/fpc_host_cmd.h \ + src/fpc_host_cmd.c + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = */test/* + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = doc/md + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = doc/img + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = hcp.md + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = YES + +# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the +# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the +# cost of reduced performance. This can be particularly helpful with template +# rich C++ code for which doxygen's built-in parser lacks the necessary type +# information. +# Note: The availability of this option depends on whether or not doxygen was +# generated with the -Duse-libclang=ON option for CMake. +# The default value is: NO. + +CLANG_ASSISTED_PARSING = NO + +# If clang assisted parsing is enabled you can provide the compiler with command +# line options that you would normally use when invoking the compiler. Note that +# the include paths will already be set by doxygen for the files and directories +# specified with INPUT and INCLUDE_PATH. +# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. + +CLANG_OPTIONS = + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = YES + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = YES + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 1 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /